JPS61224431A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61224431A JPS61224431A JP6564385A JP6564385A JPS61224431A JP S61224431 A JPS61224431 A JP S61224431A JP 6564385 A JP6564385 A JP 6564385A JP 6564385 A JP6564385 A JP 6564385A JP S61224431 A JPS61224431 A JP S61224431A
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- Prior art keywords
- insulating film
- film pattern
- type
- layer
- conductivity type
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は誘電体分離構造の相補型半導体装置の製造方法
に係り、特に上記相補型半導体装置に用いられるｐ型及
びｎ型の半導体島状領域を有する誘電体分離構造の相補
型半導体基板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a complementary semiconductor device having a dielectric isolation structure, and in particular to a method for manufacturing a complementary semiconductor device having a dielectric isolation structure, and particularly to a method for manufacturing a p-type and n-type semiconductor island shape used in the complementary semiconductor device. The present invention relates to a method of manufacturing a complementary semiconductor substrate having a dielectric isolation structure having a region.
電話交換機等に用いられる半導体集積回路装置（ＩＣ）
は、雷等の高電圧ノイズに耐えるように３５０ｖ程度の
高いベース−コレクタ耐圧や素子間分離耐圧が要求され
、しかもこれらＩＣにおいては一半導体基板上にｐｎｐ
）ランジスタとｎｐｎトランジスタとが併設される必要
がある。Semiconductor integrated circuit devices (IC) used in telephone exchanges, etc.
These ICs require a high base-collector breakdown voltage of about 350V and isolation breakdown voltage between elements in order to withstand high-voltage noise such as lightning.
) A transistor and an npn transistor must be provided together.
かかる用途に応えるために提供されたのが、それぞれ誘
電体膜によって分゛離されたｐ型の半導体島状領域とｎ
型の半導体島状領域が一基板面に併設され、このｐ型半
導体島状領域にｐｎｐ）ランジスタを、又ｎ型半導体島
状領域にｎｐｎトランジスタをそれぞれ形成してなる誘
電体分離構造の相補型バイポーラＩＣである。In order to meet such applications, p-type semiconductor island regions and n-type semiconductor islands, which are separated by dielectric films, have been provided.
Complementary type of dielectric isolation structure in which a semiconductor island-like region of the type is provided on one substrate surface, a pnp) transistor is formed in the p-type semiconductor island-like region, and an npn transistor is formed in the n-type semiconductor island-like region. It is a bipolar IC.
この構造において半導体島状領域の寸法を精度良く形成
し、且つ半導体島状領域の不純物濃度を精度良く制御す
ることが集積度及び品質の安定化に必要であり、高寸法
精度が得られ、且つ製造工程中に半導体島状領域の不純
物濃度が変動することのない誘電体分離構造の相補型半
導体基板の製造方法が要望されている。In this structure, it is necessary to form the dimensions of the semiconductor island region with high precision and to control the impurity concentration of the semiconductor island region with high precision in order to stabilize the degree of integration and quality. There is a need for a method of manufacturing a complementary semiconductor substrate with a dielectric isolation structure in which the impurity concentration of the semiconductor island region does not vary during the manufacturing process.
上記誘電体分離構造の相補型半導体基板は従来、例えば
第２図（ａ）乃至（ｈｌの工程断面図を参照して述べる
下記の方法により製造されていた。The complementary semiconductor substrate having the above-mentioned dielectric isolation structure has conventionally been manufactured by, for example, the following method described with reference to process cross-sectional views of FIGS. 2(a) to (hl).
第２図（ａ）参照
即ち、先ず（１００）面を主面とする例えばｐ型シリコ
ン基板１面に、図示しない所定のマスクを介し、水酸化
カリウム溶液等を用いる公知の異方性のウェット・エッ
チング手段により第１の台形溝パターン２ａ、２ｂ、２
ｃ等を形成する。ここで台形溝の深さｔは、通常３０〜
４０μｍ程度である。Referring to FIG. 2(a), first, a well-known anisotropic wetting process using a potassium hydroxide solution or the like is applied to one surface of, for example, a p-type silicon substrate having the (100) plane as its main surface, through a predetermined mask (not shown). - First trapezoidal groove patterns 2a, 2b, 2 by etching means
Form c, etc. Here, the depth t of the trapezoidal groove is usually 30~
It is about 40 μm.
第２図（ｂ）参照
次いで上記基板１の表面に例えば二酸化シリコン（Ｓｉ
Ｏ□）膜を形成し、通常のフォトリソグラフィ技術によ
り第１の台形溝パターン２ａ、２ｂ、２ｃ等の底面上に
選択的に上記ＳｉＯ２膜よりなる第１のマスク・パター
ン３ａ、 ３ｂ、 ３ｃ等を形、成した後、イオン注入
により上記第１のマスク・パターン３ａ、 ３ｂ、 ３
ｃ等に覆われない領域にｐ″ｂ層（ｐ＋型埋没層）４を
形成する。なおこのｐ” ｂ層４は後工程でエツチング
のストッパを兼ねるので、５ Ｘｌ０Ｉ９ｅｌｌ−’以
上の極めて高濃度に形成される。Referring to FIG. 2(b), the surface of the substrate 1 is then coated with, for example, silicon dioxide (Si).
0□) film is formed, and first mask patterns 3a, 3b, 3c, etc. made of the SiO2 film are selectively formed on the bottom surfaces of the first trapezoidal groove patterns 2a, 2b, 2c, etc. using a normal photolithography technique. After forming and forming, the first mask patterns 3a, 3b, 3 are formed by ion implantation.
A p''b layer (p+ type buried layer) 4 is formed in the region not covered by the etching layer 4. Since this p''b layer 4 also serves as an etching stopper in the subsequent process, it is formed with an extremely high concentration of 5Xl0I9ell-' or higher. is formed.
第２図（Ｃ）参照
次いで上記第１のマスク・パターン３ａ、３ｂ、３ｃ等
を除去した後該基板１上に、通常の気相エピタキシャル
成長技術により、第１の台形溝パターン２ａ。Referring to FIG. 2(C), after removing the first mask patterns 3a, 3b, 3c, etc., a first trapezoidal groove pattern 2a is formed on the substrate 1 by a conventional vapor phase epitaxial growth technique.
２ｂ、２ｃ等を上部まで埋めるに十分な厚さのｎ型単結
８２９３７層５を成長させる。ここで上記ｎ型単結晶シ
リコン層５の上面には、前記第１の台形溝パターン２ａ
、２ｂ、２ｃ等を投影して第２の台形溝パターン６ａ、
６ｂ、６ｃ等が形成される。An n-type single bond 82937 layer 5 is grown to a thickness sufficient to fill layers 2b, 2c, etc. to the top. Here, on the upper surface of the n-type single crystal silicon layer 5, the first trapezoidal groove pattern 2a is formed.
, 2b, 2c, etc. to form a second trapezoidal groove pattern 6a,
6b, 6c, etc. are formed.
第２図（ｄ）参照
次いで上記ｎ型単結８９９３７層５上にＳｉ０ｇ膜を形
成した後、通常のフォトリソグラフィ技術を用いｎ型単
結８２９３７層５の上面に形成されている第２の台形溝
パターン６ａ、 ６ｂ、 ６ｃ等の底面に上記５ｉＯｚ
膜よりなる第２のマスク・パターン７ａ４ｂ。Refer to FIG. 2(d) Next, after forming an Si0g film on the n-type single-crystal 89937 layer 5, a second trapezoid is formed on the upper surface of the n-type single-crystal 82937 layer 5 using ordinary photolithography technology. The above 5iOz is applied to the bottom of the groove patterns 6a, 6b, 6c, etc.
A second mask pattern 7a4b made of a film.
７０等を形成する。Forms 70 mag.
第２図（ｅ）参照
次いで前述した公知の異方性ウェット・エッチング手段
により、上記第２のマスク・パターン７ａ。Referring to FIG. 2(e), the second mask pattern 7a is then etched by the known anisotropic wet etching means described above.
７ｂ、７ｃ等から表出しているｎ型単結８２９３７層５
をエツチングし、該ｎ型単結晶シリコン層５にｐ型半導
体基板１との界面に沿った７字型溝８ａ、８ｂ＋８ｃ、
８ｄ等を形成する。N-type single connection 82937 layer 5 exposed from 7b, 7c, etc.
7-shaped grooves 8a, 8b+8c, along the interface with the p-type semiconductor substrate 1, are formed in the n-type single crystal silicon layer 5 by etching.
8d etc. are formed.
なおこの際、前記ｐ′″ｂ層４がエツチング・ストッパ
として機能し、ｐ型シリコン基板ｌがエツチングされる
のが防止される。At this time, the p'''b layer 4 functions as an etching stopper to prevent the p-type silicon substrate l from being etched.
第２図（ｆ）参照
次いで第２のマスク・パターン７ａ、７ｂ等を除去した
後、上記７字型溝８ａ、８ｂ、８ｃ、８ｄ等の内面を含
むｎ型単結８２９３７層５及びｐ型シリコン基板■の表
面に、例えば砒素（Ａｓ” ）を前記ｐ’ ｂ層４より
低濃度にイオン注入を行って、ｎ型単結晶９９３７層５
の表面のみに、選択的にｎ” ｂ層（ｎ＋型埋没Ｎ）９
を形成する。Referring to FIG. 2(f), after removing the second mask patterns 7a, 7b, etc., the n-type single-crystal 82937 layer 5 including the inner surfaces of the 7-shaped grooves 8a, 8b, 8c, 8d, etc. For example, arsenic (As'') is ion-implanted into the surface of the silicon substrate 2 at a lower concentration than the p'b layer 4 to form an n-type single crystal 9937 layer 5.
Selective n”b layer (n+ type buried N) 9 only on the surface of
form.
第２図（ｇ）参照
次いで上記７字型溝８ａ、８ｂ、８ｃ、８ｄ等の内面を
含むｎ型単結晶９９３７層５及びｐ型シリコン基板１の
表面に、例えば熱酸化法によりＳｉＯ□よりなる分離用
絶縁膜１０を形成した後、化学気相成長法により該基板
上に、例えば５００μｍ程度の厚さに多結晶シリコン層
１１を形成する。Refer to FIG. 2(g). Next, the surfaces of the n-type single crystal 9937 layer 5 and the p-type silicon substrate 1, including the inner surfaces of the 7-shaped grooves 8a, 8b, 8c, 8d, etc., are coated with SiO□ by, for example, thermal oxidation. After forming the isolation insulating film 10, a polycrystalline silicon layer 11 is formed to a thickness of, for example, about 500 μm on the substrate by chemical vapor deposition.
第２図（ｈｌ参照
次いでｐ型シリコン基板１を底面から７字型溝８ａ、８
ｂ、８ｃ、８ｄ等の底部の分離用絶縁膜１０が表出する
まで平面研磨することによって、多結晶シリコン層１１
よりなる基板に分離用絶縁膜１０によって互いに分離さ
れた、ｐ型シリコン基板１よりなり側面及び底面にｐ″
ｂ５層４するｐ型島状領域１０１、及びｎ型単結晶９９
３７層５よりなり側面及び底面にｎ″ｂ５層９するｎ型
島状領域ＩＱ５を形成する方法である。FIG. 2 (see hl) Next, insert the p-type silicon substrate 1 into the figure-7 grooves 8a and 8 from the bottom.
The polycrystalline silicon layer 11 is polished by surface polishing until the isolation insulating film 10 at the bottom of portions b, 8c, 8d, etc. is exposed.
It consists of a p-type silicon substrate 1, which is separated from each other by an isolation insulating film 10.
b5 layer 4 p-type island region 101 and n-type single crystal 99
This is a method of forming an n-type island region IQ5 consisting of 37 layers 5 and having n''b5 layers 9 on the side and bottom surfaces.
然し上記従来の製造方法においては、第２図（ｂ）及び
ｆｄ）に示す工程において、深い台形溝２ａ、２ｂ、２
ｃ或いは６ａ、６ｂ、６ｃ等の底面に選択的にマスク・
パターン３ａ、３ｂ、３ｃ或いは７ａ、 ７ｂ、 ７ｃ
等を形成しなければならないので、該マスク膜のパター
ンニングに際してのフォトプロセスが高い段差を有する
面について行われることになる。However, in the conventional manufacturing method described above, deep trapezoidal grooves 2a, 2b, 2
Selective masking on the bottom of c or 6a, 6b, 6c, etc.
Pattern 3a, 3b, 3c or 7a, 7b, 7c
etc., the photo process for patterning the mask film is performed on a surface with a high step.
そのため上記マスク・パターン３ａ、３ｂ、３ｃ或いは
７ａ、 ７ｂ、 ？ｃ等の位置決め精度が大幅に低下す
るので、位置合わせ余裕を大きくとる必要があり、集積
度の向上が妨げられるという問題があった。Therefore, the mask patterns 3a, 3b, 3c or 7a, 7b, ? Since the positioning accuracy of items such as c is significantly reduced, it is necessary to provide a large positioning margin, which poses a problem in that improvement in the degree of integration is hindered.
又従来方法においては第２図（Ｃ）に示すｎ型単結晶半
導体Ｎ５のエピタキシャル成長が、極度に高濃度のｐ″
ｂ５層４成された後に行われるので、該エピタキシャル
成長に際しての１１００〜１１５０℃程度の高温におけ
るｐ型不純物のｐ″ｂ５層４のｎ型単結晶半導体層５内
への這い上がり拡散及びオートドーピングによって、該
ｎ型単結晶半導体層５の比抵抗の制御が困難であり、そ
のため該相補型誘電体分離基板を用いて構成される半導
体ＩＣの特性が変動するという問題もあった。Furthermore, in the conventional method, the epitaxial growth of the n-type single crystal semiconductor N5 shown in FIG.
Since this is performed after the formation of the b5 layer 4, the p-type impurity creeps up into the n-type single crystal semiconductor layer 5 of the p''b5 layer 4 at a high temperature of about 1100 to 1150°C during the epitaxial growth, and autodoping , it is difficult to control the resistivity of the n-type single crystal semiconductor layer 5, and as a result, there is a problem that the characteristics of a semiconductor IC configured using the complementary dielectric isolation substrate vary.
本発明は上記集積度の低下、及び特性の変動を防止する
目的によってなされたものである。The present invention has been made for the purpose of preventing the above-mentioned reduction in the degree of integration and variation in characteristics.
上記問題点は、（１００）面を主面とする一導電型半導
体基板面に選択的に、該半導体基板より高不純物濃度の
第１の一導電型不純物領域を下部に存する第１の絶縁膜
パターンを形成し、該第１の絶縁膜パターンをマスクに
し異方性ウェット・エッチング手段により該半導体基板
面に台形の第１の溝を形成し、該半導体基板上に反対導
電型半導体層を成長して該第１の溝に埋め込み、該第１
の絶縁膜パターン上の該半導体層を除去した後、該第１
の溝上の該半導体層上に第２の絶縁膜パターンを形成し
、該第２の絶縁膜パターン上に該第２の絶縁膜パターン
より外形寸法の小さい第３の絶縁膜パターンを形成し、
該第１及び第２の絶縁膜パターンをマスクにし異方性ウ
ェット・エッチング手段により、該半導体層に該半導体
基板との界面に沿った第２の溝を形成し、該第１及び第
２の絶縁膜パターンをマスクにし不純物を導入して該第
２の溝の内面に第２の一導電・型不純物領域を形成し、
該第３の絶縁膜パターンをマスクにし第２の絶縁膜パタ
ーンの表出領域を選択的に除去した後、該第１及び第３
の絶縁膜パターンをマスクにし異方性ウェット・エッチ
ング手段により該半導体層の表面に形成されている該第
２の一導電型不純物領域を除去し、該第３．第２．第１
の絶縁膜パターンを除去した後、該基板上全面に反対導
電型不純物を導入して該半導体層の表出面に第２の反対
導電型不純物領域を形成し、その後、該基板上全面に第
４の絶縁膜及び多結晶半導体層を形成し、該半導体基板
を底面から該第４の絶縁膜が表出するまで平面研磨する
工程を含む本発明による半導体装置の製造方法によって
解決される。The above-mentioned problem is that a first insulating film having a first one-conductivity type impurity region with a higher impurity concentration than that of the semiconductor substrate is selectively formed on the surface of the one-conductivity type semiconductor substrate whose main surface is the (100) plane. forming a trapezoidal first groove on the semiconductor substrate surface by anisotropic wet etching using the first insulating film pattern as a mask, and growing a semiconductor layer of an opposite conductivity type on the semiconductor substrate; and embed it in the first groove, and
After removing the semiconductor layer on the first insulating film pattern,
forming a second insulating film pattern on the semiconductor layer on the groove; forming a third insulating film pattern having smaller external dimensions than the second insulating film pattern on the second insulating film pattern;
A second groove is formed in the semiconductor layer along the interface with the semiconductor substrate by anisotropic wet etching using the first and second insulating film patterns as masks, and a second groove is formed in the semiconductor layer along the interface with the semiconductor substrate. introducing an impurity using the insulating film pattern as a mask to form a second one-conductivity/type impurity region on the inner surface of the second groove;
After selectively removing the exposed area of the second insulating film pattern using the third insulating film pattern as a mask, the first and third insulating film patterns are removed.
Using the insulating film pattern as a mask, the second impurity region of one conductivity type formed on the surface of the semiconductor layer is removed by anisotropic wet etching means, and the third impurity region formed on the surface of the semiconductor layer is removed. Second. 1st
After removing the insulating film pattern, an opposite conductivity type impurity is introduced into the entire surface of the substrate to form a second opposite conductivity type impurity region on the exposed surface of the semiconductor layer, and then a fourth opposite conductivity type impurity region is introduced into the entire surface of the substrate. This problem is solved by a method of manufacturing a semiconductor device according to the present invention, which includes a step of forming an insulating film and a polycrystalline semiconductor layer, and polishing the semiconductor substrate from the bottom surface until the fourth insulating film is exposed.
即ち本発明の方法においては、−導電型半導体基板に台
形溝を形成し、その表出面に高不純物濃度の一導電型埋
没層を形成しない状態で、該−導電型半導体基板上に反
対導電型単結晶半導体層のエピタキシャル成長がなされ
。従って、エピタキシャル成長に際して一導電型埋没層
から反対導電型単結晶半導体層への一導電型不純物の這
い上がり現象及びオートドーピングが生じないので、反
対導電型単結晶半導体層（エピタキシャル成長層）の比
抵抗の制御を容易且つ正確に行い得る。That is, in the method of the present invention, a trapezoidal groove is formed in a -conductivity type semiconductor substrate, and a trapezoidal groove of an opposite conductivity type is formed on the -conductivity type semiconductor substrate without forming a buried layer of one conductivity type with high impurity concentration on the exposed surface. Epitaxial growth of a single crystal semiconductor layer is performed. Therefore, during epitaxial growth, the creeping phenomenon and autodoping of impurities of one conductivity type from the buried layer of one conductivity type to the single crystal semiconductor layer of the opposite conductivity type do not occur, so that the resistivity of the single crystal semiconductor layer of the opposite conductivity type (epitaxially grown layer) is reduced. Control can be performed easily and accurately.
また−導電型島状領域と反対導電型島状領域の相対位置
を決めるマスク膜をパターンニングする際のフォトプロ
セスが、エピタキシャル成長面を平面研磨した後はぼ同
一の平面についてなされるので、高い位置決め精度が得
られる。従って位置合わせ余裕を大きくとる必要がない
ので集積度の向上が図れる。In addition, the photo process for patterning the mask film that determines the relative positions of the island-like regions of conductivity type and the opposite conductivity-type island region is performed on almost the same plane after the epitaxial growth surface is flat-polished. Accuracy is obtained. Therefore, since there is no need to provide a large positioning margin, the degree of integration can be improved.
以下本発明を第１図（ａｌ乃至（１）に示す工程断面図
を参照し一実施例について具体的に説明する。Hereinafter, one embodiment of the present invention will be specifically described with reference to process cross-sectional views shown in FIGS.
第１図（ａ）参照
本発明の方法により誘電体分離構造の相補型バイポーラ
ＩＣを製造するに際しては、（１００）面を主面とし、
例えば３０〜４０ΩＧ程度の比抵抗を有するｐ型シリコ
ン基板２１上に、
ＣＶＤ法により厚さ３０００人程度０窒化シリコン膜２
２を形成し、
通常のフォトリソグラフィ技術により該窒化シリコン膜
２２にｐ現品状領域に対応する開孔を形成し、
・該窒化シリコン膜２２
をマスクにしｌ ＸＩＱＩ＆ａｍ−”程度の注入密度で
硼素（Ｂ゛）をイオン注入し、次いで該窒化シリコン膜
２２をマスクにして選択酸化を行い、
ｐ型シリコン基板２１面のｐ現品状領域に対応する場所
に、不純物濃度ＩＱ”ａｍ−’程度の第１のｐ型不純物
導入領域、即ち第１のｐ゛型領領域２３ａ下部に有する
、厚さ１．５μｍ程度の第１の絶縁膜、即ち第１のＳｉ
Ｏ□ｉＯ！−ン２４を形成する。Refer to FIG. 1(a) When manufacturing a complementary bipolar IC with a dielectric isolation structure by the method of the present invention, the (100) plane is the main surface,
For example, on a p-type silicon substrate 21 having a specific resistance of about 30 to 40 ΩG, a silicon nitride film 2 with a thickness of about 3,000 Ω is formed by CVD.
2, and an opening corresponding to the p-type region is formed in the silicon nitride film 22 by ordinary photolithography technology,
・The silicon nitride film 22
Using the silicon nitride film 22 as a mask, boron (B) is ion-implanted at an implantation density of approximately 1XIQI&am-'', and then selective oxidation is performed using the silicon nitride film 22 as a mask to correspond to the p-type region on the p-type silicon substrate 21 surface. A first insulating film with a thickness of about 1.5 μm, which is provided under the first p-type impurity doped region 23a, that is, the first p-type region 23a, at a location where the impurity concentration is about IQ "am-". first Si
O□iO! 24.
第１図（ｂ）参照
次いで窒化シリコン膜２２を除去した後、第１のＳｉ０
ｇ膜パターン２４をマスクにし、水酸化カリウム溶液等
を用いる公知の異方性ウェット・エッチング手段により
該基板２１面をエツチングして、深さ３０〜４０μｍ程
度の台形溝パターン２５ａ、２５ｂ、２５ｃ等を形成す
る。Refer to FIG. 1(b) Next, after removing the silicon nitride film 22, the first Si0
Using the g film pattern 24 as a mask, the surface of the substrate 21 is etched by a known anisotropic wet etching method using a potassium hydroxide solution or the like to form trapezoidal groove patterns 25a, 25b, 25c, etc. with a depth of approximately 30 to 40 μm. form.
第１図（Ｃ１参照
次いでクロールシラン系のガスを用い、１１００〜１１
５０℃程度の温度で行われる通常のエピタキシャル成長
方法により、上記基板２１上に台形溝２５ａ 、 ２５
ｂ、２５ｃ等を十分に埋める例えば３５〜４５μｍ程度
の厚さに、２０Ω口程度の比抵抗を有するｎ型単結晶９
９３７層２６を成長させる。（２７は遷移領域、２８は
多結晶化領域）
なお上記ｎ型単結晶シリコン層２６の成長に際して、該
ｎ型単結晶シリコン層２６に直に接する領域は不純物濃
度の低いｐ型シリコン基板２１面であるので、ｐ型不純
物の這い上がりによってｎ型単結晶９９３７層２６の比
抵抗が大きく変動することはない。Figure 1 (see C1) Next, using a chlorosilane-based gas,
Trapezoidal grooves 25a, 25 are formed on the substrate 21 by a normal epitaxial growth method performed at a temperature of about 50°C.
N-type single crystal 9 having a specific resistance of about 20Ω and having a thickness of about 35 to 45 μm, for example, sufficiently fills the areas b, 25c, etc.
937 layers 26 are grown. (27 is a transition region, 28 is a polycrystalline region) When growing the n-type single crystal silicon layer 26, the region directly in contact with the n-type single crystal silicon layer 26 is the surface of the p-type silicon substrate 21 with a low impurity concentration. Therefore, the resistivity of the n-type single crystal 9937 layer 26 does not vary greatly due to the creeping up of p-type impurities.
第１図（ｄ）参照
次いで通常の平面研磨手段により上記ｎ型単結晶シリコ
ン層２６を、前記第１のＳｉ０ｇ膜パターン２４が表出
するまで研磨して、前記ｐ型シリコン基板２１表面の台
形溝パターン２５ａ、 ２５ｂ、 ２５ｃ等を上部まで
埋めるｎ型単結晶９９３７層パターン２６ａ、２６ｂ。Referring to FIG. 1(d), the n-type single crystal silicon layer 26 is then polished by ordinary surface polishing means until the first Si0g film pattern 24 is exposed, and the trapezoidal shape on the surface of the p-type silicon substrate 21 is polished. N-type single crystal 9937 layer patterns 26a, 26b fill the groove patterns 25a, 25b, 25c, etc. to the top.
２６ｃ等を形成し、 次いで上記ｎ型単結晶２９３７層パターン２６ａ。26c etc. are formed, Next, the n-type single crystal 2937 layer pattern 26a.
２６ｂ、２６ｃ等におけるｎ型島状領域に対応する位置
に、酸化及びリソグラフィ工程を経て前記第１のＳｉＯ
！膜２４上２４い例えば厚さ０．５μｍ程度の第２の絶
縁膜パターン、即ち第２のＳｉＯ２膜パターン２９を形
成し、
更にＣＶＤ及びリソグラフィ工程を経て上記第２のＳｉ
Ｏ□膜パターン２９上に、該第２のＳｉＯ□ｉＯ！−ン
２９より周辺が例えばＬ＝５μｍ程度後退している該第
２のＳｉ０ｇ膜パターン２９より小型の、且つ第１．第
２の絶縁膜即ち５ｉＯｔ膜とエツチングの選択性を有す
る第３の絶縁膜よりなるパターン、例えば厚さ０．２μ
ｍ程度の窒化シリコン膜パターン３０を形成する。The first SiO is formed at positions corresponding to the n-type island regions in 26b, 26c, etc. through an oxidation and lithography process.
! A second insulating film pattern 24 with a thickness of, for example, about 0.5 μm, that is, a second SiO2 film pattern 29, is formed on the film 24, and the second SiO2 film pattern 29 is further formed through a CVD and lithography process.
On the O□ film pattern 29, the second SiO□iO! - The first SiOg film pattern 29 is smaller in size than the second Si0g film pattern 29 whose periphery is set back from the second SiOg film pattern 29 by, for example, L=5 μm. A pattern consisting of a second insulating film, that is, a 5iOt film, and a third insulating film having etching selectivity, for example, a thickness of 0.2 μm.
A silicon nitride film pattern 30 having a thickness of approximately m is formed.
この工程における、ｐ現品状領域とｎ型島状領域との位
置合わせに相当する第２のＳｉＯ□膜パターン２９の位
置決めは、従来方法と異なり略同一平面上に配設されて
いる第１のＳｉＯ２膜パターン２４を基準にしてなされ
るので高い位置決め精度が得られる。従って位置合わせ
余裕を大きくとる必要がなくなり高密度配置即ち高集積
化が可能になる。In this step, the positioning of the second SiO□ film pattern 29, which corresponds to the alignment of the p-type region and the n-type island-like region, is different from the conventional method. Since this is done based on the SiO2 film pattern 24, high positioning accuracy can be obtained. Therefore, there is no need to provide a large alignment margin, and high-density arrangement, that is, high integration, becomes possible.
第１図（ｅ）参照
次いで第１の５ｉＯｚ膜パターン２４及び第２の５ｉＯ
１膜パターン２９をマスクにし、前述した異方性ウェッ
ト・エッチング手段によりｎ型単結晶９９３７層パター
ン２６ａ、 ２６ｂ、 ２６ｃ等を選択的にエツチング
し、該ｎ型単結晶２９３７層パターン２６ａ、２６ｂ、
２６Ｃ等にｐ型シリコン基板２１の界面に沿った７字型
溝３１ａ、 ３１ｂ、 ３１ｃ、 ３１ｄ等を形成し、
次いで第１のＳｉＯ□膜パターン２４及び第２の５ｉ（
ｈ膜パターン２９をマスクにし、ｌ ＸＩＱ”ａｍ−”
程度の注入密度で硼素（Ｂｏ）をイオン注入し、上記Ｖ
字型溝３１ａ、 ３１ｂ、 ３１ｃ、 ３１ｄ等の内面
に第２のｐ゛型領領域２３ｂ形成する。Referring to FIG. 1(e), the first 5iOz film pattern 24 and the second 5iOz film pattern 24 are then formed.
1 film pattern 29 as a mask, the n-type single crystal 9937 layer patterns 26a, 26b, 26c, etc. are selectively etched by the aforementioned anisotropic wet etching means to form the n-type single crystal 2937 layer patterns 26a, 26b, 26c, etc.
7-shaped grooves 31a, 31b, 31c, 31d, etc. are formed along the interface of the p-type silicon substrate 21 in 26C, etc., and
Next, the first SiO□ film pattern 24 and the second 5i (
Using h film pattern 29 as a mask, l XIQ"am-"
Boron (Bo) is ion-implanted at an implantation density of about
Second p-type regions 23b are formed on the inner surfaces of the letter-shaped grooves 31a, 31b, 31c, 31d, etc.
第１図（ｆ）参照
次いで弗酸系の液を用いる通常のウェット・エッチング
手段によりコントロール・エツチングを行い、窒化シリ
コン膜パターン３０の外に表出している薄い第２のＳｉ
Ｏ□膜パターン２９を選択的に除去する。Referring to FIG. 1(f), control etching is then performed using a conventional wet etching method using a hydrofluoric acid solution to remove the thin second Si exposed outside the silicon nitride film pattern 30.
The O□ film pattern 29 is selectively removed.
ここで、第１のＳｉＯ□膜パターン２４と第２のＳｉ０
ｇ膜パターン２９は厚さを異ならせることで第２の５ｉ
０２膜パターン２９の表出部分を完全に除去しているが
、２４と２９で異なる物質からなる絶縁膜を用いて除去
してもよい。Here, the first SiO□ film pattern 24 and the second SiO
The g film pattern 29 has a different thickness to form the second 5i
Although the exposed portion of the 02 film pattern 29 is completely removed, it may be removed using insulating films 24 and 29 made of different materials.
次いで第１のＳｉＯ□膜パターン２４及び窒化シリコン
膜パターン３０をマスクにし、前述した異方性ウェット
・エッチング手段によりｎ型単結晶９９３７層パターン
２６ａ、 ２６ｂ、 ２６ｃ等の７字型溝３１ａ、３１
ｂ。Next, using the first SiO□ film pattern 24 and silicon nitride film pattern 30 as masks, the figure-7 grooves 31a, 31 of the n-type single crystal 9937 layer patterns 26a, 26b, 26c, etc. are formed by the above-mentioned anisotropic wet etching means.
b.
３１ｃ、 ３１ｄ等の側面を選択的に更にエツチングし
て、前工程において該側面に形成されていたｐ゛型領領
域２３ｂ除去する。The side surfaces 31c, 31d, etc. are further selectively etched to remove the p'-type region 23b formed on the side surfaces in the previous step.
第１図（ｇｌ参照
次いで燐酸ボイル等の方法により窒化シリコン膜パター
ン３０を除去し、その下部の第２のＳｉＯ２膜パターン
２９及び第１のＳｉＯ□膜パターン２４を弗酸系の液に
よるウェット・エッチング手段等により除去した後、
７字型溝３１ａ、 ３１ｂ、 ３１ｃ、 ３１ｄ等の内
面を含む該基板の表出面全面に例えばｌ ＸＩＱ”ａｍ
−”程度の注入密度でｎ型不純物例えば砒素（Ａｓ”）
をイオン注入する。このイオン注入において、高不純物
濃度の第１．第２のｐ＋型領領域２３ａ、 ２３ｂに導
入されたＡｓ”はこの領域のｐ型不純物によりコンペン
セートされてしまうので、ｎ＋型領領域３２主としてｎ
型単結晶９９３７層パターン２６ａ、２６ｂ、２６ｃ等
の表出面のみに選択的に形成される。FIG. 1 (see gl) Next, the silicon nitride film pattern 30 is removed by a method such as phosphoric acid boiling, and the second SiO2 film pattern 29 and first SiO□ film pattern 24 under it are wet-treated with a hydrofluoric acid solution. After removal by etching means or the like, a layer of, for example, l
n-type impurity such as arsenic (As”) at an implantation density of about
ion implantation. In this ion implantation, the first ion implantation with high impurity concentration is performed. Since As'' introduced into the second p+ type regions 23a and 23b is compensated by the p type impurity in this region, the n+ type region 32 is mainly n
It is selectively formed only on the exposed surfaces of the type single crystal 9937 layer patterns 26a, 26b, 26c, etc.
第１図（ｈ）参照 次いで従来通り熱酸化法等により７字型溝３１ａ。See Figure 1 (h) Next, the 7-shaped groove 31a is formed by a conventional thermal oxidation method or the like.
３１ｂ、 ３１ｃ、 ３１ｄ等の内面を含むｐ型シリコ
ン基板２１及びｎ型単結晶９９３７層パターン２６ａ、
２６ｂ、２６ｃ等の表面に厚さ例えば１〜１．５μｍ程
度の分離用ＳｉＯ□絶縁膜（誘電体膜）３３を形成し、
次いで該基板上にＣＶＤ法等により厚さ５００μｍ程度
の多結晶シリコン層３４を形成する。A p-type silicon substrate 21 including inner surfaces such as 31b, 31c, 31d, etc. and an n-type single crystal 9937 layer pattern 26a,
A separation SiO□ insulating film (dielectric film) 33 having a thickness of, for example, about 1 to 1.5 μm is formed on the surfaces of 26b, 26c, etc.,
Next, a polycrystalline silicon layer 34 having a thickness of about 500 μm is formed on the substrate by CVD or the like.
第１図（ｉ）参照
次いでｐ型シリコン基板２１を底面から７字型溝３１ａ
、３１ｂ、３１ｃ、３１ｄ等の底部の分離用Ｓｉ０ｇ絶
縁膜３３が表出するまで平面研磨する。Referring to FIG. 1(i), the p-type silicon substrate 21 is then inserted into the figure-7 groove 31a from the bottom.
, 31b, 31c, 31d, etc., are polished until the isolation SiOg insulating film 33 at the bottom is exposed.
これによって、周辺部に第１及び第２のｐ゛型領領域２
３ａび２３ｂよりなるｐ゛型埋没領域ｐ″ｂを存するｐ
型半導体島状領域３５と、周辺部にｎ１型領域３２より
なるｎ゛型埋没領域ｎ″ｂを有するｎ型半導体島状領域
３６が、多結晶シリコン層３４よりなる基板に分離用Ｓ
ｉｎ、絶縁膜３３を介して分離埋設されてなる誘電体分
離構造の相補型半導体基板が完成する。As a result, the first and second p-type regions 2 are formed in the peripheral area.
3a and 23b, which has a p-type buried region p''b.
An n-type semiconductor island region 35 and an n-type semiconductor island region 36 having an n-type buried region n″b made of an n1-type region 32 at the periphery are formed on a substrate made of a polycrystalline silicon layer 34 by a separation S.
A complementary semiconductor substrate having a dielectric isolation structure in which the semiconductor substrate is separated and buried through the insulating film 33 is completed.
そして以後図示しないが、上記ｐ型半導体島状領域３５
にｐｎｐトランジスタが、ｎ型半導体島状領域３６にｎ
ｐｎ ）ランジスタが形成され所望配線等がなされて誘
電体分離構造の相補型ＩＣが完成する。Although not shown hereafter, the p-type semiconductor island region 35
A pnp transistor is provided in the n-type semiconductor island region 36.
pn) A transistor is formed and desired wiring etc. are made to complete a complementary IC with a dielectric isolation structure.
以上実施例の説明の中で述べたように、本発明の方法に
よれば、基板と反対導電型の島状領域となる反対導電型
単結晶半導体層を一導電型半導体基板上にエピタキシャ
ル成長する際、該エピタキシャル層と接する領域に一導
電型半導体島状領域の埋没層となる高濃度の一導電型層
が形成されていない。As described above in the description of the embodiments, according to the method of the present invention, when epitaxially growing a single crystal semiconductor layer of an opposite conductivity type, which becomes an island-like region of a conductivity type opposite to that of the substrate, on a semiconductor substrate of one conductivity type, , a high concentration layer of one conductivity type which becomes a buried layer of a semiconductor island-like region of one conductivity type is not formed in a region in contact with the epitaxial layer.
従ってエピタキシャル成長時に該反対導電型のエピタキ
シャル層に、−導電型不純物の這い上がり及びオートド
ーピングが殆ど生じないので、該エピタキシャル層の比
抵抗の制御は極めて容易に且つ正確に行えるようになる
。Therefore, during epitaxial growth, creeping up of -conductivity type impurities and autodoping hardly occur in the epitaxial layer of the opposite conductivity type, so that the resistivity of the epitaxial layer can be controlled extremely easily and accurately.
またｐ型島状領域とｎ型島状領域の相対位置を決める際
のフォトプロセスが、はぼ同一の平面上で行われる。Further, a photo process for determining the relative positions of the p-type island region and the n-type island region is performed on almost the same plane.
従って位置決めの精度が向上し位置合わせ余裕が少なく
て済むので、ｐ型島状領域とｎ型島状領域を従来より接
近させて高密度に配設することが可能になる。Therefore, the accuracy of positioning is improved and the positioning margin is reduced, making it possible to arrange the p-type island region and the n-type island region closer to each other and with higher density than before.
以上の点から本発明は誘電体分離構造の相補型ＩＣの集
積度を向上し、その品質を安定化せしめるうえに有効で
ある。From the above points, the present invention is effective in improving the degree of integration of complementary ICs having a dielectric isolation structure and stabilizing their quality.
第１図（ａ）乃至（ｉｌは本発明の方法の一実施例を示
す工程断面図で、
第２図（ａ）乃至（ｈ）は従来方法を示す工程断面図で
ある。
図において、
２１はｐ型シリコン基板、
２２は窒化シリコン膜、
２３ａ、２３ｂはｐ＋型領領域
２４は第１のＳｉ０ｇ膜パターン、
２５ａ、 ２５ｂ、 ２５ｃは台形溝パターン、２６は
ｎ型単結晶シリコン層、
２６ａ、 ２６ｂ、 ２６ｃは単結晶シリコン層パター
ン、２９は第２のＳｉ０ｇ膜パターン、
３０は窒化シリコン膜パターン、
３１ａ、 ３１ｂ、 ３１ｃ、 ３１ｄはＶ字型溝、３
２はｎ１型領域、
３３は分離用ＳｉＯ□絶縁膜、
３４は多結晶シリコン層、
ｐ” ｂはｐ゛型埋没層、
ｎ”ｂはｎ＋＋埋没層
を示す。
穿 １ 図
享 １ 口
茅 ２ ａFIGS. 1(a) to (il) are process cross-sectional views showing one embodiment of the method of the present invention, and FIGS. 2(a) to (h) are process cross-sectional views showing a conventional method. In the figures, 21 22 is a p-type silicon substrate, 22 is a silicon nitride film, 23a, 23b is a p + type region 24 is a first SiOg film pattern, 25a, 25b, 25c is a trapezoidal groove pattern, 26 is an n-type single crystal silicon layer, 26a, 26b and 26c are single crystal silicon layer patterns, 29 is a second SiOg film pattern, 30 is a silicon nitride film pattern, 31a, 31b, 31c, and 31d are V-shaped grooves;
2 is an n1 type region, 33 is an isolation SiO□ insulating film, 34 is a polycrystalline silicon layer, p''b is a p'' type buried layer, and n''b is an n++ buried layer. Perforation 1 Illustration 1 Kuchihaya 2 a
Claims (1)
択的に、該半導体基板より高不純物濃度の第１の一導電
型不純物領域を下部に有する第１の絶縁膜パターンを形
成し、 該第１の絶縁膜パターンをマスクにし異方性ウェット・
エッチング手段により該半導体基板面に台形の第１の溝
を形成し、 該半導体基板上に反対導電型半導体層を成長して該第１
の溝に埋め込み、 該第１の絶縁膜パターン上の該半導体層を除去した後、
該第１の溝上の該半導体層上に第２の絶縁膜パターンを
形成し、 該第２の絶縁膜パターン上に該第２の絶縁膜パターンよ
り外形寸法の小さい第３の絶縁膜パターンを形成し、 該第１及び第２の絶縁膜パターンをマスクにし異方性ウ
ェット・エッチング手段により、該半導体層に該半導体
基板との界面に沿った第２の溝を形成し、 該第１及び第２の絶縁膜パターンをマスクにし不純物を
導入して該第２の溝の内面に第２の一導電型不純物領域
を形成し、 該第３の絶縁膜パターンをマスクにし第２の絶縁膜パタ
ーンの表出領域を選択的に除去した後、該第１及び第３
の絶縁膜パターンをマスクにし異方性ウェット・エッチ
ング手段により該半導体層の表面に形成されている該第
２の一導電型不純物領域を除去し、 該第３、第２、第１の絶縁膜パターンを除去した後、該
基板上全面に反対導電型不純物を導入して該半導体層の
表出面に第２の反対導電型不純物領域を形成し、 その後、該基板上全面に第４の絶縁膜及び多結晶半導体
層を形成し、 該半導体基板を底面から該第４の絶縁膜が表出するまで
平面研磨する工程を含むことを特徴とする半導体装置の
製造方法。[Scope of Claims] A first insulator having a first one-conductivity type impurity region with a higher impurity concentration than the semiconductor substrate selectively on the surface of the one-conductivity type semiconductor substrate whose main surface is the [100] plane. A film pattern is formed, and an anisotropic wet film is applied using the first insulating film pattern as a mask.
forming a trapezoidal first groove on the surface of the semiconductor substrate by etching means; growing a semiconductor layer of an opposite conductivity type on the semiconductor substrate;
After removing the semiconductor layer on the first insulating film pattern,
forming a second insulating film pattern on the semiconductor layer on the first trench; and forming a third insulating film pattern smaller in external dimension than the second insulating film pattern on the second insulating film pattern. forming a second groove along the interface with the semiconductor substrate in the semiconductor layer by anisotropic wet etching using the first and second insulating film patterns as masks; Using the second insulating film pattern as a mask, impurities are introduced to form a second one-conductivity type impurity region on the inner surface of the second groove, and using the third insulating film pattern as a mask, impurities are introduced into the second insulating film pattern. After selectively removing the exposed area, the first and third
removing the second impurity region of one conductivity type formed on the surface of the semiconductor layer by anisotropic wet etching using the insulating film pattern as a mask; After removing the pattern, an opposite conductivity type impurity is introduced over the entire surface of the substrate to form a second opposite conductivity type impurity region on the exposed surface of the semiconductor layer, and then a fourth insulating film is introduced over the entire surface of the substrate. and forming a polycrystalline semiconductor layer, and planarly polishing the semiconductor substrate until the fourth insulating film is exposed from the bottom surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6564385A JPS61224431A (en) | 1985-03-29 | 1985-03-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6564385A JPS61224431A (en) | 1985-03-29 | 1985-03-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61224431A true JPS61224431A (en) | 1986-10-06 |
Family
ID=13292898
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6564385A Pending JPS61224431A (en) | 1985-03-29 | 1985-03-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61224431A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4820653A (en) * | 1988-02-12 | 1989-04-11 | American Telephone And Telegraph Company | Technique for fabricating complementary dielectrically isolated wafer |
| US4925808A (en) * | 1989-03-24 | 1990-05-15 | Sprague Electric Company | Method for making IC die with dielectric isolation |
-
1985
- 1985-03-29 JP JP6564385A patent/JPS61224431A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4820653A (en) * | 1988-02-12 | 1989-04-11 | American Telephone And Telegraph Company | Technique for fabricating complementary dielectrically isolated wafer |
| US4925808A (en) * | 1989-03-24 | 1990-05-15 | Sprague Electric Company | Method for making IC die with dielectric isolation |
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