JPS61214870A - Solid-state image pickup device - Google Patents
Solid-state image pickup deviceInfo
- Publication number
- JPS61214870A JPS61214870A JP60056403A JP5640385A JPS61214870A JP S61214870 A JPS61214870 A JP S61214870A JP 60056403 A JP60056403 A JP 60056403A JP 5640385 A JP5640385 A JP 5640385A JP S61214870 A JPS61214870 A JP S61214870A
- Authority
- JP
- Japan
- Prior art keywords
- solid
- time
- gate
- picture elements
- image pickup
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Transforming Light Signals Into Electric Signals (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、電子シャッタ機能を有する新規な固体撮像
装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a novel solid-state imaging device having an electronic shutter function.
第３図は例えば従来のＭＯＳ型固体撮像装置を示す回路
図である。図において、１，２．３はフローティングソ
ース部がそれぞれ受光部１０１〜１０３．２０１〜２０
３．３０１〜３０３を形成する第１のＭＯＳトランジス
タ、４は第３のＭＯＳトランジスタ、２１．２２．２３
は垂直信号線であり、各々第１のＭＯＳトランジスタ１
．２゜３のドレインと第３のＭＯＳトランジスタ４のソ
ース側とを接続しているものである。また５は垂直走査
回路、３１，３２．３３は垂直走査回路５の信号を第１
のＭｏ３トランジスタ１，２．３のゲートに伝える垂直
走査線、６は水平走査回路、４１．４２．４３は水平走
査回路６の信号を第３のＭｏ３Ｉ−ランジスタ４の各ゲ
ートに伝える水平走査線である。FIG. 3 is a circuit diagram showing, for example, a conventional MOS type solid-state imaging device. In the figure, floating source parts 1, 2.3 are light receiving parts 101 to 103, and 201 to 20, respectively.
3. The first MOS transistor forming 301 to 303, 4 the third MOS transistor, 21.22.23
are vertical signal lines, each of which connects the first MOS transistor 1
．． The drain of the MOS transistor 2.3 is connected to the source side of the third MOS transistor 4. 5 is a vertical scanning circuit; 31, 32, and 33 are signals of the vertical scanning circuit 5;
6 is a horizontal scanning circuit, 41, 42, 43 is a horizontal scanning line that transmits the signal of the horizontal scanning circuit 6 to each gate of the third Mo3I transistor 4. It is.
次に動作について説明する。各画素の受光部１０１〜１
０３．２０１〜２０３，３０１〜３０３は光電変換を行
ない、これにより受光部には２次元情報が電気信号とし
て蓄積されている。そこで各画素の受光部からの信号を
順次読出すために、垂直、水平走査回路５，６により以
下の順に各第１、第３のＭｏ３Ｉ−ランジスタを順次オ
ンさせる。Next, the operation will be explained. Light receiving section 101-1 of each pixel
03. 201 to 203 and 301 to 303 perform photoelectric conversion, whereby two-dimensional information is stored in the light receiving section as an electrical signal. Therefore, in order to sequentially read out signals from the light receiving portion of each pixel, the vertical and horizontal scanning circuits 5 and 6 sequentially turn on each of the first and third Mo3I transistors in the following order.
即ち、まず受光部１０１〜１０３の情報を取り出すため
に垂直走査回路５の垂直走査線３１をハイレベルにする
と、各垂直信号線２１〜２３に各々の受光部１０１〜１
０３に対応した信号が転送される。次に水平走査回路６
より出ている各走査線４１〜４３を順次垂直信号線２１
に対応した側からハイレベルにすることにより、出力端
子５０には受光部１０１，１０２，１０３の電気信号が
順次読出されることになる。That is, first, when the vertical scanning line 31 of the vertical scanning circuit 5 is set to a high level in order to extract information from the light receiving sections 101 to 103, each of the light receiving sections 101 to 1 is connected to each vertical signal line 21 to 23.
The signal corresponding to 03 is transferred. Next, the horizontal scanning circuit 6
The scanning lines 41 to 43 coming out from the vertical signal line 21 are sequentially connected to the vertical signal line 21.
By setting the level to high from the side corresponding to , the electrical signals of the light receiving sections 101, 102, and 103 are sequentially read out to the output terminal 50.
次に垂直走査線３２をハイレベルにし、各受光部２０１
〜２０３に蓄積された信号を垂直信号線２１．２２．２
３にそれぞれ転送し、その後水平走査回路６により順次
重３のＭｏ３トランジスタ４のゲートを１ケ毎にオンす
ることにより、各画素の信号が読出される。以下、受光
部３０１〜３０３についても以上と同様の走査を行なう
ことにより、その蓄積信号を順次読出すことができる。Next, the vertical scanning line 32 is set to high level, and each light receiving section 201
〜203 to the vertical signal line 21.22.2
After that, the horizontal scanning circuit 6 sequentially turns on the gates of the Mo3 transistors 4 of each pixel, thereby reading out the signal of each pixel. Thereafter, by performing the same scanning as above for the light receiving sections 301 to 303, the accumulated signals can be sequentially read out.
従来の固体撮像装置は以上のように構成されており、単
に光電変換及び該光電変換信号の読出し機能しか持たな
いために、電子スチルカメラを構成するときには機械式
シャッタを使用しなければならず、カメラの小型化を図
る上で問題があった。Conventional solid-state imaging devices are configured as described above, and because they only have the function of photoelectric conversion and reading out the photoelectric conversion signal, a mechanical shutter must be used when constructing an electronic still camera. There was a problem in trying to make the camera smaller.
この発明は、上記のような問題点を解消するためになさ
れたもので、小型で軽量な電子スチルカメラを構成する
ことが可能な固体撮像装置を得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a solid-state imaging device that can constitute a small and lightweight electronic still camera.
この発明に係る固体撮像装置は、固体撮像素子の各画素
内に、受光部の他に該受光部に蓄積された電荷が転送さ
れる蓄積部を設けたものである。The solid-state imaging device according to the present invention includes, in each pixel of the solid-state imaging element, in addition to the light receiving section, an accumulation section to which charges accumulated in the light receiving section are transferred.
この発明においては、固体撮像素子の各画素が蓄積部を
有しているから、画素がリセットされてから受光部の電
荷が蓄積部に転送されるまでの時間を変えることにより
、逼像期間を電子的に変えることができ、シャッタ機能
が電子的に実現される。In this invention, since each pixel of the solid-state image sensor has an accumulation section, the imaging period can be shortened by changing the time from when the pixel is reset until the charge in the light receiving section is transferred to the accumulation section. It can be changed electronically and the shutter function is implemented electronically.
以下、本発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施例による固体撮像装置を示す
回路図で、ここでは２×２画素構成の例を示す。また第
２図は本実施例の動作Ｒ）レス図である。第１図におい
て、４０は固体撮像素子であり、該素子４０において、
７はフローティングソース部が受光部１６となる第１の
ＭＯＳトランジスタ、８はソースが第１のＭｏ５トラン
ジスタフのドレインと接続された第２のＭｏＳトランジ
スタで、該ソース部が蓄積部１７を構成する。９は第３
のＭｏ３トランジスタで、ソースが垂直信号線２０を介
して第２のＭｏ３トランジスタ８のドレインと接続され
る。また１３．１４．１５はトランジスタ７〜９の各ゲ
ートを駆動するための第１〜第３の走査回路（ゲート回
路）であり、３０は外部の増幅器、６０は直流電源であ
る。また１０は第１のＭｏ３トランジスタフのゲートと
第１の走査回路１３とを接続する第１の走査線、１１は
第２のＭｏ３トランジスタ８のゲートと第２の・走査回
路１４とを接続する第２の走査線、１２は第３のＭｏ３
トランジスタ９のゲートと第３の走査回路１５とを接続
する第３の走査線である。FIG. 1 is a circuit diagram showing a solid-state imaging device according to an embodiment of the present invention, and here an example of a 2×2 pixel configuration is shown. Further, FIG. 2 is a diagram showing the operation of this embodiment. In FIG. 1, 40 is a solid-state imaging device, and in this device 40,
7 is a first MOS transistor whose floating source part becomes the light receiving part 16; 8 is a second MoS transistor whose source is connected to the drain of the first Mo5 transistor; the source part forms the storage part 17; . 9 is the third
The source of the Mo3 transistor is connected to the drain of the second Mo3 transistor 8 via the vertical signal line 20. Further, 13, 14, and 15 are first to third scanning circuits (gate circuits) for driving each gate of the transistors 7 to 9, 30 is an external amplifier, and 60 is a DC power supply. Further, 10 is a first scanning line connecting the gate of the first Mo3 transistor 8 and the first scanning circuit 13, and 11 is connecting the gate of the second Mo3 transistor 8 and the second scanning circuit 14. Second scanning line, 12 is the third Mo3
This is a third scanning line that connects the gate of the transistor 9 and the third scanning circuit 15.
なお、本実施例では第２の走査回路１４が第３図の垂直
走査回路５に、第３の走査回路１５が第３図の水平走査
回路６にそれぞれ対応するものである。In this embodiment, the second scanning circuit 14 corresponds to the vertical scanning circuit 5 of FIG. 3, and the third scanning circuit 15 corresponds to the horizontal scanning circuit 6 of FIG. 3.
第２図は本実施例の第１〜第３のＭＯＳトランジスタに
印加されるゲートパルスａ ”−’ ｃに対応したタイ
ミング図であり、ｔｌはリセット状態、ｔ２は電子シャ
ッタ動作時、ｔ３は各トランジスタの信号読み出し時の
各時刻を示す。FIG. 2 is a timing chart corresponding to the gate pulses a''-'c applied to the first to third MOS transistors of this embodiment, where tl is in the reset state, t2 is in the electronic shutter operation, and t3 is in each case. Each time point when reading a signal from a transistor is shown.
刻ｔｌ（撮像開始時）においてリセットパルスを発生し
第１〜第３のＭＯＳトランジスタフ〜９のゲートをオン
し、全ての単位画素の受光部１６と蓄積部１７とをリセ
ットすることにより、イニシャル状態を設定する。こう
することにより所望のシャッタ時間、即ち（ｔ２−ｔｌ
）の間に入射した光により生成された光キャリアが第１
のＭＯＳトランジスタ７の受光部１６に蓄えられる。次
に第１の走査回路１３は時刻ｔ２においてシャッタパル
スを発生し、第１のＭＯＳトランジスタ７のゲートのみ
を全ての画素について一度にオンする。At time tl (at the start of imaging), a reset pulse is generated, the gates of the first to third MOS transistors are turned on, and the light receiving section 16 and storage section 17 of all unit pixels are reset. Set state. By doing this, the desired shutter time, i.e. (t2-tl
) The photocarriers generated by the light incident between
The light is stored in the light receiving section 16 of the MOS transistor 7. Next, the first scanning circuit 13 generates a shutter pulse at time t2, and turns on only the gate of the first MOS transistor 7 for all pixels at once.
こうすることにより、該シャッタ時刻ｔ２において、受
光部１６に蓄積されている電荷に比例した電荷が蓄積部
１７に転送される。By doing this, at the shutter time t2, charges proportional to the charges accumulated in the light receiving section 16 are transferred to the accumulation section 17.
次に従来例で述べたのと同様に、第２．第３の走査回路
１４．１５は上記全ての画素を走査するために第２．第
３のＭＯＳトランジスタ８，９のゲートを順次オンする
読出しパルスを発生し、これにより時刻ｔ３１から順次
各画素のデータが読出される。即ち、時刻ｔ３１におい
て第２の走査線１１ａがハイレベルとなり、蓄積部１７
ａ、１７ｂの電荷がそれぞれ垂直信号線’ｌ Ｑ ａ、
’ｌ Ｏｂに転送される。そして時刻ｔ３１１にお
いてＭＯＳトランジスタ９ａがオンされて信号線２０ａ
の電荷が外部に読出され、次に時刻ｔ３１２において信
号線２０ｂの電荷が外部に読出される。そしてさらに時
刻ｔ３２において第２の走査線１１ｂがハイレベルとな
り、以下上記と同様にして残りの各画素の信号が読出さ
れる。なお、本実施例において、露光時間を変えたいと
きは、シャッタ時間（ｔ２−ｔｌ）を変えればよく、こ
うすることにより該露光時間を自由に設定することがで
きる。Next, in the same way as described in the conventional example, the second. The third scanning circuit 14.15 is connected to the second scanning circuit 14.15 in order to scan all the pixels mentioned above. A read pulse is generated to sequentially turn on the gates of the third MOS transistors 8 and 9, and thereby the data of each pixel is sequentially read from time t31. That is, at time t31, the second scanning line 11a becomes high level, and the storage section 17
The charges of a and 17b are respectively connected to the vertical signal line 'l Q a,
'l Transferred to Ob. Then, at time t311, the MOS transistor 9a is turned on and the signal line 20a is turned on.
The charge on the signal line 20b is read out to the outside, and then at time t312, the charge on the signal line 20b is read out to the outside. Further, at time t32, the second scanning line 11b becomes high level, and the signals of the remaining pixels are read out in the same manner as described above. In this embodiment, when it is desired to change the exposure time, it is sufficient to change the shutter time (t2-tl), and by doing so, the exposure time can be set freely.
なお、上記実施例では２×２の２次元面体撮像装置を例
にとって説明したが、本発明は上記画素数に限定される
ものではなく、１次元の固体撮像装置や、より多くの画
素を有する２次元の固体撮像装置にも通用できるもので
ある。In addition, although the above embodiment has been explained using a 2×2 two-dimensional surface solid imaging device as an example, the present invention is not limited to the above number of pixels, and can be applied to a one-dimensional solid-state imaging device or a one-dimensional solid-state imaging device having a larger number of pixels. This can also be applied to two-dimensional solid-state imaging devices.
以上のように、この発明に係る固体撮像装置によれば、
受光部のほかに各画素に電荷蓄積部を別途設けたので、
電子スチルカメラのメカニカルシャッタに対応する・電
子シャ・ツタ機能を固体撮像装置内に持たせることが可
能となり、電子スチルカメラを小型、軽量に構成するこ
とが可能となる効果がある。As described above, according to the solid-state imaging device according to the present invention,
In addition to the light receiving section, each pixel has a separate charge storage section, so
It becomes possible to provide an electronic shutter function corresponding to the mechanical shutter of an electronic still camera in a solid-state imaging device, and there is an effect that the electronic still camera can be configured to be small and lightweight.
【図面の簡単な説明】
第１図は本発明の一実施例による固体撮像装置の回路図
、第２図は第１図の装置のタイミング図、第３図は従来
の固体撮像装置の回路図である。
１〜４．７．８．９−Ｍ０３トランジスタ、１６．１０
１〜１０３．２０１〜２０３．３０１〜３０３・・・受
光部、１７・・・蓄積部、３１〜３３．４１〜４３，１
０．１１．．１２・・・走査線、２０．２１〜２３・・
・垂直信号線、５．６．１３，１４．１５・・・走査回
路（ゲート回路）、４０・・・固体撮像素子、５０・・
・出力端子、６０・・・直流電源。
第１図
Ｌ
第２図[Brief Description of the Drawings] Fig. 1 is a circuit diagram of a solid-state imaging device according to an embodiment of the present invention, Fig. 2 is a timing diagram of the device shown in Fig. 1, and Fig. 3 is a circuit diagram of a conventional solid-state imaging device. It is. 1-4.7.8.9-M03 transistor, 16.10
1-103.201-203.301-303...Light receiving section, 17...Storage section, 31-33.41-43,1
0.11. ．． 12...Scanning line, 20.21-23...
・Vertical signal line, 5.6.13, 14.15...Scanning circuit (gate circuit), 40...Solid-state image sensor, 50...
・Output terminal, 60...DC power supply. Figure 1 L Figure 2
Claims (2)
タと該第１のＭＯＳトランジスタのドレインに直結され
蓄積機能を有するソース（以下蓄積部と称す）を持つ第
２のＭＯＳトランジスタとからる単位画素を１次元また
は２次元的に配置し上記第２のＭＯＳトランジスタのド
レインが第３のＭＯＳトランジスタのソースに接続され
てなる固体撮像素子と、上記第１ないし第３のＭＯＳト
ランジスタをそれぞれオンするための第１ないし第３の
ゲート回路とを備えたことを特徴とする固体撮像装置。(1) A unit consisting of a first MOS transistor whose source part serves as a light receiving part and a second MOS transistor which has a source (hereinafter referred to as an accumulation part) that is directly connected to the drain of the first MOS transistor and has a storage function. A solid-state image sensor having pixels arranged one-dimensionally or two-dimensionally and a drain of the second MOS transistor connected to a source of a third MOS transistor, and each of the first to third MOS transistors are turned on. What is claimed is: 1. A solid-state imaging device comprising: first to third gate circuits.
に上記第１ないし第３のＭＯＳトランジスタを全てオン
するリセットパルスを発生し、その後該第１のゲート回
路は、該第１のＭＯＳトランジスタを全てオンするシャ
ッタパルスを発生し、その後該第２、第３のゲート回路
は、上記全ての単位画素を走査するために上記第２、第
３のＭＯＳトランジスタを順次オンする読出しパルスを
発生することを特徴とする特許請求の範囲第１項記載の
固体撮像装置。(2) The first to third gate circuits generate a reset pulse that turns on all the first to third MOS transistors at the start of imaging, and then the first gate circuit generates a reset pulse that turns on all of the first to third MOS transistors. A shutter pulse that turns on all the transistors is generated, and then the second and third gate circuits generate read pulses that sequentially turn on the second and third MOS transistors in order to scan all of the unit pixels. A solid-state imaging device according to claim 1, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60056403A JPS61214870A (en) | 1985-03-20 | 1985-03-20 | Solid-state image pickup device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60056403A JPS61214870A (en) | 1985-03-20 | 1985-03-20 | Solid-state image pickup device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61214870A true JPS61214870A (en) | 1986-09-24 |
Family
ID=13026210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60056403A Pending JPS61214870A (en) | 1985-03-20 | 1985-03-20 | Solid-state image pickup device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61214870A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62290278A (en) * | 1986-06-10 | 1987-12-17 | Hitachi Ltd | Electronic still camera |
| JPS63161780A (en) * | 1986-12-25 | 1988-07-05 | Hamamatsu Photonics Kk | Solid-state image pickup element |
| JPS63161784A (en) * | 1986-12-25 | 1988-07-05 | Hamamatsu Photonics Kk | Solid-state image pickup element |
| JPS63253485A (en) * | 1987-04-09 | 1988-10-20 | Nippon Denso Co Ltd | Optical information reading device |
| JPH0456483A (en) * | 1990-06-25 | 1992-02-24 | Koji Eto | Video camera equipped with mos type imaging device |
| US5159677A (en) * | 1988-11-21 | 1992-10-27 | International Business Machines Corp. | Method and system for storing data in and retrieving data from a non-main storage virtual data space |
| US5274459A (en) * | 1991-04-10 | 1993-12-28 | Sony Corporation | Solid state image sensing device with a feedback gate transistor at each photo-sensing section |
| US6549234B1 (en) | 1998-06-09 | 2003-04-15 | Hyundai Electronics Industries Co., Ltd. | Pixel structure of active pixel sensor (APS) with electronic shutter function |
-
1985
- 1985-03-20 JP JP60056403A patent/JPS61214870A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62290278A (en) * | 1986-06-10 | 1987-12-17 | Hitachi Ltd | Electronic still camera |
| JPS63161780A (en) * | 1986-12-25 | 1988-07-05 | Hamamatsu Photonics Kk | Solid-state image pickup element |
| JPS63161784A (en) * | 1986-12-25 | 1988-07-05 | Hamamatsu Photonics Kk | Solid-state image pickup element |
| JPH0511830B2 (en) * | 1986-12-25 | 1993-02-16 | Hamamatsu Photonics Kk | |
| JPH0511829B2 (en) * | 1986-12-25 | 1993-02-16 | Hamamatsu Photonics Kk | |
| JPS63253485A (en) * | 1987-04-09 | 1988-10-20 | Nippon Denso Co Ltd | Optical information reading device |
| US5159677A (en) * | 1988-11-21 | 1992-10-27 | International Business Machines Corp. | Method and system for storing data in and retrieving data from a non-main storage virtual data space |
| JPH0456483A (en) * | 1990-06-25 | 1992-02-24 | Koji Eto | Video camera equipped with mos type imaging device |
| US5274459A (en) * | 1991-04-10 | 1993-12-28 | Sony Corporation | Solid state image sensing device with a feedback gate transistor at each photo-sensing section |
| US6549234B1 (en) | 1998-06-09 | 2003-04-15 | Hyundai Electronics Industries Co., Ltd. | Pixel structure of active pixel sensor (APS) with electronic shutter function |
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