JPS61212069A - Gaas field effect transistor - Google Patents
Gaas field effect transistorInfo
- Publication number
- JPS61212069A JPS61212069A JP5222685A JP5222685A JPS61212069A JP S61212069 A JPS61212069 A JP S61212069A JP 5222685 A JP5222685 A JP 5222685A JP 5222685 A JP5222685 A JP 5222685A JP S61212069 A JPS61212069 A JP S61212069A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- source
- gaas
- field effect
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 230000003321 amplification Effects 0.000 abstract description 3
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- IUVCFHHAEHNCFT-INIZCTEOSA-N 2-[(1s)-1-[4-amino-3-(3-fluoro-4-propan-2-yloxyphenyl)pyrazolo[3,4-d]pyrimidin-1-yl]ethyl]-6-fluoro-3-(3-fluorophenyl)chromen-4-one Chemical compound C1=C(F)C(OC(C)C)=CC=C1C(C1=C(N)N=CN=C11)=NN1[C@@H](C)C1=C(C=2C=C(F)C=CC=2)C(=O)C2=CC(F)=CC=C2O1 IUVCFHHAEHNCFT-INIZCTEOSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
- H01L29/8124—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate with multiple gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明はＧａＡｓ 半導体装置、４９に双ゲートＧａ
ＡｓＦＥＴ（デュアルゲート電界効果トランジスタ）に
関する。[Detailed Description of the Invention] [Technical Field] The present invention relates to a GaAs semiconductor device, a dual gate Ga
Regarding AsFET (dual gate field effect transistor).
テレビジョンのチェーナ用として、低雑音性。 Low noise for use in television channels.
電力利得性、あるいは耐サージ性のよい双ゲート型のＧ
ａＡｓＦＥＴが使われている。Twin gate type G with good power gain or surge resistance
aAsFET is used.
このＧａＡｓＦＥＴは、第３図に示すようＫ、半絶縁性
Ｇａ Ａｓ基板１上Ｋ、たとえばｎ型のアクティブ層２
を形成し、このｎ型層２上にシ璽ットキ・バリアをつく
る金属、たとえばＡ１よりなる第１ゲー）Ｇ、、第２ゲ
ーｈＧｔを並べて設け、これら２つのゲートを挾んで上
記ｎ型層にオーミックコンタクトするソース（Ｓ）・ド
レイン（至）電極を設けた構造を有し、第１ゲートＧＩ
への信号入力によって、直下のチャネルｎ型層２の空乏
層を変えてソース・ドレイン電流を制御するものである
。一方、第２ゲートＧ、は可変抵抗として使用される。As shown in FIG.
On this n-type layer 2, a first gate (G) and a second gate (hGt) made of metal, for example A1, which form a barrier are provided side by side, and these two gates are sandwiched between the above n-type layer It has a structure in which source (S) and drain (to) electrodes are provided in ohmic contact with the first gate GI.
By inputting a signal to the channel, the depletion layer of the channel n-type layer 2 immediately below is changed to control the source-drain current. On the other hand, the second gate G is used as a variable resistor.
（ＮＥＣ技報、 Ｖｏｌ ３６．ｔＶｋＬ１２／１９８
３．ｐ６〜ｐ９［低雑音ＧａＡｓＦＥＴＪ参照）
このようなＧａＡｓＦＥＴｒにおける増幅率ｇｍ特性は
、第２図のドレイン電流Ｉｄ、ゲート・ンース電圧ＹＧ
ｓ曲線で示されるように、第１ゲートＧＩは急峻な曲線
形状がのぞましく、一方、第２ゲートＧ、はなだらかな
スローカットオフの形状がのぞましい。(NEC Technical Report, Vol 36.tVkL12/198
3. p6 to p9 [Refer to low-noise GaAsFETJ] The amplification factor gm characteristics in such a GaAsFETr are as follows: drain current Id, gate-to-source voltage YG
As shown by the s curve, the first gate GI preferably has a steep curved shape, while the second gate G preferably has a gentle slow cutoff shape.
従来のスゲ−） ＧａＡｓ Ｆ Ｅ Ｔにおいては、第
３図に示されるように第１ゲート長ｎｇｔと第２ゲート
長Ａｇｔとを同寸法（ｌ ｇｔ ＝−８ｇｔ ）とする
か、又は、第４図に示されるようにＭＯＳＦＥＴの帰還
容量ＣＲ５５を小さくするため！ｇ、を大きくＣｌ５ｇ
ρ１ｇｍ）したものが利用されている。なおゲート幅は
第１ゲートと第２ゲートが同寸法であるとする。In the conventional GaAs FET, as shown in FIG. To reduce the feedback capacitance CR55 of the MOSFET as shown in the figure! g, increase Cl5g
ρ1gm) is used. It is assumed that the first gate and the second gate have the same gate width.
しかし、１３ｇｔを大きくすることは第２ゲートＧ、に
よってソース・ドレイン電流ＩＤ５Ｓ（ＩＤＳＳは、第
１ゲート拳ソース間電圧、第２ゲート−ソース間電圧が
ともに零である時のソース・ドレイン電流である。）が
大幅に制限され、Ｉ Ｉ）ｓｓ状態での９ｍが大幅に低
下する。また、ドレイン電流ＩＤの第２ゲート・ソース
電圧ＶＧ、Ｓ依存性が極めて大きくなり、パワゲインＰ
Ｇ（ＪｉＦｍと等価）のｖｃ、Ｓ依存性が急峻となって
ドレイン電流の制御が難しくなるため回路上使用し難く
なるという問題点があることがわかった。However, increasing 13gt means that the second gate G has a source-drain current ID5S (IDSS is the source-drain current when both the first gate-source voltage and the second gate-source voltage are zero). ) is significantly limited, and II) 9m in the ss state is significantly reduced. In addition, the dependence of the drain current ID on the second gate-source voltages VG and S becomes extremely large, and the power gain P
It has been found that there is a problem in that the dependence of G (equivalent to JiFm) on VC and S becomes steep, making it difficult to control the drain current, making it difficult to use in circuits.
このように従来のスゲ−）ＧａＡｓ ＦＥＴでは４３
ｇ Ｉ≦Ｅｇｔの構造が採用され、第２ゲートＧｔを積
極的に最適化して特性の向上を図るようにしていない。In this way, in the conventional GaAs FET, 43
A structure in which g I≦Egt is adopted, and the second gate Gt is not actively optimized to improve the characteristics.
したがって、双ゲート型ＧａＡｓ Ｆ Ｅ Ｔの特性は
第２ゲートの存在により単ゲートのそれよりもＰＧ、Ｎ
Ｆ（雑音指数）等の面で劣っていることがわかった。Therefore, due to the presence of the second gate, the characteristics of the double-gate GaAs FET are better than those of the single gate.
It was found that it was inferior in terms of F (noise figure), etc.
本発明の目的とするところは、Ａ Ｇ Ｃ（Ａｕｔｏｍ
ａｔ １ｃＧａｉｎ Ｃｏｎｔｒｏｌ ）において、第
２ゲート・ソース電圧Ｖｏ、ｓ依存性をゆるやかにして
回路的に使用し易すくした双ゲートＧａＡｓ Ｆ Ｅ
Ｔを提供することＫある。The object of the present invention is to perform AGC (Automatic
At 1cGain Control), the dual-gate GaAs FE has a gentle dependence on the second gate-source voltages Vo and s, making it easier to use in terms of circuitry.
There is K to provide T.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、ＧａＡｓ基板上に第１ゲート及び第２ゲート
が並設され第１ゲートへの電圧印加によってソース・ド
レイン電流が制御されるＧａＡｓＦＥＴであって、第２
ゲート長！ｇｔを第１ゲート長Ｊｇｓ よりも小さく形
成することＫより、１ｍの向上が図られ、同時に第２ゲ
ート・ソース電圧依存性ｖＧ、 ｓが弱められて回路に
使用し易くなり発明の目的を達成できる。That is, it is a GaAsFET in which a first gate and a second gate are arranged in parallel on a GaAs substrate, and the source/drain current is controlled by applying a voltage to the first gate.
Gate chief! By making gt smaller than the first gate length Jgs, an improvement of 1 m is achieved by K, and at the same time, the second gate-source voltage dependence vG, s is weakened, making it easier to use in circuits, achieving the purpose of the invention. can.
〔実施例１〕
第１図は本発明の一実施例を示すものであって、スゲ−
）ＧａＡｓＦＥＴの縦断面、斜面図である。[Example 1] Figure 1 shows an example of the present invention.
) A longitudinal section and a slope view of a GaAsFET.
１はＧａＡｓ結晶からなる半絶縁性基板（チップ）、２
はチャネル部及びソース・ドレイン・コンタクトどなる
ｎ型ドープ層である。なお、ソース・ドレインコンタク
トとなるｎ型層表面部分には高濃度ｎ＋型型数散層形成
しておくことがのぞましい。1 is a semi-insulating substrate (chip) made of GaAs crystal, 2
is an n-type doped layer that forms the channel portion and source/drain contacts. Note that it is preferable to form a highly concentrated n+ type dispersed layer on the surface portion of the n type layer which will serve as the source/drain contact.
３．４はソース・ドレイン電極であって、ＡｕＧｅを下
地とするＮｉ／Ａｕメッキ層等から構成され、前記ｎ型
層（ｎ＋型層）表面に蒸着、ス／（ツタ等により形成さ
れる。５は第１ゲートでＡ［よりなり、ゲート長−ｇｇ
＋＝１〜２μ程度とする。６は制御用のための第２ゲー
トで、ＡＡよりなりゲート長１ｇ、＝０．５〜１μ程度
とする。Reference numeral 3.4 denotes source/drain electrodes, which are composed of a Ni/Au plating layer with AuGe as a base, and are formed on the surface of the n-type layer (n+-type layer) by vapor deposition, sintering, etc. 5 is the first gate and consists of A[, gate length - gg
+=approximately 1 to 2μ. Reference numeral 6 denotes a second gate for control, which is made of AA and has a gate length of 1 g and approximately 0.5 to 1 μm.
なお、図示されないが、電極を含む基板表面上にはパッ
ジベージ冒ンとしてＣＶＤ（気相化学堆積）Ｓｉｎ、膜
のごとき無機絶縁膜、又はポリイミド系樹脂のごとき有
機絶縁膜で覆われることになる。Although not shown, the surface of the substrate including the electrodes is covered with an inorganic insulating film such as CVD (vapor phase chemical deposition) Sin, a film, or an organic insulating film such as polyimide resin as a padding coating.
以上実施例で述べた発明によれば、下記のように効果が
得られる。According to the invention described in the embodiments above, the following effects can be obtained.
ｆｉ＋ 第２ゲート長２ｇ！を第１ゲート長−１３ｇ
Ｉよりも短かくすることにより、第２ゲートＧ、による
ドレイン電流ＩＤ制限が緩和され、ソース・ドレイン電
流Ｉ Ｄ８ｇが大きくなり、その結果として増幅率１ｍ
をたかめることができる。すなわちＡＧＣ（自動利得制
御）のＶｃ、ｓ依存性がゆるやかになり、広い範囲で使
い易くなった。fi+ 2nd gate length 2g! The first gate length - 13g
By making it shorter than I, the drain current ID restriction by the second gate G is relaxed, the source-drain current ID8g becomes larger, and as a result, the amplification factor is 1m.
can be increased. In other words, the dependence of AGC (automatic gain control) on Vc and s has become gentler, making it easier to use over a wide range.
（２） 第２ゲート長を短かくすることにより、ピン
チオフが深くなり、スローカットオフが効果的になった
。(2) By shortening the second gate length, the pinch-off becomes deeper and the slow cut-off becomes more effective.
（３） 上記ｆｉｌ（２）により、利得制御側、雑音
特性が同一ゲート幅で向上する。(3) With the above fil (2), the gain control side and noise characteristics are improved with the same gate width.
〔実施例２〕
第５図は本発明の他の一実施例を示すものであって、ス
ゲ−） ＧａＡｓ Ｆ Ｅ Ｔの縦断面図である。[Embodiment 2] FIG. 5 shows another embodiment of the present invention, and is a longitudinal sectional view of a GaAs FET.
この実施例では第１ゲート、第２ゲートにおいて、ゲー
ト幅Ｗ、ゲート長−ｇ ｇ １ ｅ ４ ｇ ｔは等
しいが、チャネル深さくｄ＋ −ｄ！ ）を変える
ことにより１ｍ等を向上させるものである。In this embodiment, the gate width W and the gate length -g g 1 e 4 g t are the same in the first gate and the second gate, but the channel depth is d+ -d! ) can be improved by 1m, etc.
すなわち、同図に示すように第１ゲートＧＩの形成され
るｎ型層２０表面のみに凹部７をホトエツチングにより
あけておき、第２ゲートＧ１の形成されるｎ型層の表面
は凹部を形成しないか、又は凹部７に比べて浅い凹部を
形成し、これらの上に同じゲート長の第１ゲートＧ１及
び第２ゲートＧ！を形成するものである。That is, as shown in the figure, a recess 7 is formed by photoetching only on the surface of the n-type layer 20 where the first gate GI is formed, and no recess is formed on the surface of the n-type layer where the second gate G1 is formed. Alternatively, a recess shallower than the recess 7 is formed, and the first gate G1 and the second gate G! having the same gate length are formed above the recess 7. It forms the
このような双ゲートＧａＡｓＦＥＴ構造によれば第２ゲ
ートＧ、下のチャネル深さｄ、は第１ゲート下のチャネ
ル深さｄ、よりも深いことにより、第２ゲートＧｔによ
るドレイン電流ＩＤ制限が緩和され、実施例】の場合と
同様の理由でＪｍが向上し、電力利得、雑音特性が向上
できる。According to such a double-gate GaAsFET structure, the channel depth d under the second gate G is deeper than the channel depth d under the first gate, so that the restriction on drain current ID by the second gate Gt is relaxed. Therefore, Jm is improved for the same reason as in the embodiment, and power gain and noise characteristics can be improved.
〔実施例３〕
第６図は本発明の他の一実施例を示すものであって、ス
ゲ−） ＧａＡｓ Ｆ Ｅ Ｔの断面図である。[Embodiment 3] FIG. 6 shows another embodiment of the present invention, and is a sectional view of a GaAs FET.
この実施例では第１ゲー）、ｉＩ２ゲートにおいてゲー
ト幅、ゲート長を等しくする一方、チャネル部の不純物
濃度を変えることにより前記発明の目的を達成させるも
のである。In this embodiment, the object of the invention is achieved by making the gate width and gate length equal in the first gate) and iI2 gate, while changing the impurity concentration in the channel portion.
すなわち、同図に示すように、第１ゲートＧ。That is, as shown in the figure, the first gate G.
の形成されるｎ型層２の表面にこのｎ型層２よりわずか
に高い濃度で不純物（たとえばシリコン）をイオン打込
み等圧より導入し、ｎ型層８を形成しておくものである
。なお、チャネル部となるｎ型層２の不純物濃度ｎ−は
低く制御しておく必要がある。An impurity (for example, silicon) is introduced into the surface of the n-type layer 2 by ion implantation at a slightly higher concentration than the n-type layer 2, thereby forming the n-type layer 8. Note that the impurity concentration n- of the n-type layer 2 serving as the channel portion must be controlled to be low.
このような双ゲートＧａＡｓＦＥＴ構造によれば、第２
ゲートＧｔ下のチャネル部濃度が第１ゲートＧ、のチャ
ネル濃度よりも低いことにより第２ゲ−） Ｇ、による
ドレイン電流ＩＤ制限が緩和され、実施例１の場合と同
様の理由で１ｍが向上し、電力利得、雑音特性が向上で
きる。According to such a double-gate GaAsFET structure, the second
Since the channel concentration under the gate Gt is lower than the channel concentration of the first gate G, the drain current ID limit due to the second gate G is relaxed, and 1m is improved for the same reason as in Example 1. However, power gain and noise characteristics can be improved.
本発明は主としてテレビジョン、チューナ用双ゲー）
ＧａＡｓ Ｆ Ｅ Ｔに応用して効果がある。The present invention is mainly applicable to televisions and tuners.
It is effective when applied to GaAs FET.
第１図は本発明の一実施例を示し、ＧａＡｓ Ｆ ＥＴ
の正面断面斜面図である。
第２図は双ゲートＦＥＴにおけるＩｄ−ＶＧＳ曲線図で
ある。
第３図及び第４図はＧａＡｓＦＥＴの従来例を示す断面
図である。
第５図及び第６図は本発明の他の実施例を示す断面図で
ある。
１・・・Ｇ ａ Ａ ｓ基板、２・・・ｎ型層（チャネ
ル部、コンタクト部）、３・・・ソース電極、４・・・
ドレイン電極、５・・・第１ゲート、６・・・第２ゲー
ト、７・・・凹部、８・・・ｎ型拡散層。
第 １ 図
第 ２ 図
一１／ｆＳ
第 ３ 図
第 ４ 図FIG. 1 shows an embodiment of the present invention, in which a GaAs FET
FIG. FIG. 2 is an Id-VGS curve diagram for a double-gate FET. FIGS. 3 and 4 are cross-sectional views showing conventional examples of GaAsFETs. FIGS. 5 and 6 are cross-sectional views showing other embodiments of the present invention. DESCRIPTION OF SYMBOLS 1... Ga As substrate, 2... n-type layer (channel part, contact part), 3... source electrode, 4...
Drain electrode, 5... first gate, 6... second gate, 7... recess, 8... n-type diffusion layer. Figure 1 Figure 2 Figure 1/fS Figure 3 Figure 4
Claims (1)
ン調整用の第２ゲートが並設され、これら２つのゲート
を挾んでソース電極及びドレイン電極が設けられ、ソー
ス電極近傍に設けられた第１ゲートへの電圧印加によっ
てソース・ドレイン電流が制御されるＧａＡｓ電界効果
トランジスタであって、第２ゲート長は第１ゲート長よ
りも短かく形成されていることを特徴とするＧａＡｓ電
界効果トランジスタ。 ２、ＧａＡｓ基板上に信号入力用の第１ゲート及びゲイ
ン調整用の第２ゲートが並設され、これら２つのゲート
を挾んでソース及びドレイン各電極が設けられ、ソース
電極近傍に設けられた第１ゲートへの電圧印加によって
ソース・ドレイン電流が制御されるＧａＡｓ電界効果ト
ランジスタであって、第２ゲートのチャンネル部の深さ
が第１ゲートのそれより深くしたことを特徴とするＧａ
Ａｓ電界効果トランジスタ。 ３、第１ゲートと第２ゲートは基板表面の凹部内に形成
され、第２ゲートの凹部の深さは第１ゲートのそれより
浅く形成された特許請求の範囲第２項に記載のＧａＡｓ
電界効果トランジスタ。[Claims] 1. A first gate for signal input and a second gate for gain adjustment are arranged in parallel on a GaAs substrate, a source electrode and a drain electrode are provided sandwiching these two gates, and the source electrode A GaAs field effect transistor whose source/drain current is controlled by applying a voltage to a first gate provided nearby, characterized in that the second gate length is formed shorter than the first gate length. GaAs field effect transistor. 2. A first gate for signal input and a second gate for gain adjustment are arranged in parallel on a GaAs substrate, and source and drain electrodes are provided between these two gates, and a second gate is provided near the source electrode. A GaAs field effect transistor whose source-drain current is controlled by voltage application to one gate, characterized in that the depth of the channel portion of the second gate is deeper than that of the first gate.
As field effect transistor. 3. The GaAs according to claim 2, wherein the first gate and the second gate are formed in a recess in the substrate surface, and the depth of the recess of the second gate is shallower than that of the first gate.
Field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5222685A JPS61212069A (en) | 1985-03-18 | 1985-03-18 | Gaas field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5222685A JPS61212069A (en) | 1985-03-18 | 1985-03-18 | Gaas field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61212069A true JPS61212069A (en) | 1986-09-20 |
Family
ID=12908825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5222685A Pending JPS61212069A (en) | 1985-03-18 | 1985-03-18 | Gaas field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61212069A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03227071A (en) * | 1990-01-31 | 1991-10-08 | Nec Corp | Schottky barrier field-effect transistor |
| GB2438677B (en) * | 2006-05-31 | 2011-08-10 | Filtronic Compound Semiconductors Ltd | A field effect transistor having multiple pinch off voltages |
-
1985
- 1985-03-18 JP JP5222685A patent/JPS61212069A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03227071A (en) * | 1990-01-31 | 1991-10-08 | Nec Corp | Schottky barrier field-effect transistor |
| GB2438677B (en) * | 2006-05-31 | 2011-08-10 | Filtronic Compound Semiconductors Ltd | A field effect transistor having multiple pinch off voltages |
| US8115233B2 (en) | 2006-05-31 | 2012-02-14 | Rfmd (Uk) Limited | Field effect transistor having multiple pinch off voltages |
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