JPS6121118U - multiplier - Google Patents

multiplier

Info

Publication number
JPS6121118U
JPS6121118U JP10560284U JP10560284U JPS6121118U JP S6121118 U JPS6121118 U JP S6121118U JP 10560284 U JP10560284 U JP 10560284U JP 10560284 U JP10560284 U JP 10560284U JP S6121118 U JPS6121118 U JP S6121118U
Authority
JP
Japan
Prior art keywords
strip line
diode
open
multiplier
end connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10560284U
Other languages
Japanese (ja)
Other versions
JPH0336091Y2 (en
Inventor
昭一 鎌田
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP10560284U priority Critical patent/JPS6121118U/en
Publication of JPS6121118U publication Critical patent/JPS6121118U/en
Application granted granted Critical
Publication of JPH0336091Y2 publication Critical patent/JPH0336091Y2/ja
Granted legal-status Critical Current

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  • Control Of Motors That Do Not Use Commutators (AREA)
  • Complex Calculations (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例を示す回路図、第２図は一般
の逓倍器の基本回路を示す接続図、第３図は従来の逓倍
器を示す接続図である。 １１，２１，３１・・・入力端子、１２，２２．３２・
・・入力整合回路、１３， ２３， ３３・・・ダイ
オード、１４・・・インダクタンス、１５・・・容量、
１６，２７．３８・・・負荷、２４，２６，３４・・・
伝送線路、３５．３６・・・平行結合線路。FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a connection diagram showing the basic circuit of a general multiplier, and FIG. 3 is a connection diagram showing a conventional multiplier. 11, 21, 31... Input terminal, 12, 22. 32.
...Input matching circuit, 13, 23, 33...Diode, 14...Inductance, 15...Capacitance,
16,27.38...Load, 24,26,34...
Transmission line, 35.36...Parallel coupled line.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力端子に入力整合回路を介して接続されたダイオード
と、このダイオードに一端が接続され他端が開放された
長さが出力周波数の約１／ｍ長の第１のストリップ線路
と、この第１のストリップ線路とギャップをおいて長手
方向が平行になるように配置され一端が開放され他端が
負荷に接続された第２のストリップ線路とを具備し、前
記第１のストリップ線路及び前記第２のストリップ線路
により共振器を構成したことを特徴とする逓倍器。a diode connected to the input terminal via an input matching circuit; a first strip line with one end connected to the diode and the other end open, the length of which is approximately 1/m of the output frequency; a second strip line arranged so that its longitudinal direction is parallel to the strip line with a gap therebetween, one end of which is open and the other end connected to a load; A multiplier characterized in that a resonator is configured by a strip line.
JP10560284U 1984-07-12 1984-07-12 multiplier Granted JPS6121118U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10560284U JPS6121118U (en) 1984-07-12 1984-07-12 multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10560284U JPS6121118U (en) 1984-07-12 1984-07-12 multiplier

Publications (2)

Publication Number Publication Date
JPS6121118U true JPS6121118U (en) 1986-02-07
JPH0336091Y2 JPH0336091Y2 (en) 1991-07-31

Family

ID=30664915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10560284U Granted JPS6121118U (en) 1984-07-12 1984-07-12 multiplier

Country Status (1)

Country Link
JP (1) JPS6121118U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5942624U (en) * 1982-09-10 1984-03-19 日本電気株式会社 Harmonic generation circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5942624B2 (en) * 1980-06-27 1984-10-16 アイン・エンジニアリング株式会社 Method of forming plaster decorative board

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5942624U (en) * 1982-09-10 1984-03-19 日本電気株式会社 Harmonic generation circuit

Also Published As

Publication number Publication date
JPH0336091Y2 (en) 1991-07-31

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