JPS6120913B2 - - Google Patents
Info
- Publication number
- JPS6120913B2 JPS6120913B2 JP55080017A JP8001780A JPS6120913B2 JP S6120913 B2 JPS6120913 B2 JP S6120913B2 JP 55080017 A JP55080017 A JP 55080017A JP 8001780 A JP8001780 A JP 8001780A JP S6120913 B2 JPS6120913 B2 JP S6120913B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- level
- output
- signal
- analog signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 5
- 238000001514 detection method Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
- G06K7/10—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation
- G06K7/10544—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation by scanning of the records by radiation in the optical part of the electromagnetic spectrum
- G06K7/10821—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation by scanning of the records by radiation in the optical part of the electromagnetic spectrum further details of bar or optical code scanning devices
- G06K7/10851—Circuits for pulse shaping, amplifying, eliminating noise signals, checking the function of the sensing device
Landscapes
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- General Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Artificial Intelligence (AREA)
- Computer Vision & Pattern Recognition (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Manipulation Of Pulses (AREA)
- Character Input (AREA)
Description
【発明の詳細な説明】
本発明はアナログ信号波形を２値化処理する２
値化方式に関し、とくに２値化処理に供する装置
の回路調整を容易にした２値化方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides two methods for binarizing analog signal waveforms.
The present invention relates to a digitization method, and particularly relates to a digitization method that facilitates circuit adjustment of a device used for binarization processing.
バーコード情報読取り装置等では、バーコード
を形成するバーに光スポツトにより光走査を行
い、その反射光を光電変換して得られる電気信号
を用いて、バーコード情報の読取りを行うのがこ
の場合、読取り処理を行うため前述の光電変換信
号を２値化処理する。 In this case, a barcode information reading device scans the bar forming the barcode with a light spot, and uses the electric signal obtained by photoelectrically converting the reflected light to read the barcode information. , the above-mentioned photoelectric conversion signal is binarized for reading processing.
第１図は従来の２値化回路の構成図であつて、
１はバーコードを構成するバーからの反射光を受
け電気信号に変換するための光検知器、２は増幅
器、３は正側エンベロープ回路、４は負側エンベ
ロープ回路、５は中点検出回路、６はスライス回
路、７は出力端子である。 FIG. 1 is a block diagram of a conventional binarization circuit.
1 is a photodetector for receiving reflected light from the bars constituting the bar code and converting it into an electrical signal; 2 is an amplifier; 3 is a positive envelope circuit; 4 is a negative envelope circuit; 5 is a midpoint detection circuit; 6 is a slice circuit, and 7 is an output terminal.
光検知器１から第２図ａに示すようにバーコー
ド情報に対応したアナログ信号が出力され、増幅
器２で第２図ｂのように増幅した後、正，負側エ
ンベロープ回路３，４で正側および負側エンベロ
ープ信号を得る。 An analog signal corresponding to the barcode information is output from the photodetector 1 as shown in FIG. 2a, and after being amplified by the amplifier 2 as shown in FIG. Obtain the side and negative side envelope signals.
中点検出回路５はこれら正負側エンベロープ回
路３，４の出力を受けて正側，負側エンベロープ
信号の中点を算出し、この中点のレベルの信号を
レベルスライス回路６へ入力する。レベルスライ
ス回路６には増幅器２の出力も入力され、中点検
出回路５からの出力を基準レベルとして増幅器２
の出力信号をレベルスライスせしめるため出力端
子７より、２値化信号が現れ、図示しないバーコ
ード情報読取り部でこの２値化信号に基いて情報
の読取を行う。 The midpoint detection circuit 5 receives the outputs of the positive and negative side envelope circuits 3 and 4, calculates the midpoint of the positive side and negative side envelope signals, and inputs the signal at the level of this midpoint to the level slice circuit 6. The output of the amplifier 2 is also input to the level slice circuit 6, and the output from the midpoint detection circuit 5 is used as a reference level.
In order to level-slice the output signal, a binary signal appears from the output terminal 7, and a barcode information reading section (not shown) reads information based on this binary signal.
しかしこのような２値化方式では、正，負側エ
ンベロープ回路およびレベルスライス回路のオフ
セツト調整を必要とし、回路調整が繁雑化し、ま
た回路も複雑となる欠点があつた。 However, such a binarization method requires offset adjustment of the positive and negative side envelope circuits and the level slice circuit, which has the disadvantage that the circuit adjustment becomes complicated and the circuit becomes complicated.
本発明はかかる点に鑑みなされたもので、回路
調整が容易で、かつ回路構成も簡単で済む２値化
方式を提供することを目的とし、２値化処理すべ
きアナログ信号を予め設定されたスライスレベル
によりレベルスライスし、前記アナログ信号を２
値化する２値化方式において、前記アナログ信号
の正側および負側エンベロープ信号を得る回路
と、これらエンベロープ回路の出力値の和の１／２値
を求め、前記アナログ信号との差を得る演算回路
とを設け、該演算回路の出力信号をレベルスライ
スし２値化するようにしたことを特徴とする。 The present invention has been made in view of the above points, and aims to provide a binarization method that allows easy circuit adjustment and a simple circuit configuration. The analog signal is level-sliced according to the slice level, and the analog signal is
In the binarization method for converting into values, a circuit for obtaining positive and negative envelope signals of the analog signal, and an operation for obtaining 1/2 of the sum of the output values of these envelope circuits and obtaining the difference from the analog signal. The present invention is characterized in that a circuit is provided, and the output signal of the arithmetic circuit is level-sliced and binarized.
以下図面を参照しながら本発明の好ましい実施
例について詳細に説明する。 Preferred embodiments of the present invention will be described in detail below with reference to the drawings.
第３図は本発明の一実施例構成図であつて、第
１図と同等部分には同一符号を付した。 FIG. 3 is a configuration diagram of an embodiment of the present invention, and the same parts as in FIG. 1 are given the same reference numerals.
第３図において、８は演算部であつて第２図
ｃ，ｄ正，負側エンベロープ回路３．４の出力値
νｐ，νｎを加算して、その１／２値を算出するとと
もに、前記増幅器２の出力値νａとの減算を行
う。第２図ｅに示すνｏ＝νａ−１／２（νｐ＋ν
ｎ）なる出力値が演算部８で得られ、レベルスラ
イス回路９に入力され基準信号源１０の出力レベ
ルによつて定まるスライスレベルにより、演算部
８の出力値をレベルスライスする。 In FIG. 3, 8 is an arithmetic unit which adds the output values νp and νn of the positive and negative envelope circuits 3 and 4 in FIGS. Subtraction is performed with the output value νa of 2. An output value of νo=νa−1/2(νp+νn) shown in FIG. The output value of the calculation unit 8 is level sliced.
次にこの装置の動作を説明する。 Next, the operation of this device will be explained.
光検知器１の出力信号は、バーからの反射光を
受けて光電変換して得られる第２図ａに示すよう
なアナログ信号であり、この信号を増幅器２で増
幅した後、正，負側エンベロープ回路３，４およ
び演算部８へ入力される。 The output signal of the photodetector 1 is an analog signal as shown in Fig. 2a, which is obtained by photoelectrically converting the reflected light from the bar. The signal is input to envelope circuits 3 and 4 and arithmetic unit 8.
演算部８では前述のように、増幅器２の出力ν
ａ正，負側エンベロープ回路３，４の出力νｐ，
νｎに基いてνｏ＝νａ−１／２（νｐ＋νｎ）なる
演算を行う。第２図ｆはレベルスライス回路９の
出力波形である。 As mentioned above, the calculation unit 8 calculates the output ν of the amplifier 2.
a Output νp of positive and negative side envelope circuits 3 and 4,
Based on νn, the calculation νo=νa−1/2(νp+νn) is performed. FIG. 2f shows the output waveform of the level slice circuit 9.
ところで増幅器２、正，負側エンベロープ回路
３，４のオフセツト調整が不完全のため、それぞ
れ基準レベルに対してVa，Vp，Vnの変動が生じ
た場合、増幅器２の出力レベルはνａ＋Vaとな
り、この出力を受ける正，負側エンベロープ回路
３，４の出力はそれぞれνｐ＋Va＋Vp，νｎ＋
Va＋Vnとなる。 By the way, if the offset adjustment of amplifier 2, positive and negative envelope circuits 3 and 4 is incomplete, and Va, Vp, and Vn vary with respect to the reference level, the output level of amplifier 2 becomes νa + Va, and this The outputs of the positive and negative envelope circuits 3 and 4 that receive the outputs are νp+Va+Vp and νn+, respectively.
It becomes Va+Vn.
従つて演算部８で前述の演算処理が行われた場
合演算部８の出力は、
o′＝νａ−１／２（νｐ＋νｎ＋Vp＋Vn）とな
る。 Therefore, when the arithmetic processing described above is performed in the arithmetic unit 8, the output of the arithmetic unit 8 is o'=va-1/2 (vp+vn+Vp+Vn).
この演算部８の出力は、光検知器１の出力信号
に対応した信号νａ−１／２（νｐ＋νｎ）に正，負
側エンベロープ回路３，４のオフセツト電圧
Vp，Vnで定まる電圧−１／２（Vp＋Vn）が重畳した
形になつており、従つて基準電源１０の出力レベ
ルをこの電圧−１／２（Vp＋Vn）を相殺するよう調
整すれば済む。 The output of this calculation unit 8 is a signal νa-1/2 (νp+νn) corresponding to the output signal of the photodetector 1, and the offset voltages of the positive and negative side envelope circuits 3 and 4.
The voltage -1/2 (Vp+Vn) determined by Vp and Vn is superimposed, so it is only necessary to adjust the output level of the reference power supply 10 to offset this voltage -1/2 (Vp+Vn).
従つて本実施例においては、回路調整はこの基
準電源１０の出力レベル調整でよく第１図に示し
た従来の個々に調整する方式に比して調整は容易
である。 Therefore, in this embodiment, the circuit adjustment can be made by adjusting the output level of the reference power supply 10, and the adjustment is easier than the conventional individual adjustment method shown in FIG.
しかし、レベルスライス回路への２つの入力の
一方は固定レベル（直流）であり、レベルスライ
ス回路の構成も簡単となり、２値化の安定度も向
上する。 However, one of the two inputs to the level slice circuit is a fixed level (direct current), which simplifies the configuration of the level slice circuit and improves the stability of binarization.
以上の説明から明らかなように本発明に係る２
値化方式は、２値化すべきアナログ信号波形の
正，負側エンベロープ信号の和の１／２の値を求め、
前述のアナログ信号との減算を行い２値化処理す
るため、これら信号処理に供される個々のオフセ
ツト調整が不要となり、回路調整が簡単になると
共に、２値化の安定度向上となる。 As is clear from the above description, two according to the present invention
The digitization method calculates the value of 1/2 of the sum of the positive and negative envelope signals of the analog signal waveform to be binarized, and subtracts it from the analog signal mentioned above to perform the binarization process. This eliminates the need for individual offset adjustments, which simplifies circuit adjustment and improves the stability of binarization.
第１図は従来の２値化方式を行うための回路構
成図、第２図ａ〜ｆは信号波形図、第３図は本発
明の一実施例回路構成図である。
１…光検知器、２…増幅器、３…正側エンベロ
ープ回路、４…負側エンベロープ回路、８…演算
部、９…レベルスライス回路。
FIG. 1 is a circuit configuration diagram for performing a conventional binarization method, FIG. 2 a to f are signal waveform diagrams, and FIG. 3 is a circuit configuration diagram of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Photodetector, 2... Amplifier, 3... Positive side envelope circuit, 4... Negative side envelope circuit, 8... Arithmetic unit, 9... Level slice circuit.
Claims (1)
れたスライスレベルによりレベルスライスし、前
記アナログ信号を２値化する２値化方式におい
て、前記アナログ信号の正側および負側エンベロ
ープ信号を得る回路と、これらエンベロープ回路
の出力値の和の１／２値を求め、前記アナログ信号と の差を得る演算回路とを設け、該演算回路の出力
信号をレベルスライスし２値化するようにしたこ
とを特徴とする２値化方式。[Claims] 1. In a binarization method in which an analog signal to be binarized is level-sliced according to a preset slice level and the analog signal is binarized, the positive side and the negative side of the analog signal are A circuit that obtains an envelope signal and an arithmetic circuit that obtains the 1/2 value of the sum of the output values of these envelope circuits and obtains the difference from the analog signal are provided, and the output signal of the arithmetic circuit is level-sliced and binarized. A binarization method characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8001780A JPS576978A (en) | 1980-06-13 | 1980-06-13 | Binary coding system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8001780A JPS576978A (en) | 1980-06-13 | 1980-06-13 | Binary coding system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS576978A JPS576978A (en) | 1982-01-13 |
| JPS6120913B2 true JPS6120913B2 (en) | 1986-05-24 |
Family
ID=13706530
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8001780A Granted JPS576978A (en) | 1980-06-13 | 1980-06-13 | Binary coding system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS576978A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6159572A (en) * | 1984-08-30 | 1986-03-27 | Audio Technica Corp | Bar signal forming circuit of bar code reader |
| JPH0650513B2 (en) * | 1984-10-11 | 1994-06-29 | キヤノン株式会社 | Information retrieval device |
-
1980
- 1980-06-13 JP JP8001780A patent/JPS576978A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS576978A (en) | 1982-01-13 |
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