JPS61204984A - Field effect transistor and manufacture thereof - Google Patents
Field effect transistor and manufacture thereofInfo
- Publication number
- JPS61204984A JPS61204984A JP4580485A JP4580485A JPS61204984A JP S61204984 A JPS61204984 A JP S61204984A JP 4580485 A JP4580485 A JP 4580485A JP 4580485 A JP4580485 A JP 4580485A JP S61204984 A JPS61204984 A JP S61204984A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- electrode
- insulating film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 230000005669 field effect Effects 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 239000012212 insulator Substances 0.000 claims abstract description 8
- 239000007772 electrode material Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 abstract description 13
- 229910052751 metal Inorganic materials 0.000 abstract description 13
- 230000015572 biosynthetic process Effects 0.000 abstract description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 6
- 230000010354 integration Effects 0.000 abstract description 6
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 230000008020 evaporation Effects 0.000 abstract 2
- 238000001704 evaporation Methods 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 abstract 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 206010011732 Cyst Diseases 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 208000031513 cyst Diseases 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
電界効果トランジスタ（ＦＥＴ）およびその製造方法で
あって、ソース抵抗を低減させるため、ソース電極およ
びドレイン電極を選択的に覆う絶縁膜をゲート電極との
間の絶縁体にすることによって、ソース電極およびドレ
イン電極とゲート電極との間隙を容易に小さくし、例え
ばヘテロ接合ＦＥＴの特性向上と高集積化を可能にする
。[Detailed Description of the Invention] [Summary] A field effect transistor (FET) and a method for manufacturing the same, in which an insulating film that selectively covers a source electrode and a drain electrode is separated from a gate electrode in order to reduce source resistance. By making it an insulator, the gap between the source electrode, the drain electrode, and the gate electrode can be easily reduced, making it possible to improve the characteristics and increase the integration of, for example, a heterojunction FET.
本発明は、ＦＥＴおよびその製造方法に係り、特に、ソ
ース電極、ゲート電極、ドレイン電極およ −びそれ
らの間にある絶縁体の構成に関す。The present invention relates to a FET and a method for manufacturing the same, and particularly to the structure of a source electrode, a gate electrode, a drain electrode, and an insulator between them.
ＦＥＴは半導体装置の機能素子として多用されている。FETs are frequently used as functional elements in semiconductor devices.
そしてその高速動作の要望に応えるため、ガリウム砒素
（ＧａＡｓ）系半導体を使用したヘテロ接合ＦＥＴなど
の研究が進められている。In order to meet the demand for high-speed operation, research is underway on heterojunction FETs using gallium arsenide (GaAs)-based semiconductors.
このヘテロ接合１？ＥＴは、二次元電子ガス（２ＤＥＣ
）形成領域のドーピングプロファイルが急峻であるのが
望ましいため、イオン注入によるソース抵抗の低減化は
避けるのが望ましい。This heterojunction 1? ET is two-dimensional electron gas (2DEC
) Since it is desirable that the doping profile of the formation region be steep, it is desirable to avoid reducing the source resistance by ion implantation.
この場合上記抵抗は、ソース電極やドレイン電極とゲー
ト電極との間隙の大きさが小さい程低減するので、該間
隙は特性向上のため小さくすることが望まれる。In this case, the resistance decreases as the gap between the source electrode or drain electrode and the gate electrode becomes smaller, so it is desirable to make the gap smaller in order to improve the characteristics.
ソース抵抗を低減さ」Ｆるためのイ′：、４ンメＰ人を
行わないヘテロ接合ＦＥＴの例の製造手順は第３図（ａ
１〜（ｆ）の工程順側断面図に示す如くである。The fabrication procedure for an example of a heterojunction FET that does not require a 4-channel FET to reduce the source resistance is shown in Figure 3 (a).
As shown in the step-by-step side sectional views of 1 to (f).
即も先ず〔図（ａｌ参照〕、ノンドープＧａＡｓ基体１
ａ」二にｎ型アルミニウムガリウム砒素（ＡＩＧａＡｓ
） 屓１ｂとｎ型ＧａＡｓ層１ｃを梼屓してなる′□１
６導体基板１土に、例えば二酸化シリニ１ン（Ｓｉ０２
）の絶縁膜２と１／シスト膜３とを被着し、露光、現像
ｆよるＩ／ ｙシス１−膜３の一部除去およびＩ／・ン
スト映３をマスクにした絶縁膜２のエンチング除去によ
り１、ソース電極およびドＩメイン電極形成位置にレジ
スＩ・膜３と絶縁膜２とでズテンシル構造Ｑでな２つ基
板１を表出さ（るマスク窓４を形成する。First of all, [see figure (al)], non-doped GaAs substrate 1
a” Second, n-type aluminum gallium arsenide (AIGaAs
) Formed by separating the layer 1b and the n-type GaAs layer 1c'□1
6 Conductor substrate 1 Soil, for example, silicon dioxide (Si02
), the insulating film 2 and the 1/cyst film 3 are deposited, a portion of the I/y cis 1-film 3 is removed by exposure and development f, and the insulating film 2 is etched using the I/y cyst film 3 as a mask. By removing, 1. a mask window 4 is formed to expose two substrates 1 with a stencil structure Q made up of the resist I/film 3 and the insulating film 2 at the positions where the source electrode and the domain I main electrode are to be formed.
次いで〔図（ｂｌ参照〕、例えば金ゲルマニウム（Ａｕ
Ｇｅ） ・金（Ａｕ）の二層でなりソース電極および
ドレイン電極を形成する金属膜５を例えば蒸着により被
着する。さすれば、マスク窓４の中にソース電極６とド
レイン電極７とが形成される。言うまでもなく金属膜５
はレジスト膜３上にも被着する。Next [see figure (bl)], for example, gold germanium (Au
A metal film 5 consisting of two layers of Ge) and gold (Au) and forming a source electrode and a drain electrode is deposited, for example, by vapor deposition. Then, a source electrode 6 and a drain electrode 7 are formed in the mask window 4. Needless to say, metal film 5
is also deposited on the resist film 3.
次いで〔図（Ｃ）参照〕、レジスト膜３と共に金属膜５
をリフトオフして絶縁膜２を表出させる。Next [see figure (C)], the metal film 5 is formed together with the resist film 3.
is lifted off to expose the insulating film 2.
次いで〔図（ｄ）参照〕、全面にレジス１〜膜８を被着
して、露光、現像によりゲート電極形成位置にマスク窓
８ａを形成し、これをマスクにした絶縁膜２の選択的エ
ツチングおよびｎ型ＧａＡｓ層１ｅの選択的エツチング
（ゲートリセス）によりゲー ト電極形成領域９を形成
する。Next [see Figure (d)], resists 1 to 8 are deposited on the entire surface, and a mask window 8a is formed at the gate electrode formation position by exposure and development, and selective etching of the insulating film 2 is performed using this as a mask. Then, a gate electrode forming region 9 is formed by selectively etching (gate recess) the n-type GaAs layer 1e.
次いで〔図（８）参照〕、例えばチタン（Ｔｉ）・白金
（Ｐｔ）・Ａｕの三層でなりゲート電極を形成する金属
膜１０を例えば蒸着により被着する。さすれば、ゲート
電極形成領域９内にゲーＩ−電極１）が形成される８金
屈膜１０はレジスト膜８」二にも被着する。Next [see FIG. 8], a metal film 10 consisting of, for example, three layers of titanium (Ti), platinum (Pt), and Au and forming a gate electrode is deposited by, for example, vapor deposition. Then, the 8-metal gold film 10 on which the gate I-electrode 1) is formed in the gate electrode forming region 9 also adheres to the resist film 8''.
次いで〔図（ｆ）参照〕、レジスト膜８と共Ｇこ金属膜
１０をリフトオフして、ソース電極６、トレイン電極７
およびゲー ト電極１）の形成を完了する。Next [see figure (f)], the resist film 8 and the metal film 10 are lifted off to form the source electrode 6 and the train electrode 7.
and complete the formation of gate electrode 1).
この後は図示を省略しであるが、絶縁膜の被塔、コンタ
クトボールの形成、配線の形成などの工程を経てヘテロ
接合ＦＥＴを完成させる。After this, although not shown in the drawings, the heterojunction FET is completed through steps such as covering with an insulating film, forming contact balls, and forming wiring.
（発明が解決しようと一４゛る問題点〕上記従来の製造
方法においこ、デー１−電極１）の形成は、ソース電極
６とドレイ：／電極７との間にある絶縁膜２にゲーｔ・
電極形成領域９を形成しこ行う。そし、７ゲート電極形
成領域９の形成は、図（ｄ）により説明した露光の際に
位置合わせ作Ｘ苓必要としている。このため１−５記位
濯合わせの誤差を吸収出来るよう、図（ｆ）に示すソー
ス電極６とゲート電極１）との間隙づ゛法ａおよびドレ
イン電極“ｌとデー１〜電極１）との間隙寸法１）を太
き（せざるを（ηない問題がある。(Problem that the invention seeks to solve) In the conventional manufacturing method described above, the formation of the electrode 1) is performed on the insulating film 2 between the source electrode 6 and the drain electrode 7. t・
An electrode forming region 9 is formed. The formation of the seven gate electrode formation regions 9 requires alignment operations during exposure as explained with reference to FIG. 3(d). Therefore, in order to absorb the 1-5 position alignment error, the gap between the source electrode 6 and the gate electrode 1) shown in Figure (f) should be There is a problem that the gap size 1) cannot be increased (η).
これに伴い形成されたパ・テ１゛コ接合１月灯は、ソー
・大抵抗およびドレ・イン抵抗が大きくなって、特性の
良くないものになる問題を有する。The P/T single junction lamp that has been formed in accordance with this has a problem in that the saw resistance and the drain resistance become large, resulting in poor characteristics.
上記問題点は、本発明の要旨説明図である第１図に示す
如く、ソース電極６とゲート電″極１３との間およびド
レイン電極７とゲート電極１３との間の絶縁体が絶縁膜
１２でなり、該絶縁膜１２の端面がトランジスタを形成
する半導体基板１Ａ （第３図図示の場合の基板１）に
接しているＦＥＴによって解決され、
また、半導体基板１Ａ裏表面接してソース電極６および
ドレイン電極７を形成し、４更に両電極６．７それぞれ
の露出面を選択的に覆う絶縁膜１２を形成する工程と、
」−記形成された両絶縁膜１２の間にゲート電極材料を
充填してゲート電極１３を形成する工程とを含んでなる
ＦＥＴの製造方法によって解決される。As shown in FIG. 1, which is a diagram illustrating the gist of the present invention, the above problem is caused by the fact that the insulator between the source electrode 6 and the gate electrode 13 and between the drain electrode 7 and the gate electrode 13 is an insulating film 12. This is solved by the FET in which the end face of the insulating film 12 is in contact with the semiconductor substrate 1A (substrate 1 in the case shown in FIG. 3) forming the transistor, and the source electrode 6 and forming a drain electrode 7, and further forming an insulating film 12 selectively covering the exposed surfaces of both electrodes 6 and 7;
The present invention is solved by a method of manufacturing an FET, which includes the steps of: - filling a gate electrode material between both of the insulating films 12 formed as described above to form a gate electrode 13;
上記製造方法においてゲート電極形成領域の形成は、絶
縁膜１２の形成によってなされるため従来のような位置
合わせ作業を必要としない。然も端面が基板１Ａに接す
る絶縁膜１２が、ソース電極６とゲート電極１３との間
およびドレイン電極７とゲート電極１３との間の絶縁体
になる。In the above manufacturing method, the gate electrode forming region is formed by forming the insulating film 12, so that no alignment work is required as in the conventional method. Furthermore, the insulating film 12 whose end surface is in contact with the substrate 1A serves as an insulator between the source electrode 6 and the gate electrode 13 and between the drain electrode 7 and the gate electrode 13.
従って形成されるＦＥＴは、ソース電極６とゲート電極
１３との間隙寸法ａおよびドレイン電極７とゲート電極
１３との間隙寸法すが、絶縁膜１２の厚さ寸法になって
従来より小さくなる。Therefore, in the FET formed, the gap size a between the source electrode 6 and the gate electrode 13 and the gap size between the drain electrode 7 and the gate electrode 13 are smaller than the conventional ones because of the thickness size of the insulating film 12.
然も、ソース電極６とドレイン電極７との間隔を小さく
出来るのでＩＣを形成する際の高集積化が容易になる。Moreover, since the distance between the source electrode 6 and the drain electrode 7 can be made small, it becomes easy to achieve high integration when forming an IC.
かくして例えばヘテロ接合ＦＥＴにおいて、イオン注入
することなしにソース抵抗を低減させ特性を向上させる
ことが可能になり、更にｔＣ形成の際の高集積化が容易
になる。In this way, for example, in a heterojunction FET, it becomes possible to reduce the source resistance and improve the characteristics without ion implantation, and furthermore, it becomes easy to achieve high integration when forming the tC.
以下ソース抵抗を低減させるためのイオン注入を行わな
いヘテロ接合ＦＥＴにおける本発明の実施例についてそ
のその構成と製造手順の要部を示す第２図（ａ）〜（ｆ
）の工程順側断面図により説明する。2(a) to (f) showing the main parts of the structure and manufacturing procedure of an embodiment of the present invention in a heterojunction FET that does not perform ion implantation to reduce source resistance.
) will be explained using step-by-step side sectional views.
第２図（ａ）〜ｍは第３図（ａ） 〜（ｆ）に対応する
図で、ＦＥＴの要部は図（ｆ）に示される。FIGS. 2(a) to 2m correspond to FIGS. 3(a) to 3(f), and the main part of the FET is shown in FIG. 2(f).
このＦＥＴは、第３図図示の場合に比較して、絶縁Ｊ１
ｍ！２が絶縁１）１２に、ゲート電極１）がゲート電極
１３に替わっている。Compared to the case shown in FIG. 3, this FET has an insulation J1
m! 2 is replaced with an insulator 1) 12, and the gate electrode 1) is replaced with a gate electrode 13.
即ち、ソース電極６とゲート電極１３との間およびドレ
イン電極７とゲート電極１３との間の絶縁体が端面を半
導体基板１に接する絶縁膜１２でなっているため、ソー
ス電極６とゲート電極１３との間隙寸法ａおよびドレイ
ン電極７とゲート電極１３との間隙寸法すが、絶縁膜１
２の厚さ寸法になって第３図（ｆ）図示より小さくなっ
ている。 、このため、このＦＥＴは従来よりソース
抵抗が小さくなり、然も、ソース電極６とドレイン電極
７との間隔も従来より小さくすることが出来てＩＣ形成
の際に高集積化が容易になる。That is, since the insulator between the source electrode 6 and the gate electrode 13 and between the drain electrode 7 and the gate electrode 13 is the insulating film 12 whose end face is in contact with the semiconductor substrate 1, the source electrode 6 and the gate electrode 13 are The gap dimension a between the drain electrode 7 and the gate electrode 13 and the gap dimension a between the insulating film 1
2, which is smaller than that shown in FIG. 3(f). Therefore, this FET has a lower source resistance than the conventional FET, and the distance between the source electrode 6 and the drain electrode 7 can also be made smaller than the conventional one, making it easier to achieve high integration when forming an IC.
このＦＩＥＴの製造方法は以下の如くである。The method for manufacturing this FIET is as follows.
先ず〔図（ａ）参照〕、第３図（ａ）図示と同様にして
、半導体基板１上に絶縁膜２とレジスト膜３を被着して
マスク窓４を形成する。First, as shown in FIG. 3(a), an insulating film 2 and a resist film 3 are deposited on a semiconductor substrate 1 to form a mask window 4. Referring to FIG.
ここでは、ステンシル構造のマスク窓４が形成出来れば
よいので、絶縁膜２とレジスト膜３とを合わせた構成を
二層または三層構成のレジス）ＩＮなどにしても良い。Here, since it is sufficient to form the mask window 4 having a stencil structure, the combined structure of the insulating film 2 and the resist film 3 may be a two-layered or three-layered resist (IN).
次いで〔図山）参照〕、第３図図示と同様にしてソース
電極およびドレイン電極を形成する金属膜５ （例えば
＾ｕＧｅ−Ａｕの二層構成）を例えば蒸着により被着し
てマスク窓４内にソース電極６とドレイン電極７を形成
し、続いてソース電極６およびドレイン電極７それぞれ
の露出面を覆い端面が基板１に接するように例えば窒化
シリコン（ＳｉＮ）の絶縁１）！１２を例えば低温スパ
ッタリングにより被着する。Next, in the same manner as shown in FIG. 3, a metal film 5 (for example, a two-layer structure of uGe-Au) forming a source electrode and a drain electrode is deposited, for example, by vapor deposition, and is deposited inside the mask window 4. A source electrode 6 and a drain electrode 7 are formed on the substrate 1, and then the exposed surfaces of the source electrode 6 and the drain electrode 7 are covered so that their end surfaces are in contact with the substrate 1. 12 is deposited, for example, by low temperature sputtering.
ここで絶縁膜１２の材料をＳｉＮにしたのは、後部の絶
縁膜２の除去に際して除去されないようにするためで、
絶縁膜２の材料を例えばレジストにした場合には、５ｉ
Ｏｚにしても良い。The reason why the material of the insulating film 12 is made of SiN is to prevent it from being removed when the rear insulating film 2 is removed.
When the material of the insulating film 2 is, for example, resist, 5i
It may be set to oz.
金属膜５および絶縁膜１２は、言うまでもなくレジスト
膜３上にも被着する。Needless to say, the metal film 5 and the insulating film 12 are also deposited on the resist film 3.
次いで〔図（Ｑ）参照〕、レジスト膜３と共に金属膜５
および絶縁膜１２をリフトオフし、更に絶縁膜２をエツ
チング除去して基板１を表出させる。Next [see figure (Q)], the metal film 5 is formed together with the resist film 3.
Then, the insulating film 12 is lifted off, and the insulating film 2 is further removed by etching to expose the substrate 1.
次いで（図（ｄ）参照〕、絶縁膜１２をマスクにして基
板１のｎ型ＧａＡｓ層ＩＣを選択的にエツチング（ゲー
トリセス）しゲート電極形成領域９ａを形成する。Next (see Figure (d)), using the insulating film 12 as a mask, the n-type GaAs layer IC of the substrate 1 is selectively etched (gate recessed) to form a gate electrode forming region 9a.
このエツチングはウェットまたはドライの何れでも可能
であるが、ヘテロ接合ＦＥＴの場合は特性の制御性の点
からドライエツチングが望ましい。This etching can be done either wet or dry, but in the case of a heterojunction FET, dry etching is preferred from the viewpoint of controllability of characteristics.
次いで（図（ｅ）参照〕、例えばＴｉ−Ｐｔ−篩の三層
でなりゲート電極を形成する金Ｈ１）１０を例えば蒸着
により被着する。さすれば、金属膜１０はゲート形成領
域９ａを充填すると共に全面に形成される。Then (see figure (e)) gold H1 10 is deposited, for example by vapor deposition, which consists of three layers of Ti--Pt-sieve and forms the gate electrode. Then, the metal film 10 fills the gate formation region 9a and is formed over the entire surface.
次いで〔図（ｆ）参照〕、金属１ｇ１）０をバターニン
グしてゲート電極１３を形成し、ソース電極６、ドレイ
ン電極７およびゲート電極１３の形成を完了する。Next [see Figure (f)], the metal 1g1)0 is patterned to form the gate electrode 13, and the formation of the source electrode 6, drain electrode 7, and gate electrode 13 is completed.
この後は図示を省略しであるが従来と同様に、絶縁膜の
被着、コンタクトホールの形成、配線の形成などの工程
を経て、所望のへテロ接合ＦＥＴを完成させることが出
来る。Thereafter, although not shown, the desired heterojunction FET can be completed through steps such as depositing an insulating film, forming contact holes, and forming interconnections in the same manner as in the conventional method.
以上説明したように、本発明の構成によれば、ソース電
極とゲート電極との間隙寸法およびドレイン電極とゲー
ト電極との間隙寸法を従来より小さくすることが可能な
ＦＥＴおよびその製造方法が提供出来て、例えばヘテロ
接合ＦＥＴにおいて、イオン注入することなしにソース
抵抗を容易に低減させて特性を向上させると共Ｃご、Ｉ
Ｃ形成の際の高集積化を容易にさせることを可能にさせ
る効果がある。As explained above, according to the configuration of the present invention, it is possible to provide an FET and a method for manufacturing the same in which the gap size between the source electrode and the gate electrode and the gap size between the drain electrode and the gate electrode can be made smaller than conventional ones. For example, in a heterojunction FET, the source resistance can be easily reduced and the characteristics improved without ion implantation.
This has the effect of facilitating high integration during C formation.
第１図は本発明の要旨説明図、
第２図（ａｌ〜（ｆ）は本発明によるＦＥＴの実施例に
ついてその構成と製造手順の要部を示す工程順側断面図
、
第３図ｆａ）〜（ｆ）は従来のへテロ接合ＦＥＴ０例に
ついてその製造手順の要部を示す工程順側断面図である
。
第１図へ・第３図においで１．
１、１Ａは半導体基板、
！ａはノンドープＧａＡｓ基体、
１ｈはｎ型ＡｌＧａＡｓ層、
１ｃはｎ型Ｇａｎ５Ｎ、
２．１２は絶縁膜、
３．８は！／シスト１漠、
４．８ａばマスク窓、
５、ｌＯは金屈欣、
６はソース電極、
７はドレイン電極、
９．９ａはゲーｌ〜電極形成領域、
１）．１３はゲート電極である。Fig. 1 is an explanatory diagram of the gist of the present invention; Fig. 2 (al to f) are side sectional views in the order of steps showing the configuration and main parts of the manufacturing procedure of an embodiment of the FET according to the present invention; Fig. 3 fa) - (f) are step-order side cross-sectional views showing the main parts of the manufacturing procedure for an example of a conventional heterojunction FET. To Figure 1/In Figure 3 1. 1, 1A is a semiconductor substrate, ! a is a non-doped GaAs substrate, 1h is an n-type AlGaAs layer, 1c is an n-type Gan5N, 2.12 is an insulating film, 3.8 is! / cyst 1, 4.8a is a mask window, 5, 1O is a metal oxide, 6 is a source electrode, 7 is a drain electrode, 9.9a is a gate electrode formation region, 1). 13 is a gate electrode.
Claims (2)
よびドレイン電極（７）とゲート電極（１３）との間の
絶縁体が絶縁膜（１２）でなり、 該絶縁膜（１２）の端面がトランジスタを形成する半導
体基板（１Ａ）に接していることを特徴とする電界効果
トランジスタ。(1) The insulator between the source electrode (6) and the gate electrode (13) and between the drain electrode (7) and the gate electrode (13) is an insulating film (12), and the insulating film (12) A field-effect transistor characterized in that an end face of the field-effect transistor is in contact with a semiconductor substrate (1A) forming the transistor.
）およびドレイン電極（７）を形成し、更に両電極（６
）、（７）それぞれの露出面を選択的に覆う絶縁膜（１
２）を形成する工程と、 上記形成された両絶縁膜（１２）の間にゲート電極材料
を充填してゲート電極（１３）を形成する工程とを含ん
でなることを特徴とする電界効果トランジスタの製造方
法。(2) Source electrode (6) in contact with the surface of the semiconductor substrate (1A)
) and drain electrode (7), and further both electrodes (6
), (7) an insulating film (1
2); and a step of filling a gate electrode material between the two insulating films (12) formed above to form a gate electrode (13). manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4580485A JPS61204984A (en) | 1985-03-08 | 1985-03-08 | Field effect transistor and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4580485A JPS61204984A (en) | 1985-03-08 | 1985-03-08 | Field effect transistor and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61204984A true JPS61204984A (en) | 1986-09-11 |
Family
ID=12729451
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4580485A Pending JPS61204984A (en) | 1985-03-08 | 1985-03-08 | Field effect transistor and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61204984A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007032517A (en) * | 2005-07-29 | 2007-02-08 | Kayaba Ind Co Ltd | Variable displacement vane pump |
-
1985
- 1985-03-08 JP JP4580485A patent/JPS61204984A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007032517A (en) * | 2005-07-29 | 2007-02-08 | Kayaba Ind Co Ltd | Variable displacement vane pump |
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