JPS61203564U - - Google Patents
Info
- Publication number
- JPS61203564U JPS61203564U JP1985088034U JP8803485U JPS61203564U JP S61203564 U JPS61203564 U JP S61203564U JP 1985088034 U JP1985088034 U JP 1985088034U JP 8803485 U JP8803485 U JP 8803485U JP S61203564 U JPS61203564 U JP S61203564U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit device
- islands
- lead frame
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第1図は本考案一実施例に用いるリードフレー
ムの平面図、第2図は従来のリードフレームの平
面図である。
1……リード端子、2……先端部、3……リー
ド端子、4……先端部、5……ボンデイング線、
7……集積回路素子、8……アイランド、9……
リード端子、10……先端部、11……金属細線
、12……アイランド、13……集積回路素子、
14……リード端子。
FIG. 1 is a plan view of a lead frame used in an embodiment of the present invention, and FIG. 2 is a plan view of a conventional lead frame. 1... Lead terminal, 2... Tip, 3... Lead terminal, 4... Tip, 5... Bonding wire,
7... Integrated circuit element, 8... Island, 9...
Lead terminal, 10...Tip, 11...Metal thin wire, 12...Island, 13...Integrated circuit element,
14...Lead terminal.
Claims (1)
いて、リード端子のステツチ側の位置を集積回路
素子の取り付けられるアイランドに対して多重に
配置したリードフレームを用いたことを特徴とす
る集積回路装置。 1. An integrated circuit device characterized in that a lead frame used in an integrated circuit device is used, in which the stitch side positions of lead terminals are arranged multiple times with respect to islands to which integrated circuit elements are attached.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985088034U JPS61203564U (en) | 1985-06-11 | 1985-06-11 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985088034U JPS61203564U (en) | 1985-06-11 | 1985-06-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61203564U true JPS61203564U (en) | 1986-12-22 |
Family
ID=30640795
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1985088034U Pending JPS61203564U (en) | 1985-06-11 | 1985-06-11 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61203564U (en) |
-
1985
- 1985-06-11 JP JP1985088034U patent/JPS61203564U/ja active Pending
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