JPS61201460A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61201460A JPS61201460A JP60042196A JP4219685A JPS61201460A JP S61201460 A JPS61201460 A JP S61201460A JP 60042196 A JP60042196 A JP 60042196A JP 4219685 A JP4219685 A JP 4219685A JP S61201460 A JPS61201460 A JP S61201460A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- semiconductor device
- degree
- type
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 150000001875 compounds Chemical class 0.000 claims abstract description 6
- 230000000295 complement effect Effects 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 8
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229910021341 titanium silicide Inorganic materials 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000010410 layer Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 208000033809 Suppuration Diseases 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 241000218645 Cedrus Species 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 206010062717 Increased upper airway secretion Diseases 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 208000026435 phlegm Diseases 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、半導体装置、特にＭＩＳ型半導体装置装構造
に関する０
（従来技術とその問題点）
絶縁体上に設けられた半導体膜に形成したＭＩ８型半導
体装置いわゆる８ ０ Ｉ （８ｅｍｉｃｏｎｄｕｃｔ
ｏｒｏｎ Ｉｎ５ａｌａｔｏｒ ）構造のＭＩＳ型半導
体装置は従来のＭＩ８１１半導体装置に比較して接合容
量及び配線容量が小さく素子分離が完全かつ簡便である
ことから高速の大規模集積回路（ＬＳＩ）に適した半導
体装置であるといわれる。例えば電子材料。Detailed Description of the Invention (Industrial Application Field) The present invention relates to semiconductor devices, particularly MIS type semiconductor device structure. MI8 type semiconductor device, so-called 80I (8emiconduct
The MIS type semiconductor device with the (oron in5alator) structure has smaller junction capacitance and wiring capacitance than the conventional MI811 semiconductor device, and element isolation is complete and simple, making it suitable for high-speed large-scale integrated circuits (LSI). It is said that For example, electronic materials.
１９８２年１月の５４ページから１０４ページ掲載の中
野元雄、佐々木伸夫による文献＠８０８／ＣＭＯ８デバ
イス”においては、第３図（ａｌに示した５Ｏ８（５ｉ
ｌｉｃｏｎ ｏｎ ８ａｐｐｈｌｒｅ ）構造のＣ’Ｍ
Ｏ１ｌｊ半導体装置のような構造が示されている。ＳＯ
Ｓ構造は８０Ｉ構造の一例であり、これに対応するＣＭ
ＯＢインバータ回路素子の平面図を第３図（ｂ）に示す
口
ここで１はナファイヤ基板、２は激化膜、３はＮ影領域
、４はＰ影領域、５はＰＶソース・ドレイン領域、６は
Ｎヘソース・ドレイン領域であり。5O8 (5i
licon on 8apphlre) structure of C'M
A structure similar to an O1lj semiconductor device is shown. S.O.
The S structure is an example of the 80I structure, and the corresponding CM
A plan view of the OB inverter circuit element is shown in FIG. 3(b). Here, 1 is a Naphire substrate, 2 is an intensified film, 3 is an N shadow region, 4 is a P shadow region, 5 is a PV source/drain region, and 6 is the N source/drain region.
７はＰ）多結晶シリコン、８はＮ〜多結晶シリコン、９
はＡＩ！配線である〇
しかしながら、近年、従来の半導体基板上に形成したＭ
ＩＳ型半導体装置においても微細な素子分離技術が発達
し、ＳＯＩ構造のＭＩＳ型半導体装置と同程度の集積化
が可能となってきた。これに対し最近８０Ｉ構造のＭＩ
Ｓ型半導体装置においてさらに集積度を向上させる構造
が提案されている。第４図（ａ）（ｂ）はその改善され
たＳＯ８構造のＣＭＯ８インバータ回路素子の模式的断
面図と対応する平面図である。ここで１〜９は第３図の
１〜９と同じである。この構造はＮＭＯＳトランジスタ
とＰＭＯ８）７ンジスタのドレイン同士を接合せしめそ
の上部に少なくとも接合境界が含まれるように開口部を
形成した後Ａｔ配線を行うことによって、 Ｎ＞、
ｐ“形いずれのドレイン領域に対してもオーミックな接
続が得られるところに特徴がある。7 is P) polycrystalline silicon, 8 is N~polycrystalline silicon, 9
is AI! However, in recent years, M
Fine element isolation technology has also been developed for IS type semiconductor devices, and it has become possible to integrate them to the same degree as MIS type semiconductor devices with an SOI structure. On the other hand, recently, MI of 80I structure
Structures have been proposed to further improve the degree of integration in S-type semiconductor devices. FIGS. 4(a) and 4(b) are a schematic cross-sectional view and a corresponding plan view of the improved SO8 structure CMO8 inverter circuit element. Here, 1 to 9 are the same as 1 to 9 in FIG. This structure connects the drains of an NMOS transistor and a PMO8)7 transistor, forms an opening above it so that at least the junction boundary is included, and then performs At wiring.
The feature is that ohmic connection can be obtained to any p" type drain region.
この構造によれば従来のＳＯＩ構造のＭＩＳ型半導体装
置によるインバータ回路素子に比べてさらに集積化する
ことが可能となる。According to this structure, it is possible to further integrate the inverter circuit element using a conventional MIS type semiconductor device having an SOI structure.
ところが、よシ高遠のＬＳＩ’ｉ目指しトランジスタの
縮少化を進めていくと、前記改良盤の８０Ｉ構造の半導
体装置の場合も集積度に限界が生じてくる。すなわちト
ランジスタの縮小化にともないコンタクト孔の面積を縮
小するとコンタクト孔の抵抗は増大しＬ８Ｉの高速化を
妨げる要因となる０従ってコンタクト穴の面積の縮小化
を制限させるを得なくなり、そのため前記改良型のＳＯ
Ｉ構造の半導体装置の場合もその集積度はコンタクト孔
の面積に制限されてそれ以上の集積化が不可能となる。However, as the number of transistors is reduced with the aim of achieving ever-higher LSI'i, there will be a limit to the degree of integration even in the semiconductor device of the improved 80I structure. In other words, when the area of the contact hole is reduced as the size of the transistor is reduced, the resistance of the contact hole increases, which becomes a factor that hinders the speeding up of L8I. S.O.
In the case of an I-structure semiconductor device, the degree of integration is also limited by the area of the contact hole, making further integration impossible.
以上のように、従来の半導体装置は高速・高集積のＬＳ
Ｉを形成するうえで限界が明らかであり将来的に重大な
問題を有している０
（発明の目的）
本発明は上記問題点を除去し九ＳＯＩ構造のＭＩＳ型半
導体ｉｔの構造を提供することを目的とする〇
（発明の構成）
本発明によれば絶縁体上に設けられた半導体膜に形成し
た相補型のＭＩＳ型半導体装置において。As mentioned above, conventional semiconductor devices are high-speed, highly integrated LS
There are obvious limitations in forming I, and there will be serious problems in the future. (Objective of the Invention) The present invention eliminates the above problems and provides a MIS type semiconductor IT structure with an SOI structure. According to the present invention, there is provided a complementary MIS type semiconductor device formed on a semiconductor film provided on an insulator.
相対する導電型のＭＩＳ型トランジスタのドレイン領域
を含むように金属または金属と半導体の化合物の層が形
成され、次いでその上部にゲート電極が接続されること
によって前記相対する導電製のＭＩＳ型トランジスタの
ドレイン領域とゲート電極がオーミックに接続されてい
ることを特徴とする半導体装置が得られる。A layer of metal or a metal-semiconductor compound is formed so as to include the drain region of the MIS transistor of the opposing conductivity type, and then a gate electrode is connected to the upper part of the layer, so that the drain region of the MIS transistor of the opposing conductivity type is formed. A semiconductor device characterized in that the drain region and the gate electrode are ohmically connected is obtained.
（実施例）
まず、本発明による８０Ｉ構造のＭＩＳ型半導体装置の
実施例を説明する。(Example) First, an example of an 80I structure MIS type semiconductor device according to the present invention will be described.
第１図（ａ）（ｂ）はそれぞれ本発明によるＭＩＳ型半
導体装置の一実施例として本構造によシ形成したインバ
ータ回路素子の模式的断面図と平面図である０図中、３
〜６は第３図の３〜６と同じであシ。1(a) and 1(b) are a schematic cross-sectional view and a plan view of an inverter circuit element formed according to the present structure as an embodiment of the MIS type semiconductor device according to the present invention, respectively.
-6 are the same as 3-6 in Figure 3.
ｌＯは絶縁基板、１１は絶縁膜、１２はｐ＞半纏体膜、
１３はＮＶ半導体膜、１４は金属または金属と半導体の
化合物による膜、１５は配線である０本構造によればイ
ンバータ回路素子の出力に対応する相対する導電型のＭ
ＩＳ製）ランジスタのソース及びドレイン拡散層は金属
または金属と半導体の化合物による膜を介して次段のイ
ンバータ回路素子のゲートになるＰｌｔたＮ〜半導体膜
とオーミックな接続がとれている。従って本発明の構造
は従来構造のインバータ回路素子に比べてゲートにコン
タクト孔を開ける必要がないので集積度が向上し、また
コンタクト孔が減少したことからそのコンタクトの抵抗
分だけ低抵抗化することができ、さらにゲートによる配
線層と２−ス及びドレイン層に接続した配線層は別の層
に形成されるために配線の自由度が増すなどすぐれた特
性をもち、高速、高集積のＬＳＩに適した構造である。IO is an insulating substrate, 11 is an insulating film, 12 is a p>semiconductor film,
13 is an NV semiconductor film, 14 is a film made of a metal or a compound of a metal and a semiconductor, and 15 is a wiring. According to the 0-wire structure, M of the opposite conductivity type corresponds to the output of the inverter circuit element.
The source and drain diffusion layers of the transistor (manufactured by IS) are ohmically connected to the PltN semiconductor film which becomes the gate of the next stage inverter circuit element via a film made of metal or a compound of metal and semiconductor. Therefore, compared to inverter circuit elements with conventional structures, the structure of the present invention improves the degree of integration since it is not necessary to open a contact hole in the gate, and since the number of contact holes is reduced, the resistance can be reduced by the resistance of the contact. Furthermore, since the wiring layer connected to the gate and the wiring layer connected to the second and drain layers are formed in separate layers, it has excellent characteristics such as increased freedom in wiring, making it suitable for high-speed, highly integrated LSIs. It has a suitable structure.
次に本発明による構造を実現するための製造工程につい
て実施例に基づき説明する。Next, manufacturing steps for realizing the structure according to the present invention will be explained based on examples.
第２図（ａ）〜（ｄ）は特に本構造によるＳＯＳ構造の
Ｎ４及びＰ＋＃結晶シリコンゲートのＣＭＯＳインバー
タ回路素子の製造主要工程を示した模式的断面図である
。図中１． ３〜９は第１図の１，３〜９と同じであり
、１６はゲート酸化膜、１７はチタンシリサイド膜、１
８は層間酸化膜である０まずサファイヤ基板１の上に厚
さ０．５μｍのシリコン島を形成し、次に熱酸化してゲ
ート酸化膜１６厚さ４００Ｘに形成し、さらに不純物の
イオン注入によりてＮ影領域３、Ｐ影領域４を形成する
。〔第２図（ａ）〕
次にシリコン島のＮ影領域３とＰ影領域４の境界部分の
ゲート酸化膜４をパターンユングして下地のシリコン膜
が露出するように開口部を設け、露出したシリコン膜の
上部をチタンシリサイド化する。（第２図（ｂ））ここ
でチタンシリサイドは次のような工程で形成される。ま
ずゲート酸化膜４に開口部を設けた試料全面にチタン膜
をスパッタリング法により厚さ４００Ｘ形成した後水素
雰囲気中で６００℃、２０分アニールする。このとき開
口部のシリコンが露出した部分のみがチタンシリサイド
化する０次にこの試料をｆ（（Ｊ ： ）Ｉ、Ｏ，：
Ｈ，０＝ｌ：ｌ：４混合溶液によシ煮沸洗浄１０分、及
び純水洗浄１０分処理した後窒素雰囲気中８００℃３０
分アニールする。ここで酸洗浄を行うことによりチタン
膜がはくりされ、第２図σバｂ）のように開口部のみチ
タンシリサイドが残る。FIGS. 2(a) to 2(d) are schematic cross-sectional views showing the main steps of manufacturing a CMOS inverter circuit element having an SOS structure of N4 and P+# crystal silicon gates according to the present structure. 1 in the figure. 3-9 are the same as 1, 3-9 in FIG. 1, 16 is a gate oxide film, 17 is a titanium silicide film, 1
8 is an interlayer oxide film 0 First, a silicon island with a thickness of 0.5 μm is formed on the sapphire substrate 1, and then thermally oxidized to form a gate oxide film 16 with a thickness of 400×, and further by ion implantation of impurities. N shadow area 3 and P shadow area 4 are formed. [Figure 2 (a)] Next, the gate oxide film 4 at the boundary between the N shadow region 3 and the P shadow region 4 of the silicon island is patterned to provide an opening so that the underlying silicon film is exposed. The upper part of the silicon film thus prepared is made into titanium silicide. (FIG. 2(b)) Here, titanium silicide is formed in the following steps. First, a titanium film is formed to a thickness of 400× by sputtering on the entire surface of a sample in which an opening is provided in the gate oxide film 4, and then annealed at 600° C. for 20 minutes in a hydrogen atmosphere. At this time, only the exposed silicon part of the opening becomes titanium silicide.
H,0=l:l: After 10 minutes of boiling and washing with a 4 mixed solution and 10 minutes of pure water washing, the mixture was heated at 800°C at 30°C in a nitrogen atmosphere.
Anneal for minutes. By carrying out acid cleaning, the titanium film is peeled off, leaving titanium silicide only in the openings, as shown in Fig. 2, b).
次に（ｂ）の状態の試料に多結晶シリコンｔｏ、５μｍ
ＣＶＤ法によ）形成しゲート及び配線領域をパターンユ
ングした後、不純物のイオン注入によシ自己整合的にｐ
％ソース・ドレイン領域５．Ｎ”＠ソース・ドレイン領
域６、Ｐ＋３＃多結晶シリコン７゜Ｎ１多結晶シリコン
８を形成する（第２図ｔｃ＞ ）。Next, the sample in the state (b) was coated with polycrystalline silicon to a thickness of 5 μm.
After patterning the gate and wiring regions (by CVD method), self-aligned p
% source/drain region5. N''@source/drain regions 6, P+3# polycrystalline silicon 7°N1 polycrystalline silicon 8 are formed (FIG. 2 tc>).
ここで開口部の上部のＮ”ｌｂ、 ｐ形多結晶シリコ
ンは開口部のサイズよシ小さく形成しなければならない
０こうすることによシ開ロ部のチタンシリサイド１４と
す形ソース・ドレイン領域５Ｎ１ソース・ドレイン領域
６との間の接続がとれる。この結果、Ｐｌ及びＮ〜ソー
ス・ドレイン領域５，６とＮ〜及びＰ１多結晶シリコン
７．８とのオーミックな接続がチタンシリサイド１４ｆ
ｔ介してとることができる。Here, the N''lb p-type polycrystalline silicon at the top of the opening must be formed smaller than the size of the opening.In this way, the titanium silicide 14 at the bottom of the opening and the shaped source/drain region 5N1 source/drain region 6. As a result, an ohmic connection between Pl and N~ source/drain regions 5, 6 and N~ and P1 polycrystalline silicon 7.8 is established through titanium silicide 14f.
It can be taken via t.
次に（Ｃ）の状態の試料に層間絶縁膜全０．５μｍＣＶ
Ｄ法によシ形成しコンタクト孔をパターンユングした後
、Ａｌ配線９を形成する◎（第２図（ｄ））以上が本発
明の構造を実現するための製造工程の一実施例である◎
尚本実施例では相対する導電型の半導体の間のオーミッ
クな接続をとる方法としてチタンシリサイドの膜を用い
たが、これは他の金属シリサイドまた金属でも可能であ
る０以上、ＳＯＳ構造のＣＭＯＳインバータ回路素子を
例に製造工程を説明したが、一般的なＭＩＤ構造のイン
バータ回路素子に適用できることが明らかである。また
本発明の構造は単−導電凰の半導体ゲートや金属ゲート
の相補型ＭＩＳ型半導体装置にも適用でき、さらにイン
バータ回路素子に限らず他の回路素子５の適用も可能で
ある。Next, on the sample in state (C), the interlayer insulating film was coated with a total CV of 0.5 μm.
After forming a contact hole by the D method and patterning a contact hole, an Al wiring 9 is formed (Fig. 2(d)). The above is an example of the manufacturing process for realizing the structure of the present invention.
In this example, a titanium silicide film was used as a method for making an ohmic connection between semiconductors of opposing conductivity types, but this can also be done with other metal silicides or metals. Although the manufacturing process has been explained using a circuit element as an example, it is clear that the present invention can be applied to an inverter circuit element having a general MID structure. Further, the structure of the present invention can be applied to a complementary MIS type semiconductor device having a single-conducting semiconductor gate or a metal gate, and can also be applied to not only the inverter circuit element but also other circuit elements 5.
（発明の効果）
本発明によれば、従来のＭＩＳ型半導体装置の構造に比
較して、コンタクト孔が少ないために集積度が高く、低
抵抗化が可能であり、また配線の自由度が増すなどすぐ
れた特性をもつ半導体装置が得られる。(Effects of the Invention) According to the present invention, compared to the structure of a conventional MIS type semiconductor device, there are fewer contact holes, so the degree of integration is higher, lower resistance is possible, and the degree of freedom in wiring is increased. A semiconductor device with excellent properties such as these can be obtained.
第１図（ａ）（ｂ）はそれぞれ本発明による半導体装置
の基本的な一実施例として本構造により形成したインバ
ータ回路素子の模式的断面図と平面図。
第２図（ａ）〜ｆ、ｆ）は本発明の半導体装置？実現す
るための製造工程の実施例を示した模式的断面図、第３
図ｔａｌ、 （ｂｌはそれぞれ従来のＳＯ′Ｘ構造のＭ
Ｉ８塁半導体装置の模式的断面図と平面図。
第４図（ａｌ、（ｂ）はそれぞれ改良型の従来の８０Ｉ
構造のＭＩＳ型半導体装置の模式的断面図と平面図であ
る。
ｌ・・・サファイヤ基板、２・・・酸化膜、３・・・Ｎ
影領域、４・・・Ｐ影領域、５・・・Ｐ１形ソース・ド
レイン領域、６・・・１形ソース・ドレイン領域、７−
・・ｒ形多晶シリコン、８・・・Ｎ゛形多結晶シリコン
、９・・・ＡＩ！配線、１０・・・絶縁基板、１１・・
・絶縁膜、１２・・・Ｐ４形半導体膜、１３・・・Ｎ１
杉半導体膜、１４・・・金属または金属と半導体の化合
物の膜、１５・・・配線。
１６・・・ゲート酸化膜、１７・・・チタンシリサイド
膜、１８・・・層間酸化膜口
（ば人ど山内 ｉ（コ（１：
第１図
４−Ｎ’彰ソー人・トーレイン々會鐸ｋ ／７−
−−干フン’／’Ｉ’ワ”イド膿Ｉａ−−一層間―祇化
膿
￥３図
１−−−−リ゛フフイヤ差１反 乙 −Ｎ”Ｍ’
、”ノース・ドレイン＠賊２−−−６費化Ｆｌｌｊ
’７−Ｆη話号ＦＦ１晶シリコン３−−−
Ｎ 形＠ Ｋ ８−＝ Ｎ ’Ｗ３−ｙｙ＃
ｇ晶シリコン４−−−１’ πシ４１陶ｔｌｉ
９ −−・Ａ１＠ｉ二牙肩（５−Ｆ’ｆｉ／−
ス−）１ｄ、４Ｉ費に５Ａ ４ 図FIGS. 1(a) and 1(b) are a schematic sectional view and a plan view, respectively, of an inverter circuit element formed according to the present structure as a basic embodiment of a semiconductor device according to the present invention. 2(a) to 2(f) are semiconductor devices of the present invention? A schematic cross-sectional view showing an example of the manufacturing process for realizing the third
Figure tal, (bl is M of the conventional SO'X structure, respectively)
A schematic cross-sectional view and a plan view of an I8 base semiconductor device. Figure 4 (al, (b)) is an improved version of the conventional 80I.
FIG. 2 is a schematic cross-sectional view and a plan view of a MIS type semiconductor device having a structure. l...Sapphire substrate, 2...Oxide film, 3...N
Shadow area, 4...P shadow area, 5...P1 type source/drain area, 6...1 type source/drain area, 7-
...R-type polycrystalline silicon, 8...N-type polycrystalline silicon, 9...AI! Wiring, 10... Insulating substrate, 11...
・Insulating film, 12...P4 type semiconductor film, 13...N1
Cedar semiconductor film, 14...Metal or metal/semiconductor compound film, 15... Wiring. 16...Gate oxide film, 17...Titanium silicide film, 18...Interlayer oxide film k/7-
--Dried phlegm'/'I'W"id pus Ia--One layer-Gi suppuration ￥3 Figure 1-----Reffire difference 1 anti-N"M'
, “North Drain @ Thief 2---6-cost Fllj
'7-Fη episode number FF1 crystal silicon 3---
N type @ K 8-= N 'W3-yy#
g-crystal silicon 4---1' πshi41 tli
9 --・A1@i double fang shoulder (5-F'fi/-
S-) 1d, 5A for 4I expenses 4 Fig.
Claims (1)
Ｓ型半導体装置において、相対する導電型のＭＩＳ型ト
ランジスタのドレイン領域を含むように金属または金属
と半導体の化合物の層が形成され、次いでその上部にゲ
ートが接続されることによって前記相対する導電型のＭ
ＩＳ型トランジスタのドレイン領域とゲートがオーミッ
クに接続されていることを特徴とする半導体装置。Complementary MI formed on a semiconductor film provided on an insulator
In an S-type semiconductor device, a layer of metal or a metal-semiconductor compound is formed so as to include the drain regions of MIS transistors of opposing conductivity types, and then a gate is connected to the top of the layer to include the drain regions of MIS transistors of opposing conductivity types. M of
A semiconductor device characterized in that a drain region and a gate of an IS type transistor are ohmically connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60042196A JPH0626244B2 (en) | 1985-03-04 | 1985-03-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60042196A JPH0626244B2 (en) | 1985-03-04 | 1985-03-04 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61201460A true JPS61201460A (en) | 1986-09-06 |
| JPH0626244B2 JPH0626244B2 (en) | 1994-04-06 |
Family
ID=12629251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60042196A Expired - Lifetime JPH0626244B2 (en) | 1985-03-04 | 1985-03-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0626244B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63137467A (en) * | 1986-11-29 | 1988-06-09 | Sony Corp | Semiconductor integrated circuit device |
| JPS6453576A (en) * | 1987-08-25 | 1989-03-01 | Ricoh Kk | Semiconductor device |
| JPH04206971A (en) * | 1990-11-30 | 1992-07-28 | Sharp Corp | Film semiconductor device |
| US5374494A (en) * | 1991-03-13 | 1994-12-20 | Canon Kabushiki Kaisha | Electrophotographic photosensitive member, electrophotographic apparatus, device unit, and facsimile machine employing the same |
| JPH11289018A (en) * | 1997-12-31 | 1999-10-19 | Samsung Electronics Co Ltd | Semiconductor device and manufacture thereof |
| US7326959B2 (en) | 2004-05-24 | 2008-02-05 | Samsung Sdi Co., Ltd. | Thin film transistor with common contact hole and fabrication method thereof |
| US7952097B2 (en) | 1993-02-15 | 2011-05-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
-
1985
- 1985-03-04 JP JP60042196A patent/JPH0626244B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63137467A (en) * | 1986-11-29 | 1988-06-09 | Sony Corp | Semiconductor integrated circuit device |
| JPS6453576A (en) * | 1987-08-25 | 1989-03-01 | Ricoh Kk | Semiconductor device |
| JPH04206971A (en) * | 1990-11-30 | 1992-07-28 | Sharp Corp | Film semiconductor device |
| US5374494A (en) * | 1991-03-13 | 1994-12-20 | Canon Kabushiki Kaisha | Electrophotographic photosensitive member, electrophotographic apparatus, device unit, and facsimile machine employing the same |
| US7952097B2 (en) | 1993-02-15 | 2011-05-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
| JPH11289018A (en) * | 1997-12-31 | 1999-10-19 | Samsung Electronics Co Ltd | Semiconductor device and manufacture thereof |
| US7326959B2 (en) | 2004-05-24 | 2008-02-05 | Samsung Sdi Co., Ltd. | Thin film transistor with common contact hole and fabrication method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0626244B2 (en) | 1994-04-06 |
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