JPS61199950U - - Google Patents

Info

Publication number
JPS61199950U
JPS61199950U JP8422785U JP8422785U JPS61199950U JP S61199950 U JPS61199950 U JP S61199950U JP 8422785 U JP8422785 U JP 8422785U JP 8422785 U JP8422785 U JP 8422785U JP S61199950 U JPS61199950 U JP S61199950U
Authority
JP
Japan
Prior art keywords
signal
stereo
circuit
intermediate frequency
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8422785U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8422785U priority Critical patent/JPS61199950U/ja
Publication of JPS61199950U publication Critical patent/JPS61199950U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Superheterodyne Receivers (AREA)
  • Stereo-Broadcasting Methods (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図は本考案の一実施例を示すものである。 3……中間周波増幅回路、8……ステレオ復調
回路、15……制御回路。
The figure shows an embodiment of the present invention. 3... Intermediate frequency amplification circuit, 8... Stereo demodulation circuit, 15... Control circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 中間周波数信号を増幅する中間周波増幅回路と
、この中間周波数信号に含まれるパイロツト信号
を検出し、斯るパイロツト信号が所定レベル以上
となつた際、ステレオ受信状態に設定されると共
にステレオ表示回路を駆動制御するための信号を
出力するステレオ復調回路と、前記ステレオ表示
回路を駆動制御するための信号が所定時間継続し
たとき制御信号を出力する制御回路とを備え、こ
の制御信号に基づき前記中間周波増幅回路を広帯
域特性となるよう制御することを特徴とするAM
ステレオ受信機。
An intermediate frequency amplification circuit that amplifies an intermediate frequency signal and a pilot signal included in this intermediate frequency signal are detected, and when the pilot signal exceeds a predetermined level, the system is set to a stereo reception state and a stereo display circuit is activated. a stereo demodulation circuit that outputs a signal for drive control; and a control circuit that outputs a control signal when the signal for drive control of the stereo display circuit continues for a predetermined time; AM characterized by controlling an amplifier circuit to have broadband characteristics
stereo receiver.
JP8422785U 1985-06-04 1985-06-04 Pending JPS61199950U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8422785U JPS61199950U (en) 1985-06-04 1985-06-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8422785U JPS61199950U (en) 1985-06-04 1985-06-04

Publications (1)

Publication Number Publication Date
JPS61199950U true JPS61199950U (en) 1986-12-15

Family

ID=30633554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8422785U Pending JPS61199950U (en) 1985-06-04 1985-06-04

Country Status (1)

Country Link
JP (1) JPS61199950U (en)

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