JPS61193474A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61193474A
JPS61193474A JP60033746A JP3374685A JPS61193474A JP S61193474 A JPS61193474 A JP S61193474A JP 60033746 A JP60033746 A JP 60033746A JP 3374685 A JP3374685 A JP 3374685A JP S61193474 A JPS61193474 A JP S61193474A
Authority
JP
Japan
Prior art keywords
posts
row
rows
another
post
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60033746A
Other languages
Japanese (ja)
Other versions
JPH0446451B2 (en
Inventor
Nobuhisa Ishida
暢久 石田
Hideo Taniguchi
秀夫 谷口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP60033746A priority Critical patent/JPS61193474A/en
Publication of JPS61193474A publication Critical patent/JPS61193474A/en
Publication of JPH0446451B2 publication Critical patent/JPH0446451B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve sufficiently the reliability of bonding, by arranging posts so that the posts of one row are positioned between the posts of another row, so as to give a sufficient room for wire bonding. CONSTITUTION:Posts are arranged in such a manner that posts 4 are disposed in a first row and posts 5A and 5B in a plurality of second row. The posts 5A and 5B in the second rows are disposed so that the posts in one row are positioned between those in another row. An insulating layer 10 covering leads 6 communicating with the posts in the first row and an insulating layer 11 covering leads 7A communicating with the posts 5A in the uppermost one of the second rows are located between the rows respectively and are protuberant from the surface of a substrate, and wires 9A and 9B leading to the posts 5A and 5B are supported by the insulating layers 10 and 11 so that they are mounted on these layers. The posts 5A and 5B in the uppermost ones of the second rows can be spaced wide sufficiently from one another since the posts adjacent to one another are not juxtaposed closely, and therefore the width of the post 5A can be made large by an arrangement wherein the leads 6 passing nearby are made to bypass the posts appropriately.

Description

【発明の詳細な説明】 （産業上の利用分野） この発明は半導体装置特に基板上にダイボンディングさ
れた半導体素子とポストとをワイヤボン°　ディングし
て構成される半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a semiconductor device constructed by wire bonding a semiconductor element die-bonded onto a substrate and a post.

（従来の技術） 半導体チップ、集積回路等の半導体素子からなる半導体
装置では、基板上に前記半導体素子をダイボンディング
するとともに、基板上のポストと前記半導体素子のボン
ディングパットとを金線のようなワイヤでワイヤボンデ
ィングによって互いに接続するようにしたものはよく知
られている。(Prior Art) In a semiconductor device consisting of a semiconductor element such as a semiconductor chip or an integrated circuit, the semiconductor element is die-bonded onto a substrate, and the post on the substrate and the bonding pad of the semiconductor element are bonded using a wire such as a gold wire. It is well known that wires are connected to each other by wire bonding.

一方この種半導体装置ではその半導体素子の高密度化の
ためにボンディングパットのピッチを小さく、場合によ
っては千鳥状に並べるとともに、基板上のポストを千鳥
状に並べることが行われている′（実開昭５ｓ−１，ｏ
７ｇ４４号、公報参照）。しかしこのようにポストを千
鳥状に配列した場合は、隣合うワイヤに接続されるポス
トの間隔は広くとれるにしても、各ポストの幅を広くと
ることができず、そのためワイヤボンディングに余裕が
ないことに　　　　□より、その接着に信頼性が欠ける
といった欠点がある。On the other hand, in this type of semiconductor device, in order to increase the density of the semiconductor element, the pitch of the bonding pads is reduced, and in some cases, they are arranged in a staggered pattern, and the posts on the substrate are arranged in a staggered pattern. Kaisho 5s-1, o
7g44, publication). However, when the posts are arranged in a staggered manner like this, even though the distance between the posts connected to adjacent wires can be wide, it is not possible to make each post wide, so there is no margin for wire bonding. In particular, □ has the disadvantage that its adhesion is unreliable.

これを図面によって説明すると、第４図において１は基
板、２は半導体素子とし、この半導体素子には複数のボ
ンディングパラ’）−’３が設置されてあるものとする
。図示するボンデインクパラ１−３は千鳥状に配列され
である。４は第１の列のポスト、５は第２の列のポスト
で、前記第１の列のポストは半導体素子２に向い合うよ
うに並び、第２の列は第１の列よりも半導体素子２から
離れて並ぶようにしである。なお各ポストは基板１」二
に設置されである。To explain this with reference to the drawings, in FIG. 4, 1 is a substrate, 2 is a semiconductor element, and this semiconductor element is provided with a plurality of bonding plates')-'3. The bonded inks 1-3 shown in the figure are arranged in a staggered manner. 4 is a first column of posts, 5 is a second column of posts, the posts of the first column are arranged to face the semiconductor device 2, and the second column has more semiconductor devices than the first column. They should be lined up apart from 2. Note that each post is installed on the board 1''2.

各列のボス１〜は交互に並ぶことによって千鳥状に配列
されである。６は第１の列の各ポスト４に連なるリード
、７は第２の列の各ボス１−５に連なるり−１く、８は
第１の列のポスト４と一方の列の各ボンディングパラ１
〜３とを接続するワイヤ、９は第２の列のボス１〜５と
他の列の各ボンディングパットとを接続するワイヤで、
いずれもワイヤボンディングされである。このワイヤボ
ンディングは最初にワイヤをボンディングパット３に、
続いてボス１〜４または５にボンディングされる。The bosses 1 to 1 in each row are arranged in a staggered manner by lining up alternately. 6 is a lead connected to each post 4 in the first row, 7 is a lead connected to each boss 1-5 in the second row, and 8 is a lead connected to each post 4 in the first row and each bonding parameter in one row. 1
3, and 9 is a wire that connects the bosses 1 to 5 in the second row with each bonding pad in the other rows.
Both are wire bonded. For this wire bonding, first place the wire on bonding pad 3,
Subsequently, it is bonded to bosses 1 to 4 or 5.

ところでこの構成から理解されるように、第２の列のボ
ス１〜５は第１の列のボスｌ−４に連なる各リード６の
間に位置せしめられている。したかってこのポスト５の
幅はり一ド６の間隔に制限されるようになり、充分に広
くすることができないようになる。このために前記した
ようなボス１−５へのワイヤボンディングに余裕があま
りなく、そのためワイヤ９とポスト５との接着に対する
信頼性が欠けるようになるのである。By the way, as can be understood from this configuration, the bosses 1 to 5 in the second row are positioned between the respective leads 6 connected to the bosses l-4 in the first row. Therefore, the width of the post 5 is limited to the distance between the beams 6 and cannot be made sufficiently wide. For this reason, there is not much margin for wire bonding to the bosses 1-5 as described above, which results in a lack of reliability in bonding the wires 9 and the posts 5.

（発明が解決しようとする問題点） この発明はポストの間隔を充分狭くしてもなおポストの
幅を広くとれるようにし、これによってワイヤボンディ
ングによる接着の信頼性を向上せしめることを目的とす
る。(Problems to be Solved by the Invention) An object of the present invention is to make it possible to make the post width wide even if the distance between the posts is narrowed sufficiently, and thereby to improve the reliability of bonding by wire bonding.

（問題点を解決するための手段） この発明は基板上のボス１へを半導体素子側に沿って並
ぶ第１の列と、前記第１の列より前記半導体素子から離
れている位置に並ぶ複数の第２の列とによって構成し、
前記第２の列のポストを前記第１の列のポストとの間に
位置せしめるとともに、前記各第２の列のポストを、そ
の各列のポストの間に他の列のポストが位置するように
配置して構成したことを特徴とする。(Means for Solving the Problems) The present invention provides a first row arranged along the semiconductor element side toward the boss 1 on the substrate, and a plurality of rows arranged at a position farther from the semiconductor element than the first row. a second column of
The second row of posts is positioned between the first row of posts, and each second row of posts is positioned between the posts of the other row. It is characterized by being arranged and configured.

＝４− この発明を図によって説明する。なお第４図と同じ符合
を付した部分は同一または対応する部分を示す。第１図
の構成から理解できるように、この発明では第１のポス
ト４の列と複数の第２のボスｌ−５Ａ、、５Ｂの列とに
よってボス１〜を配列する。=4- This invention will be explained using figures. Note that parts with the same reference numerals as in FIG. 4 indicate the same or corresponding parts. As can be understood from the configuration shown in FIG. 1, in the present invention, the bosses 1 to 1 are arranged by a row of first posts 4 and a row of a plurality of second bosses 1-5A, 5B.

７Ａ、７Ｂは各ポスト５Ａ、５Ｂに連なるリードである
。各第２の列のポスト５Ａ、５Ｂは互いに他の列のポス
ト間に位置するように配置されである。7A and 7B are leads connected to the respective posts 5A and 5B. The posts 5A, 5B in each second row are arranged so as to be located between the posts in the other row.

］０は第１の列のポストに連なるリード６を覆う絶縁層
、１］は第２の列の最−１；端の列のボス１−５Ａに連
なるリード７Ａを覆う絶縁層で、何れも各列間にあって
、かつ基板表面から突出しており、ポスト５Ａ、５Ｂに
至るワイヤ９Ａ、９Ｂがこの絶縁層１０．１１の表面に
載るようにして支持されている。]0 is an insulating layer that covers the lead 6 connected to the post in the first row, 1] is an insulating layer that covers the lead 7A connected to the boss 1-5A in the second row, the most-1; end row; Wires 9A and 9B located between each row and protruding from the substrate surface and reaching posts 5A and 5B are supported so as to rest on the surface of this insulating layer 10.11.

（作用） 第１図の構成から理解できるように、第２の列のうちの
最」―端の列の各ポスト５Ａ、５Ｂの間隔は、第４図の
構成におけるように隣同志のポスト５が近接して並ぶこ
とがないので、このボス１へ５の間隔よりも充分広くす
ることができるようになる。したがってこのポスト５Ａ
の幅を、その付近を通るリード６を適当に逃すことによ
って、そのリードに邪魔をされることなく、広くするこ
とができるようになる。(Operation) As can be understood from the configuration of FIG. 1, the distance between the posts 5A and 5B in the end row of the second row is the same as that of the adjacent posts 5A and 5B as in the configuration of FIG. Since the two bosses are not lined up closely, the distance between the bosses 1 and 5 can be made sufficiently wider than that between the bosses 1 and 5. Therefore this post 5A
By appropriately allowing the lead 6 passing near the lead to escape, the width of the lead can be increased without being obstructed by the lead.

第３図は第２のポストの列を３列とした実施例である。FIG. 3 shows an embodiment in which the number of rows of second posts is three.

５Ａ〜５Ｃは第２の列のポストを、７Ａ〜７Ｃはポスト
５Ａ〜５Ｃに連なるリードを示す。5A to 5C indicate the posts of the second row, and 7A to 7C indicate the leads connected to the posts 5A to 5C.

また１２はポスト５Ｂに連なるリード７Ｂを覆う絶縁層
である。この構成においても、ポスト５Ａ〜５Ｃの間隔
が広くなり、したがって各ポストの幅を広くすることが
できるようになる。Further, 12 is an insulating layer that covers the lead 7B connected to the post 5B. Also in this configuration, the intervals between the posts 5A to 5C are wide, and therefore the width of each post can be increased.

なお絶縁層１０〜１２を設けておくと、これによってワ
イヤがこの上にのって支持されるので、これが垂れて基
板上の他のリードに接触するようなことはこれをもって
確実に回避できるようになる。Note that by providing the insulating layers 10 to 12, the wires are supported by being placed on top of the insulating layers 10 to 12, so that it is possible to reliably prevent the wires from sagging and coming into contact with other leads on the board. become.

（発明の効果） 以上詳述したようにこの発明によれば、第１の＝６− 列のポストと複数の第２の列のポストを用意し、各第２
の列のポストの間に他の第２の列のポストが位置するよ
うに配置したので、この第２の列のポストの間隔は広く
なり、したがって第１の列に連なるリードを適当に逃す
ことによって各第２の列のポストの幅を充分に広くする
ことができ、もってワイヤボンディングに余裕が出てく
るようになり、これによってその接着の信頼性が充分に
向上するようになるといった効果を奏する。(Effects of the Invention) As detailed above, according to the present invention, a first =6- column of posts and a plurality of second column posts are prepared, and each second
Since the posts in the second row are positioned between the posts in the second row, the spacing between the posts in the second row is wide, so that the leads connected to the first row can be appropriately missed. This makes it possible to make the width of each second row of posts sufficiently wide, thereby providing ample margin for wire bonding, thereby sufficiently improving the reliability of the bonding. play.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の実施例を示す平面図、第２図は同断
面図、第３図は他の実施例を示す平面図、第４図は従来
例を示す平面図である。FIG. 1 is a plan view showing an embodiment of the invention, FIG. 2 is a sectional view thereof, FIG. 3 is a plan view showing another embodiment, and FIG. 4 is a plan view showing a conventional example.

Claims (1)

【特許請求の範囲】[Claims] 　半導体素子のボンディングパットと基板上のポストと
をワイヤで接続してなる半導体装置において、前記ポス
トを前記半導体素子側に沿って並ぶ第１の列と、前記第
１の列より前記半導体素子から離れている位置に並ぶ複
数の第２の列とによって構成し、前記第２の列のポスト
を前記第１の列のポストとの間に位置せしめるとともに
、前記各第２の列のポストを、その各列のポストの間に
他の列のポストが位置するように配置してなる半導体装
置。In a semiconductor device in which a bonding pad of a semiconductor element and a post on a substrate are connected with a wire, the posts are arranged in a first row along the semiconductor element side and further away from the semiconductor element than the first row. a plurality of second rows lined up in a row, the posts in the second row are positioned between the posts in the first row, and the posts in each second row are A semiconductor device in which posts in each row are arranged between posts in another row.
JP60033746A 1985-02-21 1985-02-21 Semiconductor device Granted JPS61193474A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60033746A JPS61193474A (en) 1985-02-21 1985-02-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60033746A JPS61193474A (en) 1985-02-21 1985-02-21 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS61193474A true JPS61193474A (en) 1986-08-27
JPH0446451B2 JPH0446451B2 (en) 1992-07-30

Family

ID=12394977

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60033746A Granted JPS61193474A (en) 1985-02-21 1985-02-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61193474A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0382445A2 (en) * 1989-02-10 1990-08-16 Honeywell Inc. High density bond pad design
US5895977A (en) * 1996-08-08 1999-04-20 Intel Corporation Bond pad functional layout on die to improve package manufacturability and assembly
JP2007103423A (en) * 2005-09-30 2007-04-19 Renesas Technology Corp Semiconductor device and its manufacturing method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58107844U (en) * 1982-01-13 1983-07-22 株式会社東芝 thermal head
JPS594131A (en) * 1982-06-30 1984-01-10 Fujitsu Ltd Semiconductor package
JPS5914652A (en) * 1982-07-16 1984-01-25 Nec Corp Semiconductor package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58107844U (en) * 1982-01-13 1983-07-22 株式会社東芝 thermal head
JPS594131A (en) * 1982-06-30 1984-01-10 Fujitsu Ltd Semiconductor package
JPS5914652A (en) * 1982-07-16 1984-01-25 Nec Corp Semiconductor package

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0382445A2 (en) * 1989-02-10 1990-08-16 Honeywell Inc. High density bond pad design
EP0382445A3 (en) * 1989-02-10 1991-04-17 Honeywell Inc. High density bond pad design
US5895977A (en) * 1996-08-08 1999-04-20 Intel Corporation Bond pad functional layout on die to improve package manufacturability and assembly
JP2007103423A (en) * 2005-09-30 2007-04-19 Renesas Technology Corp Semiconductor device and its manufacturing method

Also Published As

Publication number Publication date
JPH0446451B2 (en) 1992-07-30

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