JPS61183971A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS61183971A JPS61183971A JP2383585A JP2383585A JPS61183971A JP S61183971 A JPS61183971 A JP S61183971A JP 2383585 A JP2383585 A JP 2383585A JP 2383585 A JP2383585 A JP 2383585A JP S61183971 A JPS61183971 A JP S61183971A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film
- layer
- source
- titanium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 27
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 20
- 239000010936 titanium Substances 0.000 claims abstract description 14
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 13
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 230000004888 barrier function Effects 0.000 claims abstract description 11
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052726 zirconium Inorganic materials 0.000 claims abstract description 9
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052735 hafnium Inorganic materials 0.000 claims abstract description 7
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims abstract description 7
- ZVWKZXLXHLZXLS-UHFFFAOYSA-N zirconium nitride Chemical compound [Zr]#N ZVWKZXLXHLZXLS-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 229910052749 magnesium Inorganic materials 0.000 claims description 2
- 239000011777 magnesium Substances 0.000 claims description 2
- 239000000654 additive Substances 0.000 claims 1
- 230000000996 additive effect Effects 0.000 claims 1
- 239000012212 insulator Substances 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 23
- 238000005530 etching Methods 0.000 abstract description 5
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052804 chromium Inorganic materials 0.000 abstract description 2
- 239000011651 chromium Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 3
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 1
- -1 hunium Chemical compound 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910021354 zirconium(IV) silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はアクティブマトリクス型液晶表示装置、イメー
ジセンサ等に用いられる薄膜トランジスタ（以下、ＴＰ
Ｔと略称する）に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to thin film transistors (hereinafter referred to as TP) used in active matrix liquid crystal display devices, image sensors, etc.
(abbreviated as T).
従来の技術
近年、低温プロセスや大面積化を特徴とするアモルファ
スシリコンＴＰＴを液晶表示装置、イメージセンサ−等
に利用する研究開発が活発である。BACKGROUND OF THE INVENTION In recent years, there has been active research and development into the use of amorphous silicon TPT, which is characterized by its low temperature process and large area, for liquid crystal display devices, image sensors, and the like.
以下図面を参照しながら従来のＴＰＴの一例について説
明する。第２図は従来のＴＰＴの断面図であり、１はガ
ラス等の絶縁性基板であり、この上にゲート電極２、ゲ
ート絶縁膜３、アモルファスシリコン半導体薄膜４、ｎ
＋アモルファスシリコン薄膜６、保護絶縁膜６、および
ソース・ドレイン電極７を形成する。An example of a conventional TPT will be described below with reference to the drawings. FIG. 2 is a cross-sectional view of a conventional TPT, in which 1 is an insulating substrate made of glass or the like, on which are formed a gate electrode 2, a gate insulating film 3, an amorphous silicon semiconductor thin film 4, and an amorphous silicon semiconductor thin film 4.
+Amorphous silicon thin film 6, protective insulating film 6, and source/drain electrodes 7 are formed.
以上のように構成されたＴＰＴについてその動作を以下
に説明する。ソース・ドレイン電極７の電極間に電圧を
印加したとき、ゲート電極２が零電位であれば半導体薄
膜４は通常高抵抗なのでソース・ドレイン電極７を流れ
る電流は少い。しかし、ゲート電圧を正または負に増加
させるとゲート絶縁膜３を介して半導体薄膜４と絶縁膜
３の界面付近にチャネルが誘起されるためソース・ドレ
イン電流が増加する。例えば、「日経エレクトロニクス
Ｊ １９８２年１２月２０日号、１０５〜１７９ページ
。The operation of the TPT configured as described above will be explained below. When a voltage is applied between the source and drain electrodes 7, if the gate electrode 2 is at zero potential, the semiconductor thin film 4 usually has a high resistance, so the current flowing through the source and drain electrodes 7 is small. However, when the gate voltage is increased to be positive or negative, a channel is induced near the interface between the semiconductor thin film 4 and the insulating film 3 via the gate insulating film 3, so that the source-drain current increases. For example, "Nikkei Electronics J, December 20, 1982 issue, pages 105-179.
発明が解決しようとする問題点
しかしながら上記のような構成では、ソース・ドレイン
電極として導電率の良いアルミニウム膜を用いた場合、
ｎ＋７モル７７２７９３７層との界面でアルミ・シリコ
ンの反応が比較的低温から生じるため安定な金属・半導
体界面は得られないという問題点を有していた。Problems to be Solved by the Invention However, in the above configuration, when an aluminum film with good conductivity is used as the source/drain electrode,
Since the reaction between aluminum and silicon occurs at a relatively low temperature at the interface with the n+7 mol 7727937 layer, there was a problem in that a stable metal/semiconductor interface could not be obtained.
本発明は上記問題点に鑑み、ソース・ドレイン電極とｎ
＋７モル７７２７９３７層との界面を安定化し、経時変
化が少く信頼性の高いＴＰＴを提供するものである。In view of the above problems, the present invention provides source/drain electrodes and
The interface with the +7 mol 7727937 layer is stabilized to provide a highly reliable TPT with little change over time.
問題点を解決するための手段
上記問題点を解決するために本発明のＴＰＴは、ｎ ア
モルファスシリコン層とソース・ドレイン電極との間に
相互拡散障壁層としてチタン、ジルコニウム、ハフニウ
ム、窒化チタン、窒化ジルコニウムのいずれかを用いる
という構成を備えたものである。Means for Solving the Problems In order to solve the above problems, the TPT of the present invention uses titanium, zirconium, hafnium, titanium nitride, or titanium nitride as an interdiffusion barrier layer between the n-amorphous silicon layer and the source/drain electrodes. It has a structure that uses either zirconium.
作 用
本発明は上記した構成によって、拡散障壁層として高融
点金属であるチタン、ジルコニウム、ハフニウム、およ
びその窒化物である窒化チタン。Function The present invention uses titanium, zirconium, and hafnium, which are high melting point metals, and titanium nitride, which is a nitride thereof, as a diffusion barrier layer.
窒化ジルコニウムのいずれかの薄膜を用いる。これらは
シリコンと反応してシリコン化合物（シリサイド）を形
成するがその温度はＴｉＳｉがｓｏｏ’ｃ。Use any thin film of zirconium nitride. These react with silicon to form a silicon compound (silicide), but the temperature is soo'c for TiSi.
ＺｒＳｉ２カフ００ ℃、 ＨｆＳｉが５５０−７０Ｃ
）Ｃである。ZrSi2 cuff 00℃, HfSi 550-70C
)C.
（ＶＬＳＩ Ｅｌｅｃｔｒｏｎｉｃｓ Ｖｏ１６．ｐ
３４６）。ＴＰＴは通常これらの温度よりずっと低い温
度におかれるので上記金属とｎ＋７モル７７２７９３７
層の界面は安定している。アモルファスシリコン中では
単結晶シリコンの場合に比べ物質の拡散速度が桁違いに
大きくなることが見い出されており、ソース・ドレイン
電極としてアルミニウム膜を用いた場合、比較的低温（
２００〜３ｏｏ℃）でも界面拡散が進行して、ＴＰＴの
電気的特性を劣化させるのはこのためである。本発明の
場合はより高い温度域まで界面は安定している。さらに
チタン。(VLSI Electronics Vol16.p
346). Since TPT is normally kept at temperatures much lower than these temperatures, the above metals and n+7 moles of 7727937
The layer interfaces are stable. It has been found that the diffusion rate of substances in amorphous silicon is an order of magnitude higher than in single crystal silicon, and when aluminum films are used as source and drain electrodes, the temperature is relatively low (
This is the reason why interfacial diffusion progresses even at temperatures of 200 to 300° C.) and deteriorates the electrical characteristics of TPT. In the case of the present invention, the interface is stable up to a higher temperature range. More titanium.
ジルコニウム、ハフニウムの仕事関数は各々４．３３ｅ
Ｖ 、 ４．０５ ｅＶ 、 ３．９ｅＶであり、アモ
ルファスシリコンとの仕事関数の違いが少いのでオーム
性接触が得られやすい。The work functions of zirconium and hafnium are each 4.33e.
V, 4.05 eV, and 3.9 eV, and since the difference in work function from amorphous silicon is small, ohmic contact is easily obtained.
実施例
以下本発明の一実施例のＴＰＴについて、図面を参照し
ながら説明する。EXAMPLE Hereinafter, a TPT according to an example of the present invention will be explained with reference to the drawings.
第１図は本発明の実施例におけるＴＰＴの断面図を示す
ものである。第１図において、ｎ＋７モル７７７７９７
７層５とソース・ドレイン電極７との間にチタン、ジル
コニウム、ハフニウム、窒化チタン、窒化ジルコニウム
のいずれかよりなる拡散障壁層８が存在する。その他は
第２図の従来例と同一であシ、同一部分は第２図と同一
符号を付してその説明を省略する。FIG. 1 shows a sectional view of a TPT in an embodiment of the present invention. In Figure 1, n+7 moles 777797
A diffusion barrier layer 8 made of titanium, zirconium, hafnium, titanium nitride, or zirconium nitride is present between layer 5 and source/drain electrode 7 . The rest is the same as the conventional example shown in FIG. 2, and the same parts are given the same reference numerals as in FIG. 2 and their explanation will be omitted.
このようなＴＰＴは以下のようにして製造される。まず
、ガラスなどの絶縁性基板１上にクロムなどの膜を蒸着
またはスパッタリングによシ形成し、所定形状にフォト
リングラフ・エツチング加工を施し、ゲート電極２とす
る。この上にプラズマＣＶＤなどにより、シリコン窒化
膜、アモルファスシリコン膜、シリコン窒化膜の順で３
層形成しフォトリングラフ・エツチング加工を行い、所
定の形状にし、各々ゲート絶縁膜３．アモルファスシリ
コン半導体膜４．保護絶縁膜６とする。保護絶縁膜６に
フォトリングラフ・エツチング加工により所定のコンタ
クト窓を開け、ｎ＋アモルファスシリコン薄膜をプラズ
マＣＶＤ法で形成し、チタン薄膜を蒸着またはスパッタ
リングによシ形成し、アルミニウム薄膜をさらにその上
に蒸着またはスパッタリングによシ形成する。この後フ
ォトリングラフ・エツチング加工により所定の形状にし
、各々ｎ＋７モル７７２７９３７層６．拡散障壁層８．
ソース・ドレイン電極７とする。Such TPT is manufactured as follows. First, a film of chromium or the like is formed on an insulating substrate 1 of glass or the like by vapor deposition or sputtering, and photolithographic etching is applied to a predetermined shape to form the gate electrode 2. On top of this, a silicon nitride film, an amorphous silicon film, and a silicon nitride film are deposited in the order of 3 using plasma CVD or the like.
The layers are formed and subjected to photolithographic etching processing to form a predetermined shape, and each gate insulating film 3. Amorphous silicon semiconductor film 4. A protective insulating film 6 is used. A predetermined contact window is opened in the protective insulating film 6 by photolithographic etching, an n+ amorphous silicon thin film is formed by plasma CVD, a titanium thin film is formed by vapor deposition or sputtering, and an aluminum thin film is further formed thereon. Formed by vapor deposition or sputtering. After that, it is formed into a predetermined shape by photoringraph etching, and each layer is formed into a layer of n+7 moles of 7727937 layers.6. Diffusion barrier layer 8.
This is assumed to be a source/drain electrode 7.
以上のように本実施例によれば、ｎ＋７モル７７７７９
７７層５とソース・ドレイン電極７０間に拡散障壁層８
が存在しているため安定な金属・半導体界面が得られ、
ＴＰＴの信頼性を向上させている。As described above, according to this example, n+7 moles 77779
A diffusion barrier layer 8 is provided between the 77 layer 5 and the source/drain electrode 70.
A stable metal-semiconductor interface is obtained due to the presence of
Improves the reliability of TPT.
上記の実施例では拡散障壁層８としてチタン薄膜を用い
、ソース・ドレイン電極７としてアルミニウム薄膜を用
いたが、チタンのかわりに、ジルコニウム、ハフニウム
、窒化チタン、窒化ジルコニウムのいずれかを用いても
上記実施例と同様の効果が得られる。さらに、アルミニ
ウム薄膜のかワリに、シリコン、銅、マグネシウム、チ
タンのいずれかを少量添加したアルミニウム合金薄膜を
用いてもよい。In the above embodiment, a titanium thin film was used as the diffusion barrier layer 8 and an aluminum thin film was used as the source/drain electrode 7, but instead of titanium, any of zirconium, hafnium, titanium nitride, or zirconium nitride may be used. Effects similar to those of the embodiment can be obtained. Furthermore, an aluminum alloy thin film in which a small amount of silicon, copper, magnesium, or titanium is added to the aluminum thin film may be used.
発明の効果
以上のように本発明はｎ アモルファスシリコン層とソ
ース・ドレイン電極の間に拡散障壁層とシテ、チタン、
ジルコニウム、・・フニウム、窒化チタン、窒化ジルコ
ニウムのいずれかの薄膜を介在させることにより安定で
信頼性の高い金属・半導体界面が得られＴＰＴを液晶表
示装置やイメージセンサ−に応用する場合に有利となる
。Effects of the Invention As described above, the present invention provides a diffusion barrier layer between the amorphous silicon layer and the source/drain electrodes, titanium, titanium,
By interposing a thin film of zirconium, hunium, titanium nitride, or zirconium nitride, a stable and highly reliable metal-semiconductor interface can be obtained, which is advantageous when applying TPT to liquid crystal display devices and image sensors. Become.
第１図は本発明の一つの実施例における薄膜トランジス
タの断面図、第２図は従来の薄膜トランジスタの断面図
である。
１・・・・・・絶縁性基板、２・・・・・・ゲート電極
、３・・・・・・ケート絶縁膜、４・・・・・・アモル
ファスシリコン半導体膜、５・・・・・・ｎ＋アモルフ
ァスシリコン薄膜、６・・・・・・保護絶縁膜、７・・
・・・・ソース・ドレイ／電極、８・・・・・・拡散障
壁層。FIG. 1 is a sectional view of a thin film transistor according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional thin film transistor. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Gate electrode, 3... Kate insulating film, 4... Amorphous silicon semiconductor film, 5...・n+ amorphous silicon thin film, 6...protective insulating film, 7...
. . . Source/dray/electrode, 8 . . . Diffusion barrier layer.
Claims (2)
リコン半導体層ｎ＾＋アモルファスシリコン層、ソース
、ドレイン電極を備え、前記ｎ＾＋アモルファスシリコ
ン層とソース・ドレイン電極との間に、相互拡散障壁層
としてチタン、ジルコニウム、ハフニウム、窒化チタン
、窒化ジルコニウムのいずれかを用いることを特徴とす
る薄膜トランジスタ。(1) At least a gate electrode, an insulator layer, an amorphous silicon semiconductor layer n^+ amorphous silicon layer, a source, and a drain electrode, and a mutual diffusion barrier between the n^+ amorphous silicon layer and the source/drain electrode. A thin film transistor characterized in that a layer is made of titanium, zirconium, hafnium, titanium nitride, or zirconium nitride.
しくは、アルミニウムに添加元素としてシリコン、銅、
マグネシウム、チタンのいずれかを加えたアルミニウム
合金薄膜を用いる特許請求の範囲第１項記載の薄膜トラ
ンジスタ。(2) Use an aluminum thin film as source/drain electrodes, or use silicon, copper, etc. as additive elements to aluminum.
The thin film transistor according to claim 1, which uses an aluminum alloy thin film to which either magnesium or titanium is added.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2383585A JPS61183971A (en) | 1985-02-08 | 1985-02-08 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2383585A JPS61183971A (en) | 1985-02-08 | 1985-02-08 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61183971A true JPS61183971A (en) | 1986-08-16 |
Family
ID=12121445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2383585A Pending JPS61183971A (en) | 1985-02-08 | 1985-02-08 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61183971A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0191467A (en) * | 1987-10-02 | 1989-04-11 | Asahi Glass Co Ltd | Thin film transistor substrate |
| JPH0548106A (en) * | 1991-02-20 | 1993-02-26 | Alps Electric Co Ltd | Thin film transistor and its manufacture |
| JPH08186264A (en) * | 1994-12-28 | 1996-07-16 | Seiko Epson Corp | Thin-film transistor and its production |
| US5536951A (en) * | 1993-06-24 | 1996-07-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having thin film transistor with diffusion preventing layer |
| US5808315A (en) * | 1992-07-21 | 1998-09-15 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor having transparent conductive film |
| JP2000216403A (en) * | 1994-07-30 | 2000-08-04 | Semiconductor Energy Lab Co Ltd | Active matrix circuit |
| US6201281B1 (en) | 1993-07-07 | 2001-03-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for producing the same |
| US6455875B2 (en) | 1992-10-09 | 2002-09-24 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor having enhanced field mobility |
| US6608353B2 (en) | 1992-12-09 | 2003-08-19 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor having pixel electrode connected to a laminate structure |
| US6624477B1 (en) | 1992-10-09 | 2003-09-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| JP2007204332A (en) * | 2006-02-03 | 2007-08-16 | Sumco Corp | Device and method for manufacturing single crystal |
| US8147613B2 (en) | 2002-11-12 | 2012-04-03 | Memc Electronic Materials, Inc. | Crystal puller and method for growing a monocrystalline ingot |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60224270A (en) * | 1984-04-20 | 1985-11-08 | Fujitsu Ltd | Thin film amorphous silicon transistor |
-
1985
- 1985-02-08 JP JP2383585A patent/JPS61183971A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60224270A (en) * | 1984-04-20 | 1985-11-08 | Fujitsu Ltd | Thin film amorphous silicon transistor |
Cited By (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0191467A (en) * | 1987-10-02 | 1989-04-11 | Asahi Glass Co Ltd | Thin film transistor substrate |
| JPH0548106A (en) * | 1991-02-20 | 1993-02-26 | Alps Electric Co Ltd | Thin film transistor and its manufacture |
| US5808315A (en) * | 1992-07-21 | 1998-09-15 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor having transparent conductive film |
| US6624477B1 (en) | 1992-10-09 | 2003-09-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US8017506B2 (en) | 1992-10-09 | 2011-09-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US7723788B2 (en) | 1992-10-09 | 2010-05-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US7602020B2 (en) | 1992-10-09 | 2009-10-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US6455875B2 (en) | 1992-10-09 | 2002-09-24 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor having enhanced field mobility |
| US7109108B2 (en) | 1992-10-09 | 2006-09-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device having metal silicide |
| US6790749B2 (en) | 1992-10-09 | 2004-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| US7547916B2 (en) | 1992-12-09 | 2009-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit |
| US7897972B2 (en) | 1992-12-09 | 2011-03-01 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit |
| US6608353B2 (en) | 1992-12-09 | 2003-08-19 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor having pixel electrode connected to a laminate structure |
| US7045399B2 (en) | 1992-12-09 | 2006-05-16 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit |
| US7061016B2 (en) | 1992-12-09 | 2006-06-13 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit |
| US7105898B2 (en) | 1992-12-09 | 2006-09-12 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit |
| US8294152B2 (en) | 1992-12-09 | 2012-10-23 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit including pixel electrode comprising conductive film |
| US5536951A (en) * | 1993-06-24 | 1996-07-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having thin film transistor with diffusion preventing layer |
| US6201281B1 (en) | 1993-07-07 | 2001-03-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for producing the same |
| US6784453B2 (en) | 1993-07-07 | 2004-08-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for producing the same |
| US6569719B2 (en) | 1993-07-07 | 2003-05-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for producing the same |
| JP2000216403A (en) * | 1994-07-30 | 2000-08-04 | Semiconductor Energy Lab Co Ltd | Active matrix circuit |
| JPH08186264A (en) * | 1994-12-28 | 1996-07-16 | Seiko Epson Corp | Thin-film transistor and its production |
| US8147613B2 (en) | 2002-11-12 | 2012-04-03 | Memc Electronic Materials, Inc. | Crystal puller and method for growing a monocrystalline ingot |
| JP2007204332A (en) * | 2006-02-03 | 2007-08-16 | Sumco Corp | Device and method for manufacturing single crystal |
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