JPS6118338B2 - - Google Patents
Info
- Publication number
- JPS6118338B2 JPS6118338B2 JP15259080A JP15259080A JPS6118338B2 JP S6118338 B2 JPS6118338 B2 JP S6118338B2 JP 15259080 A JP15259080 A JP 15259080A JP 15259080 A JP15259080 A JP 15259080A JP S6118338 B2 JPS6118338 B2 JP S6118338B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- temperature
- integrated circuit
- semiconductor wafer
- probe card
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000523 sample Substances 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000001514 detection method Methods 0.000 claims description 6
- 235000012431 wafers Nutrition 0.000 description 26
- 238000001816 cooling Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000009529 body temperature measurement Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07342—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
Description
【発明の詳細な説明】
この発明はプローブカードに係り、特に多数個
の集積回路素子を有する半導体ウエハ（以下単に
ウエハという）の各集積回路素子の電気的特性を
検査するために、ウエハの表面温度も検出するこ
とが可能なプローブカードに関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a probe card, in particular a probe card for testing the electrical characteristics of each integrated circuit element of a semiconductor wafer (hereinafter simply referred to as a wafer) having a large number of integrated circuit elements. The present invention relates to a probe card that can also detect temperature.
前記のウエハを任意の温度に加熱あるいは冷却
し、集積回路素子の電気的特性を測定する場合に
は、そのウエハ上の集積回路素子の温度を知る必
要がある。 When heating or cooling the wafer to a desired temperature and measuring the electrical characteristics of the integrated circuit elements, it is necessary to know the temperature of the integrated circuit elements on the wafer.
従来は、ウエハ表面の温度を知る手段として、
熱電対を用いて、熱電対電極をウエハ上に手操作
により押し当て温度を測定していた。この方法に
よると、熱電対電極の形状がウエハに対して比較
的に大きいため、ウエハ上の各集積回路素子ごと
の温度測定は困難であり、また手操作により熱電
対電極をウエハ表面に押し当てるので一定の圧力
を加えることが容易でなく、温度測定の条件に再
現性を得られない。また、ウエハ上の集積回路素
子を損傷させる危険性が多分にあつた。 Conventionally, as a means of determining the temperature of the wafer surface,
Using a thermocouple, the temperature was measured by manually pressing the thermocouple electrode onto the wafer. According to this method, since the shape of the thermocouple electrode is relatively large compared to the wafer, it is difficult to measure the temperature of each integrated circuit element on the wafer, and the thermocouple electrode is manually pressed against the wafer surface. Therefore, it is not easy to apply a constant pressure, and it is not possible to obtain reproducibility in temperature measurement conditions. Additionally, there was a significant risk of damaging integrated circuit elements on the wafer.
本発明の目的は、任意の温度に加熱あるいは冷
却されたウエハ上の集積回路素子の電気的特性を
測定する場合に、ウエハ上の集積回路素子を損傷
させることなく、ウエハ表面の温度を再現性良く
測定し、得られた温度データを集積回路素子の電
気的特性の検査に取り入れようとするものであ
る。 An object of the present invention is to reproducibly measure the temperature of the wafer surface without damaging the integrated circuit elements on the wafer when measuring the electrical characteristics of integrated circuit elements on a wafer heated or cooled to an arbitrary temperature. The purpose is to take accurate measurements and incorporate the obtained temperature data into testing the electrical characteristics of integrated circuit devices.
以下、図面をもつて説明する。 This will be explained below with reference to the drawings.
第１図は実施例の一例であつて、５のウエハチ
ヤツクに吸着された４のウエハ、および１のプロ
ーブカードに設けられた２のプローブと３の温度
検出端の断面である。２のプローブと３の温度検
出端の先端は同一平面内に構成され、４のウエハ
との接触は同一圧力をもつて行なわれる。また、
３の温度検出端はウエハ上の各集積回路素子を損
傷しないように各集積回路素子以外のウエハ表面
に接触し、ウエハ表面の温度を電気的要素の変化
により検出するもので、外部測定器に接続するこ
とにより温度を感知することができる。 FIG. 1 shows an example of the embodiment, and is a cross section of four wafers adsorbed to a five wafer chuck, two probes provided on one probe card, and a temperature detection end 3. The tip of the probe No. 2 and the temperature sensing end No. 3 are arranged in the same plane, and the contact with the wafer No. 4 is made with the same pressure. Also,
The temperature detection end 3 contacts the wafer surface other than each integrated circuit element so as not to damage each integrated circuit element on the wafer, and detects the temperature of the wafer surface by changes in electrical elements. By connecting it, you can sense the temperature.
一般に特性検査はウエハ上の有効集積回路素子
の全てに対して実施されるので、同時に、温度測
定も有効集積回路素子の全てについて行うことが
できる。従つて集積回路素子の特性検査に温度の
条件を加味することも可能であり、また、ウエハ
の加熱あるいは冷却機構に温度データを掃還させ
ることにより、ウエハ温度の自動制御も可能にな
る。 Since characteristic testing is generally performed on all active integrated circuit elements on a wafer, temperature measurements can also be performed on all active integrated circuit elements at the same time. Therefore, it is possible to take temperature conditions into consideration when testing the characteristics of integrated circuit elements, and by having the wafer heating or cooling mechanism sweep the temperature data, it is also possible to automatically control the wafer temperature.
以上のように本発明によれば、ウエハを任意の
温度に加熱あるいは冷却させて集積回路素子の電
気的特性を検査する場合に、ウエハ表面の温度を
精度よく測定できるため、温度条件を含めた集積
回路素子の電気的特性を検査できる利点がある。 As described above, according to the present invention, when testing the electrical characteristics of an integrated circuit element by heating or cooling a wafer to an arbitrary temperature, the temperature on the wafer surface can be measured with high accuracy. There is an advantage that the electrical characteristics of integrated circuit elements can be tested.
第１図は本発明の一実施例の概略を示す断面図
であり、１……プローブカード、２……プロー
ブ、３……温度検出端、４……ウエハ、５……ウ
エハチヤツクを示す。
FIG. 1 is a sectional view schematically showing an embodiment of the present invention, and shows 1...probe card, 2...probe, 3...temperature detection end, 4...wafer, and 5...wafer chuck.
Claims (1)
うためのプローブカードにおいて、複数のプロー
ブの先端と同一平面内にその先端が位置するごと
く前記半導体ウエハの表面温度測定のための温度
検出端が該プローブカードに設けられ、これによ
り該複数のプローブと前記半導体ウエハとが接触
するときに、該複数のプローブと同一の圧力をも
つて該温度検出端が該半導体ウエハに接触し、か
つ該温度検出端は各半導体素子が設けられていな
い該半導体ウエハの表面個所に接触するように位
置していることを特徴とするプローブカード。1. In a probe card for testing each semiconductor element of a semiconductor wafer, a temperature detection end for measuring the surface temperature of the semiconductor wafer is arranged so that the tip thereof is located in the same plane as the tips of a plurality of probes. provided in the card so that when the plurality of probes and the semiconductor wafer come into contact, the temperature detection end contacts the semiconductor wafer with the same pressure as the plurality of probes, and the temperature detection end contacts the semiconductor wafer with the same pressure as the plurality of probes; A probe card characterized in that the probe card is positioned so as to come into contact with a surface portion of the semiconductor wafer where each semiconductor element is not provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15259080A JPS5776852A (en) | 1980-10-30 | 1980-10-30 | Card for probe |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15259080A JPS5776852A (en) | 1980-10-30 | 1980-10-30 | Card for probe |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5776852A JPS5776852A (en) | 1982-05-14 |
| JPS6118338B2 true JPS6118338B2 (en) | 1986-05-12 |
Family
ID=15543765
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15259080A Granted JPS5776852A (en) | 1980-10-30 | 1980-10-30 | Card for probe |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5776852A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62154636A (en) * | 1985-12-27 | 1987-07-09 | Hitachi Electronics Eng Co Ltd | Cvd thin film forming apparatus |
| JP5008877B2 (en) * | 2006-02-21 | 2012-08-22 | 株式会社リコー | IC test method |
-
1980
- 1980-10-30 JP JP15259080A patent/JPS5776852A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5776852A (en) | 1982-05-14 |
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