JPS61166078A - Floating-gate type nonvolatile memory element - Google Patents

Floating-gate type nonvolatile memory element

Info

Publication number
JPS61166078A
JPS61166078A JP60006470A JP647085A JPS61166078A JP S61166078 A JPS61166078 A JP S61166078A JP 60006470 A JP60006470 A JP 60006470A JP 647085 A JP647085 A JP 647085A JP S61166078 A JPS61166078 A JP S61166078A
Authority
JP
Japan
Prior art keywords
floating gate
floating
memory element
gate
gate type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60006470A
Other languages
Japanese (ja)
Inventor
Rie Ariga
有賀　理恵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP60006470A priority Critical patent/JPS61166078A/en
Publication of JPS61166078A publication Critical patent/JPS61166078A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7885—Hot carrier injection from the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To not only project ultraviolet rays but also enable an erasing electrically on the erasing by combining a diode with a floating-gate. CONSTITUTION:A diode is combined with a floating-gate. Consequently, when a diode 7 for the floating-gate section is biassed in the opposite direction, only a memory element section is effective in the floating-gate 4, and charges can be stored temporarily as a floating-gate type nonvolatile memory element. When the floating-gate 4 section is biassed in the forward direction, on the contrary, charges stored in the memory element section can be discharged.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、電気的に、あるいは紫外線により消去可能な
フローティング・ゲート型不揮発性メモリー素子の構造
に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the structure of a floating gate non-volatile memory element that is electrically or ultraviolet erasable.

従来の技術 第２図は従来のフローティング・ゲート型不揮発性メモ
リー素子の構造を示すものであり、１はソース、２はド
レイン、３は第１の絶縁膜、４はフローティング・ゲー
ト、６は第２の絶縁膜、６はコントロール・ゲートであ
る。BACKGROUND ART FIG. 2 shows the structure of a conventional floating gate type non-volatile memory device, in which 1 is a source, 2 is a drain, 3 is a first insulating film, 4 is a floating gate, and 6 is a third insulating film. 2 is an insulating film, and 6 is a control gate.

発明が解決しようとする問題点 以上のように構成されたフローティング・ゲート型メモ
リー素子では、フローティング・ゲート部分に蓄積され
た電子を逃がすため、紫外線を照射する。この方法では
、メモリー素子の内容を書きかえるため、専用の紫外線
の照射装置を必要とす、る。また、照射した紫外線をメ
モリー素子表面まで透過する特殊なパッケージを必要と
する。Problems to be Solved by the Invention In the floating gate type memory device configured as described above, ultraviolet rays are irradiated to release electrons accumulated in the floating gate portion. This method requires a dedicated ultraviolet irradiation device to rewrite the contents of the memory element. Additionally, a special package is required that allows the irradiated ultraviolet rays to pass through to the surface of the memory element.

本発明は上記従来の問題点を解消するもので、紫外線を
必要とせずに、電気的にメモリー素子の消去を行なうこ
とを目的とする。The present invention solves the above-mentioned conventional problems and aims to electrically erase a memory element without requiring ultraviolet light.

問題点を解決するための手段 本発明は、−導電型半導体基板の表面に、所定の間隔を
設けて逆導電型不純物を導入して形成したソース・ドレ
イン領域と、そのソース・ドレイン両領域の間に第１の
絶縁膜を介して設けたフローティング・ゲートの上に第
２の絶縁膜を介して設けたコントロール・ゲートからな
るフローティング・ゲート型不揮発性メモリー素子に於
いて、前記フローティング・ゲートにダイオードを結合
させたものである。Means for Solving the Problems The present invention provides - source/drain regions formed by introducing opposite conductivity type impurities at predetermined intervals into the surface of a conductivity type semiconductor substrate; In a floating gate type non-volatile memory element comprising a control gate provided via a second insulating film on a floating gate provided via a first insulating film in between, the floating gate is It is a combination of diodes.

作　　用 この構成によシ、フローティング・ゲート部分にダイオ
ード特性を持たせ、これを逆方向にバイアスすることで
、フローティング・ゲート型不揮発性メモリー素子とし
ての特性をもたせ、順方向のバイアスを加えることで、
蓄積された電荷を放電して、消去を行なうことができる
。Function: By giving the floating gate part diode characteristics and biasing it in the reverse direction, this structure gives it the characteristics of a floating gate type non-volatile memory element, and by applying a forward bias. in,
Erasing can be performed by discharging the accumulated charge.

実施例 第１図は、本発明の一実施例における、フローティング
・ゲート型不揮発性メモリー素子の構造を示す等価概要
図である。１は、ソース、２はドレイン、３は第１の絶
縁膜、４はフローティング・ゲート、６は第２の絶縁膜
、６はコントロール・ゲート、７はダイオードである。Embodiment FIG. 1 is an equivalent schematic diagram showing the structure of a floating gate type nonvolatile memory element in an embodiment of the present invention. 1 is a source, 2 is a drain, 3 is a first insulating film, 4 is a floating gate, 6 is a second insulating film, 6 is a control gate, and 7 is a diode.

第１図で、メモリー素子の構造要部は、第４図と全く同
様になるが、これを平面的に９ｏ度回転させた場合の断
面図が第２図である。In FIG. 1, the main structural parts of the memory element are exactly the same as those in FIG. 4, but FIG. 2 is a cross-sectional view when this is rotated 90 degrees in plan view.

８は、ＬＯＧＯ８部分、２は、トランジスタ・チャンネ
ル、３は第１の絶縁膜、４は、フローティング・ゲート
であり、７はこのフローティング・ゲートを構成してい
るＰ型またはＮ型のポリシリコンにＮ型およびＰ型の不
純物を導入した部分、６は第２の絶縁膜、６はコントロ
ール・ゲートである。8 is the LOGO8 portion, 2 is the transistor channel, 3 is the first insulating film, 4 is the floating gate, and 7 is the P-type or N-type polysilicon that constitutes this floating gate. A portion into which N-type and P-type impurities are introduced, 6 is a second insulating film, and 6 is a control gate.

第３図に、本実施例におけるフローティング・ゲート型
メモリー素子の斜視断面図を示す。FIG. 3 shows a perspective cross-sectional view of the floating gate type memory element in this example.

以上のように構成されているフローティング・ゲート型
メモリー素子で、第３図の中の符号４゜７の部分で構成
されているフローティング・ゲート部のダイオードを逆
方向にバイアスと、フローティング・ゲートは、メモリ
ー素子部分のみが有効となって、フローティング・ゲー
ト型不揮発性メモリー素子として一時的に電荷を蓄積し
ておくことができる。反対に、このフローティング・ゲ
ート部分に、順方向のバイアスを行なうと、メモリー素
子部分に蓄積された電荷を放電することができる。In the floating gate type memory device constructed as described above, if the diode of the floating gate part, which is constructed by the section 4°7 in Fig. 3, is biased in the opposite direction, the floating gate is , only the memory element portion becomes effective, allowing charge to be temporarily stored as a floating gate type nonvolatile memory element. Conversely, if the floating gate portion is forward biased, the charges accumulated in the memory element portion can be discharged.

発明の効果 本発明によると、フローティング・ゲート型メモリー素
子において、消去時に紫外線の照射のみでなく電気的に
も消去を可能にするという効果を得るものである。Effects of the Invention According to the present invention, in a floating gate type memory element, erasing can be performed not only by ultraviolet irradiation but also electrically.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明のフローティング・ゲート型メモリー素
子の構造断面図、第２図、第３図は本発明のフローティ
ング・ゲート型メモリー素子の断面図および斜視断面図
、第４図は、従来例のフローティング・ゲート型メモリ
ー素子の構造断面図である。 １・・・・・・ソース、２・・・・・・ドレイン、３．
６・・・・・・酸化膜、４・・・・・・ポリシリコンフ
ローティング・ゲート、６・・・・・・ポリシリコンコ
ントロール−ゲート、７・・・・・・ポリシリコン逆導
電型部分。 ＆ｆＩＩ！ＩFIG. 1 is a structural sectional view of a floating gate type memory device of the present invention, FIGS. 2 and 3 are sectional views and perspective sectional views of a floating gate type memory device of the present invention, and FIG. 4 is a conventional example. FIG. 2 is a cross-sectional view of the structure of a floating gate type memory device. 1...source, 2...drain, 3.
6...Oxide film, 4...Polysilicon floating gate, 6...Polysilicon control gate, 7...Polysilicon reverse conductivity type portion. &fII! I

Claims (1)

【特許請求の範囲】[Claims] 導電型半導体基板と、その基板表面に、所定の間隔を設
けて逆導電型不純物を導入して形成した逆導電型のソー
ス・ドレイン領域と、そのソース・ドレイン両領域の間
に第一の絶縁膜を介して設けたフローティング・ゲート
の上に第二の絶縁膜を介して設けたコントロール・ゲー
トとから成るフローティング・ゲート型不揮発性メモリ
ー素子に於いて、前記フローティング・ゲートにダイオ
ードを結合したことを特徴としたフローティング・ゲー
ト型不揮発性メモリー素子。A conductive type semiconductor substrate, opposite conductive type source/drain regions formed by introducing opposite conductive type impurities into the substrate surface at a predetermined interval, and a first insulation between the source/drain regions. In a floating gate type nonvolatile memory element consisting of a floating gate provided through a film and a control gate provided through a second insulating film, a diode is coupled to the floating gate. A floating gate non-volatile memory device featuring
JP60006470A 1985-01-17 1985-01-17 Floating-gate type nonvolatile memory element Pending JPS61166078A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60006470A JPS61166078A (en) 1985-01-17 1985-01-17 Floating-gate type nonvolatile memory element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60006470A JPS61166078A (en) 1985-01-17 1985-01-17 Floating-gate type nonvolatile memory element

Publications (1)

Publication Number Publication Date
JPS61166078A true JPS61166078A (en) 1986-07-26

Family

ID=11639339

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60006470A Pending JPS61166078A (en) 1985-01-17 1985-01-17 Floating-gate type nonvolatile memory element

Country Status (1)

Country Link
JP (1) JPS61166078A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02282996A (en) * 1989-03-23 1990-11-20 Sgs Thomson Microelectron Srl Reference cell for reading eeprom memory device
US6888200B2 (en) * 2002-08-30 2005-05-03 Micron Technology Inc. One transistor SOI non-volatile random access memory cell
US6903969B2 (en) * 2002-08-30 2005-06-07 Micron Technology Inc. One-device non-volatile random access memory cell
US6917078B2 (en) 2002-08-30 2005-07-12 Micron Technology Inc. One transistor SOI non-volatile random access memory cell
US7145186B2 (en) 2004-08-24 2006-12-05 Micron Technology, Inc. Memory cell with trenched gated thyristor
US7968402B2 (en) 2003-07-02 2011-06-28 Micron Technology, Inc. Method for forming a high-performance one-transistor memory cell
JP2012028756A (en) * 2010-06-25 2012-02-09 Semiconductor Energy Lab Co Ltd Semiconductor device and driving method of semiconductor device

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02282996A (en) * 1989-03-23 1990-11-20 Sgs Thomson Microelectron Srl Reference cell for reading eeprom memory device
US7440317B2 (en) 2002-08-30 2008-10-21 Micron Technology, Inc. One transistor SOI non-volatile random access memory cell
US6888200B2 (en) * 2002-08-30 2005-05-03 Micron Technology Inc. One transistor SOI non-volatile random access memory cell
US7485513B2 (en) 2002-08-30 2009-02-03 Micron Technology, Inc. One-device non-volatile random access memory cell
US7130216B2 (en) 2002-08-30 2006-10-31 Micron Technology, Inc. One-device non-volatile random access memory cell
US7566601B2 (en) 2002-08-30 2009-07-28 Micron Technology, Inc. Method of making a one transistor SOI non-volatile random access memory cell
US7184312B2 (en) 2002-08-30 2007-02-27 Micron Technology, Inc. One transistor SOI non-volatile random access memory cell
US7339830B2 (en) 2002-08-30 2008-03-04 Micron Technology, Inc. One transistor SOI non-volatile random access memory cell
US6917078B2 (en) 2002-08-30 2005-07-12 Micron Technology Inc. One transistor SOI non-volatile random access memory cell
US6903969B2 (en) * 2002-08-30 2005-06-07 Micron Technology Inc. One-device non-volatile random access memory cell
US7968402B2 (en) 2003-07-02 2011-06-28 Micron Technology, Inc. Method for forming a high-performance one-transistor memory cell
US7145186B2 (en) 2004-08-24 2006-12-05 Micron Technology, Inc. Memory cell with trenched gated thyristor
JP2012028756A (en) * 2010-06-25 2012-02-09 Semiconductor Energy Lab Co Ltd Semiconductor device and driving method of semiconductor device
JP2016026393A (en) * 2010-06-25 2016-02-12 株式会社半導体エネルギー研究所 Memory cell and driving method of the same
US9583576B2 (en) 2010-06-25 2017-02-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for driving the same
US9633722B2 (en) 2010-06-25 2017-04-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for driving the same
US10726913B2 (en) 2010-06-25 2020-07-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for driving the same
US11551751B2 (en) 2010-06-25 2023-01-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for driving the same

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