JPS6116563A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6116563A JPS6116563A JP13832184A JP13832184A JPS6116563A JP S6116563 A JPS6116563 A JP S6116563A JP 13832184 A JP13832184 A JP 13832184A JP 13832184 A JP13832184 A JP 13832184A JP S6116563 A JPS6116563 A JP S6116563A
- Authority
- JP
- Japan
- Prior art keywords
- region
- diffusion
- wiring material
- contact
- contact region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 abstract description 3
- 239000011229 interlayer Substances 0.000 abstract description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract 1
- 230000005496 eutectics Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/8605—Resistors with PN junctions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、拡散抵抗領域の破壊による入力リーーり電流
を防ぐ半導体装置に関するものである０ 秀従来
例の構成とその問題点
絶縁ゲート型電界効果ｌ・ランジスタのゲート型
１極はゲート下のシリコン酸化膜によってトランジ
Ｏスタのンース、ドレインから完全に絶縁されている
。このゲート電極に高入力電圧゛が印加されると
橿ゲート酸化膜は破壊されてしまう。それゆえ、高入力
電圧によるゲート電極部の破壊を防ぐため、呆護素子が
しばしば用いられ、その保護素子に流りるピーク電流を
制限するために入力ボンディング・パッドと保護素子と
の間に直列に抵抗が挿入される。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device that prevents input leakage current due to destruction of a diffused resistance region.・Ransistor gate type
One pole is transitioned by the silicon oxide film under the gate.
It is completely insulated from the source and drain of the OS. When a high input voltage is applied to this gate electrode,
The gate oxide film is destroyed. Therefore, to prevent damage to the gate electrode due to high input voltage, a protection device is often used, and a protection device is often used in series between the input bonding pad and the protection device to limit the peak current flowing through the protection device. A resistor is inserted.
以下に従来のこの抵抗の構造について説明する。The structure of this conventional resistor will be explained below.
第１図は、従来の半導体装置の構造を示す断面口である
。Ｐ型巣結晶シリコン基板１上に、ヒ素と拡散して拡散
抵抗領域４を形成する。この上に階間絶縁膜６を成長さ
せ、この絶縁膜を選択的にエツチングすることによりコ
ンタクト窓６をあけ乙。この上に金属の配線材γを形成
し、一方を入勾ボンディング・パッドに、一方を、内部
回路に接売する。FIG. 1 is a cross-sectional view showing the structure of a conventional semiconductor device. A diffused resistance region 4 is formed on a P-type nested crystal silicon substrate 1 by diffusing arsenic. An interstory insulating film 6 is grown on this, and a contact window 6 is opened by selectively etching this insulating film. A metal wiring material γ is formed on this, and one side is sold as an inclined bonding pad and the other side is sold as an internal circuit.
しかしながら、上記のような構成では、拡散低元領域の
基板方向への深さが０．３μｍ以下の場合では、入力に
高電圧が印加されると、入力ボンディング・パッドに接
続されている金属の配線材と広敷抵抗領域とのコンタク
ト領域において、拡散抵抗領域が破壊されてしまう。拡
散抵抗領域が破壊されてしまうと、入力ボンディング・
パッドと基板とが電気的に接続されてしまい、よって入
力リーク電流が流れてしまう。従来の構造では上記のよ
うな問題点を有していた。However, in the above configuration, if the depth of the diffused low element region in the substrate direction is 0.3 μm or less, when a high voltage is applied to the input, the metal connected to the input bonding pad will be damaged. The diffused resistance region is destroyed in the contact region between the wiring material and the wide-spread resistance region. If the diffused resistor area is destroyed, the input bonding
The pad and the board are electrically connected, resulting in an input leakage current. The conventional structure had the above-mentioned problems.
発明の目的
本発明は、上記従来の問題点を解消するもので拡散抵抗
領域がコンタクト領域において高入力電圧のために破壊
されてしまうことによって、金属配線材と基板とが電気
的に接続され、入力リーク電流が流れる、ということを
防止することができる半導体装置を提供するものである
。OBJECTS OF THE INVENTION The present invention solves the above-mentioned problems of the conventional art.The metal wiring material and the substrate are electrically connected because the diffused resistance region is destroyed due to high input voltage in the contact region. The present invention provides a semiconductor device that can prevent input leakage current from flowing.
発明の構成
本発明は、−導電形の半導体基板上に不純物拡散により
形成された、基板と導電型を異にする拡散抵抗領域にお
いて、金属の配線材との一方のコンタクト領域下に、前
記拡散抵抗領域の不純物濃度よりうすく、かつ、拡散の
深さが深い基板と導電型を異にする拡散領域を、前記コ
ンタクト領域を包括するように形成しである半導体装置
である。Structure of the Invention The present invention provides a diffusion resistance region having a conductivity type different from that of the substrate, which is formed by impurity diffusion on a conductivity type semiconductor substrate, and the diffusion resistance region is formed under one contact region with a metal wiring material. In the semiconductor device, a diffusion region having a conductivity type different from that of the substrate and having an impurity concentration lower than that of the resistance region and having a deeper diffusion depth is formed so as to surround the contact region.
この構造によれば、入力に高電圧が印加され、入力ボン
ディング・パッドに接続された金属配線材と前記拡散抵
抗領域とのコンタクト領域下で、金属が共晶となシ前記
拡散抵抗領域内を基板方向に侵食した場合でも、そのコ
ンタクト領域下には拡散抵抗領域形成より前工程で拡散
抵抗領域より拡散の深さが深い拡散領域が形成しである
ため、前記共晶が基板にまで達して金属配線材と基板と
が電気的に接続されることはない。よって入力リーク電
流は流れない。かつ、拡散抵抗領域と拡散の深さの深い
拡散領域とは同一の導電型の拡散領域であるので、前記
コンタクト領域下に深い拡散領域が形成してあっても、
拡散抵抗はその本来の役目を害されることはない。According to this structure, when a high voltage is applied to the input, the metal becomes eutectic under the contact region between the metal wiring material connected to the input bonding pad and the diffused resistance region. Even if it erodes toward the substrate, the eutectic may not reach the substrate because a diffusion region with a deeper diffusion depth than the diffused resistance region is formed under the contact region in a process prior to the formation of the diffused resistance region. The metal wiring material and the board are not electrically connected. Therefore, no input leakage current flows. In addition, since the diffusion resistance region and the deep diffusion region are of the same conductivity type, even if the deep diffusion region is formed under the contact region,
The diffusion resistance is not compromised in its original role.
実施例の説明
第２図は、本発明の実施例における半導体装置の構造を
示す断面図である。DESCRIPTION OF EMBODIMENTS FIG. 2 is a sectional view showing the structure of a semiconductor device in an embodiment of the present invention.
Ｐ型巣結晶シリコン基板１の１主面に、リンを拡散して
基板方向の深さが数μｍのＮ型の深い拡散領域２を形成
する。そして、ＬＯＧＯ８と呼ばれる選択酸化膜３を成
長させ、それに隣接して活性領域を設ける。その活性領
域にヒ素を拡散することにより、前工程の拡散領域２の
拡散濃度より高濃度で、かつ、拡散の深さが浅い拡散抵
抗領域４を形成する。その後、酸化によって二酸化シリ
コン膜による層間絶縁膜５を形成し、選択的にエツチン
グを行ないコンタクト領域６を形成する。Phosphorus is diffused onto one main surface of a P-type nested crystalline silicon substrate 1 to form an N-type deep diffusion region 2 having a depth of several μm in the substrate direction. Then, a selective oxide film 3 called LOGO8 is grown, and an active region is provided adjacent to it. By diffusing arsenic into the active region, a diffused resistance region 4 is formed which has a higher concentration than the diffusion concentration of the diffusion region 2 in the previous step and has a shallower diffusion depth. Thereafter, an interlayer insulating film 5 of a silicon dioxide film is formed by oxidation, and a contact region 6 is formed by selectively etching.
一方のコンタクト領域は、深い拡散領域２で完全に包括
されるように形成する。そしてその上に金属配線材７を
形成し、拡散領域２上でのコンタクト領域で拡散抵抗領
域と電気的に接続された金属配線材７は入力ボンディン
グ・パッドに接続され他方の金属配線材’ｌｊ内部回路
に接続される。One contact region is formed so as to be completely surrounded by the deep diffusion region 2. Then, a metal wiring material 7 is formed thereon, and the metal wiring material 7, which is electrically connected to the diffused resistance region in the contact region on the diffusion region 2, is connected to the input bonding pad and the other metal wiring material 'lj Connected to internal circuit.
第３図は、本発明の実施例における半導体装置のマスク
レイアウト図である。ａは、拡散の深さの深いＮ型の拡
散領域２のマスクであり、ｂは、拡散抵抗領域４のマス
クを示し、Ｃはコンタクト領域６を形成するマスクであ
り、ｄは金属配線材７のマスクである。FIG. 3 is a mask layout diagram of a semiconductor device in an embodiment of the present invention. a is a mask for the N-type diffusion region 2 with a deep diffusion depth, b is a mask for the diffusion resistance region 4, C is a mask for forming the contact region 6, and d is a mask for forming the metal wiring material 7. It is a mask.
以上のように構成された本実施例の半導体装置によれば
、高入力電圧が印加された場合、入力ボンディング・パ
ッドに接続されている金属配線材７と拡散抵抗領域４と
のコンタクト領域６下において、金属が共晶となって、
拡散抵抗領域４を基板方向に侵食しても、そのコンタク
ト領域θ下には拡散の深さが深い拡散領域２が形成され
ているため、雪の共晶は基板に壕で到達することはない
。According to the semiconductor device of this embodiment configured as described above, when a high input voltage is applied, the contact region 6 between the metal wiring material 7 connected to the input bonding pad and the diffused resistance region 4 is , the metal becomes eutectic,
Even if the diffused resistance region 4 is eroded toward the substrate, the snow eutectic will not reach the substrate in a trench because the diffused region 2 with a deep diffusion depth is formed under the contact region θ. .
それゆえ、本実施例によれば、入力ボンディング令パッ
ドに接続された金属配線材７と拡散抵抗領域４とのコン
タクト領域６下に、コンタクト領域６を包括するように
、拡散抵抗領域４より深い拡散領域２を形成することに
より、高入力電圧によって、コンタクト領域６下の拡散
抵抗領域４に生じた共晶が基板にまで到達して人力ボン
ティング・パッドに接続された金属配線材７と基板１と
が電気的に接続されて入力リーク電流が流れる、という
ことを防ぐことができる。Therefore, according to this embodiment, under the contact region 6 between the metal wiring material 7 connected to the input bonding pad and the diffused resistance region 4, a depth deeper than the diffused resistance region 4 is formed so as to cover the contact region 6. By forming the diffusion region 2, the eutectic generated in the diffusion resistance region 4 under the contact region 6 due to the high input voltage reaches the substrate and connects the metal wiring material 7 and the substrate to the manual bonding pad. It is possible to prevent input leakage current from flowing due to electrical connection between the two terminals.
発明の効果
本発明の半導体装置は、不純管拡散により形成された拡
散抵抗領域の金属配線材との一方のコンタクト領域下に
、拡散抵抗領域の拡散の深さより深く、かつ、不純物濃
度のうすい拡散領域を、前 ノ□記拡散抵抗形成よ
り前工程で、前記コンタクト領 ）域を包括するよ
うに形成することにより、高入力電圧が印加され、前記
コンタクト領域下で金属が共晶となって拡散抵抗領域内
全基板方向に侵食した場合でも、そのコンタクト領域下
には深い拡散領域が形成しであるので、前記共晶が基板
にまで到達して金属配線材と基板とが電気的に接続され
れることはない。それゆえ、本発明によれば、高入力電
圧のために入力リーク電流が流れる、ということを防ぐ
ことができ、その実用的効果は非常に大きい。Effects of the Invention The semiconductor device of the present invention has a diffusion layer which is deeper than the diffusion depth of the diffused resistance region and has a lower impurity concentration under one contact region with the metal wiring material of the diffused resistance region formed by impurity tube diffusion. By forming the region so as to cover the contact region in the process prior to the formation of the diffused resistor described above, a high input voltage is applied, and the metal becomes eutectic and diffuses under the contact region. Even if the resistance region is eroded in the entire direction of the substrate, a deep diffusion region is formed under the contact region, so the eutectic reaches the substrate and electrically connects the metal wiring material and the substrate. It won't happen. Therefore, according to the present invention, it is possible to prevent input leakage current from flowing due to high input voltage, and the practical effect thereof is very large.
第１図は、従来の半導体装置の構造例の断面図、第２図
は、本発明の実施例における半導体装置の構造例の断面
図、第３図は、本発明の実施例における半導体装置のマ
スクレイアウト図である。
１・・・・・Ｐ型巣結晶シリコン基板、２・・・・・・
不純物濃度のうすい、かつ、拡散の深さの深い拡散領域
、３・・・・・・選択酸化膜、４・・団・拡散抵抗領域
、５・・・・・・１間絶縁膜、６・・・・・・コンタク
ト窓、７・・・・・・金属配線材。
代理人の氏名 弁理士 中 尾 敏 男 はが１名第１
図
第２図
第３図FIG. 1 is a cross-sectional view of a structural example of a conventional semiconductor device, FIG. 2 is a cross-sectional view of a structural example of a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view of a structural example of a semiconductor device according to an embodiment of the present invention. It is a mask layout diagram. 1...P-type nest crystal silicon substrate, 2...
Diffusion region with low impurity concentration and deep diffusion depth, 3... selective oxide film, 4... group diffused resistance region, 5... 1 interlayer insulating film, 6... ...Contact window, 7...Metal wiring material. Name of agent: Patent attorney Toshio Nakao (1st person)
Figure 2 Figure 3
Claims (1)
同基板と導電型を異にする浅い拡散の抵抗領域の金属配
線材とのコンタクト領域に、前記抵抗領域の不純物より
低濃度で、かつ、拡散深さの深い、前記基板と導電型を
異にする拡散領域を前記コンタクト領域を包括するよう
に形成したことを特徴とする半導体装置。In a contact region with a metal wiring material of a shallowly diffused resistance region which is formed by impurity diffusion on a semiconductor substrate of one conductivity type and whose conductivity type is different from that of the same substrate, the impurity concentration is lower than that of the resistance region, and A semiconductor device characterized in that a diffusion region having a deep diffusion depth and having a conductivity type different from that of the substrate is formed to encompass the contact region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13832184A JPS6116563A (en) | 1984-07-03 | 1984-07-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13832184A JPS6116563A (en) | 1984-07-03 | 1984-07-03 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6116563A true JPS6116563A (en) | 1986-01-24 |
Family
ID=15219165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13832184A Pending JPS6116563A (en) | 1984-07-03 | 1984-07-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6116563A (en) |
-
1984
- 1984-07-03 JP JP13832184A patent/JPS6116563A/en active Pending
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