JPS6116539A - High speed integrated circuit contained in package - Google Patents

High speed integrated circuit contained in package

Info

Publication number
JPS6116539A
JPS6116539A JP60101180A JP10118085A JPS6116539A JP S6116539 A JPS6116539 A JP S6116539A JP 60101180 A JP60101180 A JP 60101180A JP 10118085 A JP10118085 A JP 10118085A JP S6116539 A JPS6116539 A JP S6116539A
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor substrate
package
speed
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60101180A
Other languages
Japanese (ja)
Inventor
タツシヤー・アール・ギーワラ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JIGABITSUTO ROJITSUKU Inc
Original Assignee
JIGABITSUTO ROJITSUKU Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JIGABITSUTO ROJITSUKU Inc filed Critical JIGABITSUTO ROJITSUKU Inc
Publication of JPS6116539A publication Critical patent/JPS6116539A/en
Pending legal-status Critical Current

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    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Microwave Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 発明の背景 本発明は、ＧａＡｓ　ＩＣのような高速集積回路を、こ
の高速ＩＣを該ＩＣと密接に関連する抵抗器及びコンデ
ンサのような他の構成要素と接続する伝送ラインが精密
に制御されるようにして実装することに係わる。上記実
装の際、高速ＩＣをセラミック製ＩＱツケージの入出力
端子と接続する伝送ラインも精密に制御されることが望
ましい。ライン幅を細く調節することによって、伝送ラ
インのインピーダンスが精密に制御され得、また信号ラ
イン及び入出カラインが高密度に設置され得る。ライン
幅を細（すると付加的な余地が生じ、その結果信号伝送
ライン同士の間に接地線もしくは接地面を挿入すること
が可能となシ、クロストークが減少する。セラミックパ
ッケージ内に設置されるラインの幅はかなし細いもので
も１００マイクロメートルはあるが、平滑な半導体基板
上には幅２〜３マイクロメートルはどの細い金属ライン
が通常の方法で設けられ得る。DETAILED DESCRIPTION OF THE INVENTION Background of the Invention The present invention relates to a transmission system that connects a high speed integrated circuit, such as a GaAs IC, with other components such as resistors and capacitors that are closely associated with the IC. It is concerned with implementing the line so that it is precisely controlled. During the above mounting, it is desirable that the transmission line connecting the high-speed IC to the input/output terminals of the ceramic IQ cage is also precisely controlled. By adjusting the line width to be narrow, the impedance of the transmission line can be precisely controlled, and signal lines and input/output lines can be installed with high density. Narrower line widths (which provide additional room so that a ground wire or ground plane can be inserted between the signal transmission lines, reducing crosstalk; installed in a ceramic package) Although the width of a line is as thin as 100 micrometers, any thin metal line with a width of 2 to 3 micrometers can be provided on a smooth semiconductor substrate by a normal method.

電源雑音をバイパスするためにインピーダンスのきわめ
て低い伝送ライン金設置することも望ましい。インピー
ダンスのきわめて低い伝送ラインは、半導体基板上に５
ｌＯｚ及び５ｉＳＮ４のような絶縁体をデポジットする
半導体処理の際に通常の方法で形成される。上記絶縁体
は半導体材料上に、１．０００オングストロームのオー
ダの厚みにデポジットされる。誘電体がこのように薄（
デポジットされることによシ、と（低インピーダンスの
伝送ラインが形成され得る。通常のようにダイオードが
、静電放電からの保護のため半導体基板上において高速
ＧａＡｌＩ　　ＩＣにきわめて近い位置に形成され得る
。同様にして形成されるトランジスタが、オフチップド
ライバ（ｏｆｆ　−ｃｈｉｐ　ｄｒｉｖｅｒ　）として
ＧａＡｇ　　ＩＣのと（近くに使用され得る。It is also desirable to install very low impedance transmission lines to bypass power supply noise. Very low impedance transmission lines are
It is formed in a conventional manner during semiconductor processing to deposit insulators such as lOz and 5iSN4. The insulator is deposited onto the semiconductor material to a thickness on the order of 1.000 Angstroms. The dielectric is thin like this (
A low impedance transmission line can be formed by depositing the diodes (as usual) in close proximity to the high speed GaAlI IC on the semiconductor substrate for protection from electrostatic discharge. Similarly formed transistors can be used as off-chip drivers (near GaAg ICs).

シリコン半導体基板を用いれは、非線形インピーダンス
のデバイス並びにクランプデバイスをＧａＡ３その他の
高速ＩＣのと（近（に使用することも可能となる。The use of silicon semiconductor substrates also allows nonlinear impedance devices and clamp devices to be used in close proximity to GaA3 and other high-speed ICs.

支持ＩＱツケージの有する補助構成要素及び伝送ライン
が集積回路の高速特性を阻害しないような高速集積回路
用パッケージをもたらすことは、当業者の従来からの課
題である。いかなる高速ＩＣ、Ｑツケージも、機械的、
電気的かつ物理的に配慮して設計される。It is a conventional challenge for those skilled in the art to provide a package for high speed integrated circuits in which the supporting IQ packages have auxiliary components and transmission lines that do not interfere with the high speed characteristics of the integrated circuits. Any high-speed IC, Q-Tcage, mechanical,
Designed with electrical and physical considerations in mind.

発明の概要 本明細書に記載した本発明とその具体例によって、高速
ＧａＡＦＩ　　ＩＣの実装形態が改善される。SUMMARY OF THE INVENTION The invention and its embodiments described herein improve the implementation of high speed GaAFI ICs.

好ましくは、ＧａＡｓ　　ＩＣは半導体基板にエポキシ
樹脂か、はんだか、共融化合物を用いて接着され、半導
体基板とＧａＡａ　　ＩＣとの間の電気的接続はボンデ
ィングワイヤによってもたらされる。Preferably, the GaAs IC is bonded to the semiconductor substrate using epoxy, solder, or eutectic, and electrical connections between the semiconductor substrate and the GaAa IC are provided by bonding wires.

ＧａＡｓ　ＩＣはまた、多重はんだボール（Ｃ４として
も知られる）が用いられる６フリツプ取付は型（ｆｌｉ
ｐ　−ｍｏｕｎｔｅｄ　）”でちってもよい。その場合
、ＧａＡｓ　　ＩＣからの入力ライン、出力ライン、電
源ライン及び接地線は半導体基板である支持体上の信号
ラインと直接はんだ付けされる。信号伝送ラインは半導
体基板支持体上に形成され、この支特休にはまた、電源
ラインに存在し得る電源雑音をバイパスするのに用いら
れる低インピーダンスコンデンサも設けられる。半導体
基板はまた、抵抗器、フィルタ、インピーダンス整合回
路網、インピーダンス変成器、並びにダイオード、バイ
ポーラトランジスタ、電界効果トランジスタ及び電圧調
整器のような能動半導体デバイスをも支持し得る。上記
のようなデバイスを半導体基板上に形成する方法は、当
業者には周知である。次いで半導体基板がセラミック類
の／（ツケージ内に取付けられ、この／ξミツケージ、
高速ＩＣ及び半導体基板とプリント基板とを接続する入
力及び出力接続部を具備している。セラミツクツ９ツケ
ージは、衝撃、湿気、腐食性の化学薬品等からの保＠を
もたらす。多数の半導体基板支持体をただ１個のセラミ
ツクツ９ツケージにか、あるいはまた直接プリント基板
に実装することも可能であ）、この実装方法によって混
成回路の構成に適した手段が提供される。半導体基板の
使用によって伝送ラインの幅及びインピーダンスが微細
に制御され得、を大基板支持体上に能動及び受動電気デ
バイスが設置され得る。GaAs ICs are also available in a 6-flip mounting system where multiple solder balls (also known as C4) are used.
In that case, the input line, output line, power line, and ground line from the GaAs IC are directly soldered to the signal line on the support, which is a semiconductor substrate.Signal transmission line are formed on the semiconductor substrate support and are also provided with low impedance capacitors that are used to bypass power supply noise that may be present on the power supply line.The semiconductor substrate also includes resistors, filters, Impedance matching networks, impedance transformers, and active semiconductor devices such as diodes, bipolar transistors, field effect transistors, and voltage regulators may also be supported. It is well known in the art that the semiconductor substrate is then mounted in a ceramic /ξ cage;
It is equipped with input and output connections for connecting a high-speed IC and a semiconductor substrate to a printed circuit board. The ceramic cage provides protection from impact, moisture, corrosive chemicals, etc. It is also possible to mount a number of semiconductor substrate carriers on a single ceramic cage or even directly on a printed circuit board), and this mounting method provides a suitable means for the construction of hybrid circuits. Through the use of semiconductor substrates, the width and impedance of transmission lines can be finely controlled and active and passive electrical devices can be mounted on large substrate supports.

従って本発明は、改良され九高速ｘｃ／ｅツケージの提
供を目的とする。SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an improved nine-speed xc/e cage.

本発明はまた、伝送ラインの幅が精密に制御され得る基
板支持体パッケージの提供も目的とし、このノ（ツケー
ジは高速ＩＣの特性全補足する。The present invention also aims to provide a substrate support package in which the width of the transmission line can be precisely controlled, which complements all the characteristics of high speed ICs.

本発明は、抵抗器及びコンデンサのような受動の電子的
構成要素を自身の一部として具備したＩＣ支持／（ツケ
ージの提供も目的とする。The present invention also seeks to provide an IC support/(cage) having as part of it passive electronic components such as resistors and capacitors.

更に本発明は、基板支持体パッケージの支持する高速Ｉ
Ｃの特性を補足する能動半導体デバイスも前記〕ｑツケ
ージ内に設置することをも目的とする。Further, the present invention provides a substrate support package supporting high speed I
It is also an object of the present invention to install an active semiconductor device that complements the characteristics of C into the above-mentioned q cage.

本発明の目的及び諸特徴を、添付図面を参照しつつ以下
に詳述する◎ 好ましい具体例の説明 第１図は、ポリイミドベースのエポキシ樹脂あるいは銀
エポキシ樹脂（５ｉｌｖｅｒ　ｅｐｏｘｙ　）のような
導電性のエポキシ樹脂によって半導体基板３４と接着さ
れたＧａＡｓ　ＩＣ２８を示し、前記基板３４はセラミ
ック類のキャリヤ１０上に設置されている。The objects and features of the present invention will be described in detail below with reference to the accompanying drawings. ◎ Description of Preferred Embodiments FIG. A GaAs IC 28 is shown bonded by epoxy to a semiconductor substrate 34, which is mounted on a ceramic carrier 10.

ＧａＡｓ　ＩＣ２８を半導体基板３４と結合する方法は
多数ある。一つの方法として、エポキシ樹脂（あるいは
ポリイミド樹脂）を基板上に滴下し、その上にＧａＡｓ
　ＩＣを載せて軽く擦った後に２００〜３００Ｃでベー
クする。より高い温度３００〜５００　Ｃで行なわれる
別の方法では、ＧａＡｓ　ＩＣと基板支持体とは通常の
方法で互いにはんだ付けされる。There are many ways to bond GaAs IC 28 to semiconductor substrate 34. One method is to drop epoxy resin (or polyimide resin) onto the substrate and place GaAs on it.
After placing the IC and rubbing it lightly, bake it at 200-300C. In another method carried out at higher temperatures of 300-500 C, the GaAs IC and substrate support are soldered together in a conventional manner.

ＱａＡａ集積回路２８と半導体基板３４との電気的接続
は、ボンディングワイヤ３０によって達成される。前記
接続はまた、饋−外６や、ワイヤの横断面力喋力形であ
るテープ自動化ボンディングで用いられるような異なる
形状のワイヤをはんだ付けすることによってもたらされ
得る。信号伝送ライン２０が、ＧａＡｆｌ集積回路２８
の入力ラインあるいは出力ラインを、半導体基板３４上
に通常の方法で物理的にデポジットされて基板３４の一
部となっている整合コンデンサ２６などの構成要素と接
続するのに用いられる。はんだ接続部、溶接部、テープ
あるいは騎ρ並でもよいワイヤ４６が半導体基板３４上
の整合コンデンサ２６を、セラミック類のチップキャリ
ヤ１０上に配置された入力あるいは出力端子２４と接続
する。入出カライン２４はまた入出カライン２２と物理
的に接続され、このライン２２はパッケージ全体をシス
テム内の他の電子回路と電気的に接続する。図中、Ｇａ
Ａｇチップ２８は、前もって半導体基板３４上にデポジ
ットサしたバイパスフンデンサ１４とも接続されている
。パイノ９スコンデンサ１４はワイヤ１８によって、セ
ラミックチップキャリヤ１０上の入出カライン１２と接
続されている。Electrical connection between QaAa integrated circuit 28 and semiconductor substrate 34 is achieved by bonding wires 30. The connection may also be effected by soldering wires of different shapes, such as those used in tape automated bonding, where the cross-section of the wire is force-tight. The signal transmission line 20 is a GaAfl integrated circuit 28
are used to connect the input or output lines of the semiconductor substrate 34 to components such as matching capacitors 26 that are physically deposited on the semiconductor substrate 34 in a conventional manner and become part of the substrate 34. Wires 46, which may be solder connections, welds, tape, or wires, connect matching capacitors 26 on semiconductor substrate 34 to input or output terminals 24 disposed on ceramic chip carrier 10. Input/output line 24 is also physically connected to input/output line 22, which electrically connects the entire package to other electronic circuits in the system. In the figure, Ga
The Ag chip 28 is also connected to the bypass capacitor 14 deposited on the semiconductor substrate 34 in advance. The pinos capacitor 14 is connected by a wire 18 to the input/output line 12 on the ceramic chip carrier 10.

通常のように抵抗器３２が半導体基板３４上にデポジッ
トされて、伝送ライン３６と接続され、またワイヤ４０
によってＧａＡｇ集積回路２８とも接続されている。抵
抗器３２はワイヤ３８によって、セラミックチップキャ
リヤ１０とも接続されている。A resistor 32 is conventionally deposited on a semiconductor substrate 34 and connected to a transmission line 36 and a wire 40
It is also connected to the GaAg integrated circuit 28 by. Resistor 32 is also connected to ceramic chip carrier 10 by wire 38 .

図示のように、電圧調整器１６のような能動電気デバイ
スが半導体基板３４上に物理的にデポジットされ得る。As shown, active electrical devices, such as voltage regulator 16, may be physically deposited on semiconductor substrate 34.

伝送ライン４２が電圧調整器１６をＧａＡｓチツゾ２８
と、ワイヤ４３を介して接続する。ワイヤ４４によって
、電圧調整器１６はセラミックチップキャリア１０と接
続されている。The transmission line 42 connects the voltage regulator 16 to the GaAs transistor 28.
and are connected via wire 43. A wire 44 connects the voltage regulator 16 to the ceramic chip carrier 10 .

第３図は半導体基板３４上の接地面５０を示し、この接
地面５０は信号ライン５２を囲繞して、信号同士のクロ
ストークを最少にする。伝送ラインのインピーダンスが
、接地面と伝送ラインとの間隔を変更することによって
制御され得る。信号ライン５２は、第３図に示すような
いわゆるコ、プレーす型（ｃｏｐｌａｎａｒ　）伝送ラ
インであるか、あるいはまた第４図に示すようないわゆ
るマイクロストリップライン５４であり得る。第４図は
、接地面５０上に位置する絶縁体５６の上に設置された
信号ライン５４を示す。信号ライ１５２及び５４並びに
誘電体５６の寸法は、所望のインピーダンスが得られる
ように選択される。半導体基板３４上の接地面５０はＧ
ａＡｇ　ＩＣ２８上の接地面（図示せず）と電気的に接
続されている。FIG. 3 shows a ground plane 50 on semiconductor substrate 34 that surrounds signal lines 52 to minimize crosstalk between signals. The impedance of the transmission line can be controlled by changing the spacing between the ground plane and the transmission line. The signal line 52 may be a so-called coplanar transmission line as shown in FIG. 3, or alternatively a so-called microstrip line 54 as shown in FIG. FIG. 4 shows a signal line 54 mounted on an insulator 56 located on a ground plane 50. FIG. The dimensions of signal lines 152 and 54 and dielectric 56 are selected to provide the desired impedance. The ground plane 50 on the semiconductor substrate 34 is G
It is electrically connected to the ground plane (not shown) on the aAg IC28.

第２図は、各々の半導体基板３４と接続された複数個の
ＧａＡｓ　ＩＣ２８を示し、前記基板３４は多層プリン
ト基板４８と結合されている。ＧａＡｓＩＣ２８とその
半導体基板３４の各組は、標準的なゾ＋）Ｗ上基板のト
レースであるワイヤ５０によって互いに接続されている
。多層プリント基板４８は、半導体基板３４同士を電気
的に接続する幾つかの回路層を有する。FIG. 2 shows a plurality of GaAs ICs 28 connected to respective semiconductor substrates 34, which are coupled to a multilayer printed circuit board 48. FIG. Each pair of GaAs ICs 28 and their semiconductor substrates 34 are connected together by wires 50, which are standard Z+W on-board traces. Multilayer printed circuit board 48 has several circuit layers that electrically connect semiconductor substrates 34 to each other.

本明細書において、本発明の好ましい具体例を説明しか
つ図示したが、様々な変形が当業者には明らかであり、
そのような変形及び変更の総てを特許請求の範囲の各項
に包含させた。While preferred embodiments of the invention have been described and illustrated herein, various modifications will be apparent to those skilled in the art.
All such modifications and changes are intended to be included within the scope of the following claims.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は高速集積回路並びに該回路の、伝送ライン及び
関連補助デバイス、即ち抵抗器、バイｌＲスコンデンサ
、インヒータンス整合コンデンサ、トランジスタ及び電
圧調整器などを有する半導体基板支持体との接続を示す
斜視図、第２図は多層プリント基板上に配置された複数
個の半導体支持チップの支持する複数個のＧａＡｇＩＣ
を示す説明図、第３図は高速集積回路並びに該回路の、
接地面に囲繞された伝送ラインを有する半導体基板支持
体との接続を示す斜視図、第４図は接地面上に載置され
た絶縁体上に位置−するマイクロストリップ信号ライン
を示す説明図である。 １０・・・セラミックチップキャリヤ、１２、２２．２
４・・・入出カライン、１４・・・パイ／Ｑスコンデン
サ、　　１６・・・電圧調整器、　１８．３ｇ、　４０
゜招・祠、４６・・・ワ　イ　ヤ、　２０．３６．４２
・・・伝送ライン、２６・・・整合コンデンサ、　詔・
・・ＧａＡｓ集積回路、３０・・・ボンディングワイヤ
、３２・・・抵抗器、　３４・・・半導体基板、４８・
・・多層プリント基板、　５ｏ・・・接地面、５２．５
４・・・信号ライン、　５６・・・絶　縁　体。 代理人　弁理土用　　口　　我　　莱 ｆｆｉ百の浄書（白毛＝（二変更なしン手続補正書 昭和６０年７月λ十日 １、事件の表示　　　昭和６０年特許願第１０１１８０
号２、発明の名称　　　パッケージに収容された高速集
積回路３、補正をする者 事件との関係　　特許出願人 名　称　　　　シカビット・ロジック・インコーホレイ
テッド ４、代　理　人　　　東京都新宿区新宿１丁目１番１４
号　山田ビル（郵便番号１６０）電話（０３）　　３５
４−８６９３６、補正により増加する発明の数 ７、補正の対象　　　図面 ８、補正の内容　　　正式図面を別紙の通り補充する。FIG. 1 is a perspective view showing a high speed integrated circuit and its connection to a semiconductor substrate support including transmission lines and associated auxiliary devices, such as resistors, bias capacitors, inheatance matching capacitors, transistors and voltage regulators; FIG. Figure 2 shows a plurality of GaAg ICs supported by a plurality of semiconductor support chips arranged on a multilayer printed circuit board.
FIG. 3 is an explanatory diagram showing a high-speed integrated circuit and the circuit.
FIG. 4 is a perspective view showing a connection to a semiconductor substrate support having a transmission line surrounded by a ground plane; FIG. be. 10... Ceramic chip carrier, 12, 22.2
4... Input/output power line, 14... Pi/Q capacitor, 16... Voltage regulator, 18.3g, 40
゜Invitation Shrine, 46...Wire, 20.36.42
...Transmission line, 26...Matching capacitor, Imperial order
...GaAs integrated circuit, 30...bonding wire, 32...resistor, 34...semiconductor substrate, 48...
...Multilayer printed circuit board, 5o...ground plane, 52.5
4...Signal line, 56...Insulator. Agent Patent Attorney Doyo Kuchi I Raiffi Hyakusho (White Hair = (2 No Changes) Procedural Amendment July 1985 λ 10th 1, Case Description 1985 Patent Application No. 101180
No. 2, Title of the invention: High-speed integrated circuit housed in a package 3, Relationship to the amended case Name of patent applicant: Sikabit Logic Incorporated 4, Agent: 1-14 Shinjuku, Shinjuku-ku, Tokyo
No. Yamada Building (zip code 160) Telephone (03) 35
4-86936, Number of inventions increased by amendment 7, Subject of amendment Drawing 8, Contents of amendment Official drawings will be supplemented as shown in the attached sheet.

Claims (8)

【特許請求の範囲】[Claims] （１）集積回路を支持する半導体基板手段を含み、この
半導体基板手段がインピーダンスの制御された伝送ライ
ン、接地線、並びに該手段上の集積回路と接続される電
子的構成要素を提供するべく構成されていることを特徴
とするパツケージに収容された高速集積回路。(1) Semiconductor substrate means for supporting an integrated circuit, the semiconductor substrate means configured to provide controlled impedance transmission lines, ground lines, and electronic components for connection with the integrated circuit on the means. A high-speed integrated circuit housed in a package characterized by: （２）集積回路が高速ＧａＡｓ集積回路であり、半導体
基板手段はシリコンベースの半導体から成ることを特徴
とする特許請求の範囲第１項に記載の高速集積回路。(2) A high-speed integrated circuit according to claim 1, wherein the integrated circuit is a high-speed GaAs integrated circuit and the semiconductor substrate means comprises a silicon-based semiconductor. （３）半導体基板手段がプラスチック製のチップ支持手
段上に設置されており、前記支持手段はチップに電気的
接続をもたらし、かつチップの汚れを防ぐべく構成され
ていることを特徴とする特許請求の範囲第１項に記載の
高速集積回路。(3) The semiconductor substrate means is mounted on a plastic chip support means, said support means being configured to provide electrical connections to the chip and to prevent contamination of the chip. A high-speed integrated circuit according to scope 1. （４）１個の配線手段上に配置された各々集積回路を支
持する複数個の半導体基板を含み、これらの半導体基板
がインピーダンスの制御された伝送ライン、接地線、並
びに該基板上の集積回路と接続される電子的構成要素を
提供するべく構成されていることを特徴とするパツケー
ジに収容された高速集積回路。(4) It includes a plurality of semiconductor substrates each supporting an integrated circuit arranged on one wiring means, and these semiconductor substrates serve as a transmission line with controlled impedance, a ground line, and an integrated circuit on the substrate. 1. A high speed integrated circuit housed in a package, the circuit being configured to provide electronic components for connection with the circuit. （５）高速集積回路を支持している半導体基板上に位置
する受動構成要素を含み、この受動構成要素が前記半導
体基板上に配置された電源ラインを容量的にバイパスす
る逆バイアスされた接合型ダイオードであることを特徴
とするパツケージに収容された高速集積回路。(5) a reverse biased junction type including a passive component located on a semiconductor substrate supporting a high speed integrated circuit, the passive component capacitively bypassing a power supply line located on the semiconductor substrate; A high-speed integrated circuit housed in a package characterized by being a diode. （６）集積回路を支持する半導体基板支持体を含み、こ
の半導体基板支持体の高速信号ラインがその末端で該支
持体の一部である整合抵抗器に接続していることを特徴
とするパッケージに収容された高速集積回路。(6) A package comprising a semiconductor substrate support supporting an integrated circuit, the high speed signal line of the semiconductor substrate support being connected at its terminus to a matching resistor that is part of the support. High-speed integrated circuits housed in. （７）半導体基板支持体上に位置する絶縁体上に配置さ
れた定インピーダンスのコプレーナ型マイクロストリッ
プラインを含み、このマイクロストリップラインが前記
半導体基板支持体上に設けられた集積回路に接続してい
ることを特徴とするパツケージに収容された高速集積回
路。(7) a constant impedance coplanar microstrip line disposed on an insulator located on a semiconductor substrate support, the microstrip line being connected to an integrated circuit provided on the semiconductor substrate support; A high-speed integrated circuit housed in a package characterized by: （８）集積回路を支持する半導体基板手段を含み、この
半導体基板手段がインピーダンスの制御された伝送ライ
ンを提供するべく構成されていることを特徴とするパッ
ケージに収容された高速集積回路。(8) A high speed integrated circuit housed in a package comprising semiconductor substrate means for supporting the integrated circuit, the semiconductor substrate means being configured to provide a controlled impedance transmission line.
JP60101180A 1984-05-14 1985-05-13 High speed integrated circuit contained in package Pending JPS6116539A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US60972884A 1984-05-14 1984-05-14
US609728 2003-06-30

Publications (1)

Publication Number Publication Date
JPS6116539A true JPS6116539A (en) 1986-01-24

Family

ID=24442081

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60101180A Pending JPS6116539A (en) 1984-05-14 1985-05-13 High speed integrated circuit contained in package

Country Status (4)

Country Link
JP (1) JPS6116539A (en)
DE (1) DE3516954A1 (en)
FR (1) FR2564244B1 (en)
GB (1) GB2160707B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0226243U (en) * 1988-08-08 1990-02-21

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Publication number Priority date Publication date Assignee Title
US4754317A (en) * 1986-04-28 1988-06-28 Monolithic Memories, Inc. Integrated circuit die-to-lead frame interconnection assembly and method
US4774635A (en) * 1986-05-27 1988-09-27 American Telephone And Telegraph Company At&T Bell Laboratories Semiconductor package with high density I/O lead connection
FR2623662B1 (en) * 1987-11-20 1990-03-09 Labo Electronique Physique CONNECTION DEVICE FOR ULTRA-FAST DIGITAL INTEGRATED CIRCUITS
US5089878A (en) * 1989-06-09 1992-02-18 Lee Jaesup N Low impedance packaging
US5063177A (en) * 1990-10-04 1991-11-05 Comsat Method of packaging microwave semiconductor components and integrated circuits
US20030089998A1 (en) * 2001-11-09 2003-05-15 Chan Vincent K. Direct interconnect multi-chip module, method for making the same and electronic package comprising same

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Publication number Priority date Publication date Assignee Title
EP0007993A1 (en) * 1978-07-12 1980-02-20 Siemens Aktiengesellschaft Conductor plate for mounting and electrically connecting semiconductor chips
JPS5687395A (en) * 1979-12-18 1981-07-15 Fujitsu Ltd Semiconductor device
CA1115852A (en) * 1980-01-09 1982-01-05 Jacques R. St. Louis Mounting and packaging of silicon devices on ceramic substrates, and assemblies containing silicon devices
JPS6041861B2 (en) * 1980-03-25 1985-09-19 三菱電機株式会社 semiconductor equipment
JPS57154861A (en) * 1981-03-20 1982-09-24 Hitachi Ltd Package
US4437141A (en) * 1981-09-14 1984-03-13 Texas Instruments Incorporated High terminal count integrated circuit device package
GB2117564B (en) * 1982-03-26 1985-11-06 Int Computers Ltd Mounting one integrated circuit upon another
JPS58210650A (en) * 1982-06-01 1983-12-07 Fujitsu Ltd Semiconductor device
GB2136203B (en) * 1983-03-02 1986-10-15 Standard Telephones Cables Ltd Through-wafer integrated circuit connections

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0226243U (en) * 1988-08-08 1990-02-21

Also Published As

Publication number Publication date
GB8512092D0 (en) 1985-06-19
FR2564244B1 (en) 1988-12-02
GB2160707B (en) 1988-10-19
GB2160707A (en) 1985-12-24
DE3516954A1 (en) 1985-11-14
FR2564244A1 (en) 1985-11-15

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