JPS61148880A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61148880A JPS61148880A JP27113284A JP27113284A JPS61148880A JP S61148880 A JPS61148880 A JP S61148880A JP 27113284 A JP27113284 A JP 27113284A JP 27113284 A JP27113284 A JP 27113284A JP S61148880 A JPS61148880 A JP S61148880A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- vacuum chamber
- polycrystalline silicon
- conducting layers
- contact holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 38
- 239000010703 silicon Substances 0.000 claims abstract description 38
- 238000004544 sputter deposition Methods 0.000 claims abstract description 12
- 238000000992 sputter etching Methods 0.000 claims abstract description 11
- 238000004140 cleaning Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 39
- 239000000758 substrate Substances 0.000 abstract description 15
- 238000005530 etching Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 13
- 239000007789 gas Substances 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体装置の製造方法に関し、特にシリコン
基板表面の拡散層や多結晶シリコン配線等のシリコンか
らなる導電層と多結晶シリコン電極とのコンタクト技術
を改良した半導体装置の製造方法に係わる。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device. It relates to a method for manufacturing semiconductor devices using improved contact technology.
最近、多結晶シリコンをシリコン基板表面の拡散層やゲ
ート電極等の取出し配線として用いられている。かかる
多結晶シリコン配線を有する半導体装置、例えばｎチャ
ンネルＭＯＳトランジスタは、従来より以下に示す方法
によって製造されている。Recently, polycrystalline silicon has been used as a diffusion layer on the surface of a silicon substrate and as lead wiring for gate electrodes and the like. Semiconductor devices having such polycrystalline silicon wiring, such as n-channel MOS transistors, have conventionally been manufactured by the method described below.
まず、ｐ型シリコン基板１表面に選択酸化法によりフィ
ールド酸化膜２を形成し゛た後、熱酸化処理を施してフ
ィールド酸化膜２で分離された島状の基板１表面にゲー
ト酸化膜３を形成する。つづいて、全面に多結晶シリコ
ン膜を堆積し、該多結晶シリコン膜をパターニングして
ゲート電極４を形成する。ひきつづき、前記フィールド
酸化膜２及びゲート電極４をマスクとしてｎ型不純物、
例えば砒素を前記島状の基板１表面に選択的にイオン注
入し、活性化してｎ４″型のソース、ドレイン領域５１
．６を形成する（第３図（ａ）図示）。First, a field oxide film 2 is formed on the surface of a p-type silicon substrate 1 by selective oxidation, and then a gate oxide film 3 is formed on the surface of the island-shaped substrate 1 separated by the field oxide film 2 by thermal oxidation treatment. do. Subsequently, a polycrystalline silicon film is deposited over the entire surface, and the polycrystalline silicon film is patterned to form a gate electrode 4. Subsequently, using the field oxide film 2 and gate electrode 4 as a mask, an n-type impurity,
For example, arsenic is selectively ion-implanted into the surface of the island-shaped substrate 1 and activated to form the n4'' type source and drain regions 51.
．． 6 (as shown in FIG. 3(a)).
次いで、ゲート電極４を含む全面に層間絶縁躾としての
ＣＶＤ−８ｉ０２膜７を堆積した後、前記ゲート電極４
及びソース、ドレイン領域５．６の一部に対応するＣＶ
Ｄ−８ｉ０２躾７にフォトエツチング技術によりコンタ
クトホール８を開孔する（同図（ｂ）図示）。つづいて
、ＳｉＨ＋の熱分解反応による減圧ＣＶＤ法によって全
面に多結晶シリコン膜を堆積し、更にリン等の不純物を
該多結晶シリコンに拡散して低抵抗・かした後、該多結
晶シリコンをバターニングして前記コンタクトホール８
を通してゲート電極４、ソース、ドレイン領域５．６と
夫々接続する多結晶シリコン配線９〜１１を夫々形成し
てｎチャンネルＭＯＳトランジスタを製造する（同図（
Ｃ）図示）。Next, after depositing a CVD-8i02 film 7 as an interlayer insulation layer on the entire surface including the gate electrode 4,
and CV corresponding to part of the source and drain regions 5.6
A contact hole 8 is formed in the D-8i02 plate 7 by photo-etching technique (as shown in FIG. 8(b)). Next, a polycrystalline silicon film is deposited on the entire surface by low-pressure CVD using a thermal decomposition reaction of SiH+, and impurities such as phosphorus are diffused into the polycrystalline silicon to make it low in resistance. contact hole 8.
An n-channel MOS transistor is manufactured by forming polycrystalline silicon wirings 9 to 11, which are respectively connected to the gate electrode 4 and the source and drain regions 5.6 through the
C) As shown).
しかしながら、従来の方法にあっては、ＣｖＤ−８ｉ
０２１１７にコンタクトホール８を開孔した後、多結晶
シリコン膜′を堆積するまでの間に大気中の酸素とコン
タクトホール８から露出したゲート電極４やソース、ド
レイン領域５．６を構成するシリコンとが反応して酸化
物１２を生成するため、前記多結晶シリコン配線９〜１
１とゲート電極４やソース、ドレイン領域５．６とのコ
ンタクト抵抗が増大するという問題があったｒ特に、Ｍ
ＯＳトランジスタの微細化に伴って、コンタクトホール
の寸法が縮小されると、前記コンタクト抵抗の増大はよ
り一層顕著となる。However, in conventional methods, CvD-8i
After the contact hole 8 is opened at 02117 and before the polycrystalline silicon film is deposited, oxygen in the atmosphere and the silicon forming the gate electrode 4 and the source and drain regions 5 and 6 exposed from the contact hole 8 are exposed. reacts to generate oxide 12, so that the polycrystalline silicon wirings 9 to 1
There was a problem in that the contact resistance between M 1 and the gate electrode 4 and the source and drain regions 5.6 increased.
As the size of the contact hole decreases with miniaturization of OS transistors, the increase in contact resistance becomes even more remarkable.
（発明の目的）
本発明は、シリコン基板表面の拡散層や多結晶シリコン
電極等のシリコンからなる導電層と多結晶シリコン配線
とを微細なコンタクトホールを通して接続した場合でも
低抵抗のコンタクトを実現できる高信頼性、高集積度の
半導体装置の製造方法を提供しようとするものである。(Object of the invention) The present invention can realize a low-resistance contact even when a conductive layer made of silicon such as a diffusion layer on the surface of a silicon substrate or a polycrystalline silicon electrode is connected to a polycrystalline silicon wiring through a fine contact hole. The present invention aims to provide a method for manufacturing a highly reliable and highly integrated semiconductor device.
本発明は、シリコンからなる導電層上に絶縁膜を形成す
る工程と、この絶縁膜に前記導電層表面に達するコンタ
クトホールを選択的に開孔する工程と、前記コンタクト
ホールから露出するシリコンの導電層を、真空槽内での
スパッタエツチングにより清浄化処理を行なった後、同
一の真空槽内でシリコンのスパッタリングを行なってシ
リコン族を堆積する工程とを具備したことを特徴とする
ものである。かかる本発明によれば、既述した如くシリ
コン基板表面の拡散層や多結晶シリコン、電極等のシリ
コンからなる導電層と多結晶シリコン配線とを微細なコ
ンタクトホールを通して接続した場合でも低抵抗コンタ
クトを実現できる高信頼性、高集積度の半導体装置を得
ることができる。The present invention includes a step of forming an insulating film on a conductive layer made of silicon, a step of selectively opening a contact hole in the insulating film reaching the surface of the conductive layer, and a step of forming a conductive layer of silicon exposed from the contact hole. This method is characterized by the step of cleaning the layer by sputter etching in a vacuum chamber, and then depositing a silicon group by sputtering silicon in the same vacuum chamber. According to the present invention, as described above, even when a conductive layer made of silicon such as a diffusion layer, polycrystalline silicon, or an electrode on the surface of a silicon substrate is connected to a polycrystalline silicon wiring through a fine contact hole, a low resistance contact can be made. A highly reliable and highly integrated semiconductor device can be obtained.
以下、本発明をｎチャンネルＭＯＳトランジスタの製造
に適用した例についてＭ１図及び第２図（ａ）〜（ｄ）
を参照して説明する。Below, an example in which the present invention is applied to the manufacture of an n-channel MOS transistor is shown in Figure M1 and Figures 2 (a) to (d).
Explain with reference to.
第１図は、本実施例に使用するスパッタリング装置の概
略図であり、図中の２１は真空槽である。FIG. 1 is a schematic diagram of a sputtering apparatus used in this example, and numeral 21 in the figure is a vacuum chamber.
この真空槽２１内は、隔壁２２で区画されたスパッタエ
ツチングを行なう第１の真空室２３１と、シリコンのス
パッタリングを行なう第２の真空室２３２とが形成され
ている。第１の真空室２３１側の真空槽２１の側壁にも
開閉自在な第１のシャッタ２４１が設けられている。前
記隔！２２には開閉自在な第２のシャッタ２４２が設け
られている。また、前記第１の真空室２３１内には平行
して対向する一対の平板電極２５ａ、２５ｂが配設され
ている。この上部平板電極２５ａは、グランドに接続さ
れており、かつ前記下部平板電極２５ｂは高周波電源２
６を介してグランドに接続されている。前記第１の真空
室２３１内には、前記一対の平板電極間に磁界を与える
ための電磁石２７が配−設されている。こうした高周波
電１２６から一対の平板電極２５ａ、２５ｂの′間に高
周波を入力すると共に、前記電磁石２７から磁界を与え
ることによって、前記一対の平板電極２５ａ、２５ｂ間
でマグネトロン放電がなされる。更に、前記第１の真空
室２３１の真空槽２１の側壁上部にはＡｒガスの導入管
２８が連結されていると共に、同下部壁面には排気管２
９が連結されている。一方、前記第２の真空室２３２内
にはシリコンからなるターゲット、該ターゲットとの間
で放電を行なう平板電極、該ターゲットと平板電極の間
に高周波電力を入力するための高周波電源（いずれも図
示せず）が配設されていると共に、該第２の真空室２３
２の真空槽２１にはＡｒとＨ２を導入する導入管及び排
気管（いずれも図示せず）が連結されている。Inside the vacuum chamber 21, there are formed a first vacuum chamber 231 for performing sputter etching and a second vacuum chamber 232 for performing silicon sputtering, which are partitioned by partition walls 22. A first shutter 241 that can be opened and closed is also provided on the side wall of the vacuum chamber 21 on the first vacuum chamber 231 side. Said interval! 22 is provided with a second shutter 242 that can be opened and closed. Furthermore, a pair of flat plate electrodes 25a and 25b are arranged in parallel and opposite to each other in the first vacuum chamber 231. This upper flat plate electrode 25a is connected to the ground, and the lower flat plate electrode 25b is connected to the high frequency power source 2.
6 to ground. An electromagnet 27 is disposed within the first vacuum chamber 231 for applying a magnetic field between the pair of flat electrodes. By inputting a high frequency wave from the high frequency electric field 126 between the pair of plate electrodes 25a and 25b and applying a magnetic field from the electromagnet 27, magnetron discharge is generated between the pair of plate electrodes 25a and 25b. Furthermore, an Ar gas introduction pipe 28 is connected to the upper side wall of the vacuum chamber 21 of the first vacuum chamber 231, and an exhaust pipe 28 is connected to the lower wall surface of the same.
9 are connected. On the other hand, inside the second vacuum chamber 232, there is a target made of silicon, a flat plate electrode for discharging with the target, and a high frequency power source for inputting high frequency power between the target and the flat plate electrode (all of which are shown in the figure). ) is provided, and the second vacuum chamber 23
The second vacuum chamber 21 is connected to an inlet pipe for introducing Ar and H2 and an exhaust pipe (both not shown).
次に、ＭＯＳトランジスタの製造方法を説明する。Next, a method for manufacturing a MOS transistor will be explained.
まず、ｐ型シリコン基板３１表面に選択酸化法によりフ
ィールド酸化膜３２を形成した後、熱酸化処理を施して
フィールド酸化膜３２で分離された島状の基板３１領域
表面に厚さ１５０人の熱酸化１１３３を形成した（第２
図（ａ）Ｉ示）。つづいて、全面に厚さ３０００人の多
結晶シリコン膜をＣＶＤ法により堆積し、更にＰＯＣｊ
２ｉの雰囲気で多結晶シリコン膜にリン拡散を行なって
低抵抗化した後、フォトエツチング技術により該多結晶
シリコン膜をバターニングしてゲート電極３４を形成し
た。ひきつづき、フィールド酸化膜３２及びゲート電極
３４をマスクとしてｎ型不純物、例えば砒素を前記島状
の基板３１領域にイオン注入し、活性化してｎ＋型のソ
ース、ドレイン領域３５．３６を形成した（同図（ｂ）
図示）。First, a field oxide film 32 is formed on the surface of a p-type silicon substrate 31 by a selective oxidation method, and then a thermal oxidation treatment is applied to the surface of the island-shaped substrate 31 separated by the field oxide film 32 to a thickness of 150 mm. Oxide 1133 was formed (second
Figure (a) I). Subsequently, a polycrystalline silicon film with a thickness of 3000 nm was deposited on the entire surface using the CVD method, and further POCj
After phosphorus was diffused into the polycrystalline silicon film in an atmosphere of 2i to lower its resistance, the polycrystalline silicon film was buttered by photoetching to form a gate electrode 34. Subsequently, using the field oxide film 32 and the gate electrode 34 as a mask, n-type impurities, such as arsenic, were ion-implanted into the island-shaped substrate 31 region and activated to form n+-type source and drain regions 35 and 36 (same as above). Figure (b)
(Illustrated).
次イテ、全面に厚さ１μＩＴＩのＣＶＤ−８ｉ０２膜３
７を堆積した後、フォトエツチング技術と反応性イオン
エツチング技術を用いてＣＶＤ−８ｉ０２膜３７の前記
ゲート電極３４、ソース、ドレイン領域３５．３６の一
部に対応する部分及び熱酸化膜３３を選択的に除去して
約１〜１．５μｍのコンタクトホール３８１〜３８３を
開孔した（同図（Ｃ）図示）。Next iteration, CVD-8i02 film 3 with a thickness of 1 μITI on the entire surface.
After depositing 7, portions of the CVD-8i02 film 37 corresponding to parts of the gate electrode 34, source and drain regions 35 and 36, and the thermal oxide film 33 are selected using photoetching technology and reactive ion etching technology. contact holes 381 to 383 of approximately 1 to 1.5 μm were opened (as shown in FIG. 1C).
次いで、コンタクトホール３８１〜３８３開孔後の基板
（ウェハ）３１を前述した第１図図示の第１のシャッタ
２４１から第１の真空室２３１内の下部平板電極２５ｂ
上にセットした。つづいて、スパッタリング装置の排気
管２９から第１の真空室２３１内のガスを１Ｘ１０−”
ｔｏｒｒまで排気した後、導入管２８からＡｒガスを３
×１０°’ ｔｏｒｒまで真空室２３ｉ内に導入し、更
に高周波′Ｒ源２６ （１３，５６ＭＨｚ）からパワー
２００Ｗの高周波電力を下部平板電極２５ｂに印加し、
同時に電磁石２７から６０ガウスの磁界を与えて平板電
極２５ａ、２５ｂ間でプラズマ電位２００〜２５０■の
マグネトロン放電を行なわせ、コンタクトホール３８１
〜３８３から露出した多結晶シリコンからなるゲート電
極３４表面及びソース、トレイン領域３５．３６表面の
スパッタエツチングを行なった。ひきつづき、スパッタ
エツチング後のウェハ３１を第２のシャッタ２４２から
第２の真空室２３２内の図示しない保持板上にセットし
、排気管（図示せず）から第２の真空室２３２内のガス
を５Ｘ １０−８ｔｏｒｒまで排気した後、導入管（図
示せず）からＡｒとＨ２の混合ガス（混合比８：２）を
２ Ｘ １０’ ｔｏｒｒの条件で真空室２３２内に導
入し、更に高周波電源（１３，５６ＭＨｚ）からパワー
２．５Ｗの高周波電力をシリコンターゲットと平板電極
の間に印加し、更にウェハ３１を２００〜３００℃に加
熱した状態でシリコンのスパッタリングを行なって同図
（ｄ）に示すようにコンタクトホール３８１〜３８３を
含む全面に厚さ４０００人の多結晶シリコン膜３９を堆
積した。この後、真空槽２１の第２の真空室２３２から
ウェハ３１を取出し、ｎ型不純物、例えばリンをイオン
注入を施して該多結晶シリコン膜３９を低抵抗化した。Next, the substrate (wafer) 31 after contact holes 381 to 383 are opened is moved from the first shutter 241 shown in FIG.
set on top. Next, the gas in the first vacuum chamber 231 is pumped 1×10-” from the exhaust pipe 29 of the sputtering device.
After exhausting to torr, Ar gas is introduced from the introduction pipe 28 at 3.
×10°' torr into the vacuum chamber 23i, and furthermore, a high frequency power of 200 W from the high frequency 'R source 26 (13.56 MHz) is applied to the lower flat plate electrode 25b,
At the same time, a magnetic field of 60 Gauss is applied from the electromagnet 27 to cause magnetron discharge with a plasma potential of 200 to 250 cm between the plate electrodes 25a and 25b, and the contact hole 381
Sputter etching was performed on the surface of the gate electrode 34 made of polycrystalline silicon exposed from 383 to 383, and the surfaces of the source and train regions 35 and 36. Subsequently, the wafer 31 after sputter etching is set on a holding plate (not shown) in the second vacuum chamber 232 through the second shutter 242, and the gas in the second vacuum chamber 232 is discharged from the exhaust pipe (not shown). After evacuating to 5X 10-8 torr, a mixed gas of Ar and H2 (mixing ratio 8:2) was introduced into the vacuum chamber 232 at 2X 10' torr from an inlet pipe (not shown), and then a high frequency power supply was applied. (13,56MHz) with a power of 2.5W was applied between the silicon target and the flat electrode, and silicon was sputtered with the wafer 31 heated to 200 to 300°C. As shown, a polycrystalline silicon film 39 having a thickness of 4,000 wafers was deposited over the entire surface including contact holes 381 to 383. Thereafter, the wafer 31 was taken out from the second vacuum chamber 232 of the vacuum chamber 21, and ions of n-type impurities, such as phosphorus, were implanted to lower the resistance of the polycrystalline silicon film 39.
次いで、多結晶シリコン膜３９をフォットエッチング技
術によりパターニングしてコンタクトホール３８１〜３
８３を通してゲートＩｒ極３４及びｎ＋型のソース、ド
レイン領域３５．３６と夫々接続する多結晶シリコン配
線４０〜４２を形成してｎチャンネルＭＯＳトランジス
タを製造した（同図（ｅ）図示）。Next, the polycrystalline silicon film 39 is patterned using a photo-etching technique to form contact holes 381 to 3.
Polycrystalline silicon wirings 40 to 42 were formed to connect to the gate Ir electrode 34 and the n+ type source and drain regions 35 and 36, respectively, through the polycrystalline silicon wires 83, thereby manufacturing an n-channel MOS transistor (as shown in FIG. 3(e)).
しかして、本発明方法によればシリコン基板３１上にゲ
ート電極３４を形成し、同基板表面にソース、ドレイン
領域３５．３６を形成し、更に全面にＣＶＤ−８ｉ０２
膜３７の堆積、コンタクトホール３８１〜３８３の開孔
を行なった後、第１図図示のスパッタリング装置の真空
槽２１（第１の真空室２３１）内でコンタクトホール３
８１〜３８３から露出したゲート電極３４、ソース、ド
レイン領域３５．３６の表面の酸化膜等をスパッタエツ
チングにより除去して清浄化する。ひきつづき、大気中
に取出すことなく、同一の真空槽２１（第２の真空室２
３２）内でシリコンのスパッタリングを行なってコンタ
クトホール３８１〜３８３を含む全面に多結晶シリコン
躾３９を堆積する。従って、該多結晶シリコン１１３９
をバターニングすることによって、多結晶シリコンから
なる配置１１４０と多結晶シリコンからなるゲート電極
３４の問、及び配線４１．４２とＩＩ型のソース、ドレ
イン領域３５．３６との間のコンタクト部（コンタクト
ホール３８１〜３８！底部）に酸化膜が存在しないため
、シリコン同志の接続である配線４０〜４２とゲート電
極３４、ソース、ドレイン領域３５．３６との闇を低抵
抗で接続できる。According to the method of the present invention, a gate electrode 34 is formed on a silicon substrate 31, source and drain regions 35 and 36 are formed on the surface of the same substrate, and further CVD-8i02 is formed on the entire surface.
After depositing the film 37 and opening the contact holes 381 to 383, the contact holes 3 are opened in the vacuum chamber 21 (first vacuum chamber 231) of the sputtering apparatus shown in FIG.
The oxide film and the like on the surfaces of the gate electrode 34, source and drain regions 35 and 36 exposed from 81 to 383 are removed and cleaned by sputter etching. Subsequently, the same vacuum chamber 21 (second vacuum chamber 2
32) to deposit polycrystalline silicon 39 over the entire surface including contact holes 381 to 383 by sputtering silicon. Therefore, the polycrystalline silicon 1139
By patterning, contact areas (contacts) between the arrangement 1140 made of polycrystalline silicon and the gate electrode 34 made of polycrystalline silicon, and between the wiring 41.42 and the type II source and drain regions 35.36 are formed. Since there is no oxide film in the holes 381 to 38 (bottoms), the wirings 40 to 42, which are connections between silicones, and the gate electrode 34 and the source and drain regions 35 and 36 can be connected with low resistance.
また、、スパッタエツチングによるコンタクトホール３
８１〜３８３底部の清浄化に際して、マグネトロン放電
によりプラズマ電位を２００〜２５０ｖと低電位にする
ことによって、エツチング速度の低下を招かず、しかも
露出したゲート電極３４やソース、ドレイン領域３５．
３６表面にダメージを発生させることなく、酸化膜等の
除去が可能となる。従って、プラズマ電位を高くした状
態でスパッタエツチングして清浄化した場合に比べて、
多結晶シリコンからなる配線４０〜４２とシリコンから
なるゲート電１１３４、ソース、ドレイン領域３５．３
６との閣のコンタクト抵抗をより一層低減でき良好な接
続が可能となる。事実、多結晶シリコンからなるゲート
電極と多結晶シリコンからなる配線との間のコンタクト
抵抗を測定したところ、従来方法では数にΩ〜敗ＭΩで
ありたのに対し、本実施例の場合では２０〜３ｏΩと著
しく減少していることが確認された。なお、こうしたス
パッタエツチング時のプラズマ電位の上限は、多結晶シ
リコンからなるゲート電極等へのダメージ発生を抑制乃
至防止する観点から３００■とすることが望ましい。In addition, contact hole 3 is formed by sputter etching.
When cleaning the bottom portions of the gate electrodes 34 and 81 to 383, the plasma potential is reduced to a low potential of 200 to 250 V by magnetron discharge, thereby preventing a decrease in the etching rate and cleaning the exposed gate electrode 34, source, and drain regions 35.
The oxide film etc. can be removed without causing damage to the 36 surface. Therefore, compared to cleaning by sputter etching with a high plasma potential,
Wiring lines 40 to 42 made of polycrystalline silicon, gate electrode 1134 made of silicon, source and drain regions 35.3
It is possible to further reduce the contact resistance with 6 and achieve a good connection. In fact, when we measured the contact resistance between the gate electrode made of polycrystalline silicon and the wiring made of polycrystalline silicon, it was found to be in the range of several Ω to MΩ in the conventional method, but in the case of this example it was 20 MΩ. It was confirmed that the resistance was significantly reduced to ~3oΩ. Incidentally, the upper limit of the plasma potential during such sputter etching is desirably 300 cm from the viewpoint of suppressing or preventing damage to the gate electrode etc. made of polycrystalline silicon.
更に、シリコンのスパッタリングに際して、イオン種と
してＡｒとＨ２どの混合ガスを使用することによって、
結晶性が改善された膜質の良好な多結晶シリコン膜を堆
積でき、ひいては高精度のバターニングが可能となると
共に、抵抗値が均一な配線形成が可能となる。この場合
、ＡｒとＨ２との混合割合はＡｒ：Ｈ２−９：１〜７：
３の範囲とすることが望ましい。Furthermore, when sputtering silicon, by using a mixed gas such as Ar and H2 as ion species,
A polycrystalline silicon film with improved crystallinity and good film quality can be deposited, which in turn enables highly accurate patterning and the formation of interconnects with uniform resistance values. In this case, the mixing ratio of Ar and H2 is Ar:H2-9:1-7:
It is desirable to set it in the range of 3.
なお、上記実施例ではｎチャンネルＭＯＳトランジスタ
の製造に適用した例について説明したが、ｎチャンネル
ＭＯＳトランジスタ、相補型ＭＯＳトランジスタ、バイ
ポーラトランジスタ等にも同様に適用できる。また、第
１１１多結晶シリコン配線とコンタクトホールを通して
第２層多結晶シリコン配線を接続する多層配線構造のも
のにも同様に適用できる。In the above embodiment, an example in which the present invention is applied to the manufacture of an n-channel MOS transistor has been described, but the present invention can be similarly applied to an n-channel MOS transistor, a complementary MOS transistor, a bipolar transistor, etc. Further, the present invention can be similarly applied to a multilayer wiring structure in which the 111th polycrystalline silicon wiring is connected to the second layer polycrystalline silicon wiring through the contact hole.
以上詳述した如く、本発明によればシリコン基板表面の
拡散層や多結晶シリコン電極等のシリコンからなる導電
層と多結晶シリコン配線とを微細なコンタクトホールを
通して接続した場合でも低抵抗のコンタクトが実現でき
る高信頼性、＾集積度の半導体装置の製造方法を提供で
きる。As detailed above, according to the present invention, even when a conductive layer made of silicon such as a diffusion layer on the surface of a silicon substrate or a polycrystalline silicon electrode is connected to a polycrystalline silicon wiring through a fine contact hole, a contact with low resistance can be achieved. It is possible to provide a method for manufacturing a semiconductor device with high reliability and high degree of integration.
第１図は本実施例で用いたスパッタリング装置の概略図
、第２図（ａ）〜（ｅ）は本発明の実施例、におけるｎ
チャンネルＭＯＳトランジスタの製造工程を示す断面図
、第３図（ａ）〜（Ｃ）は従来のｎチャンネルＭＯＳト
ランジスタの製造工程を示す断面図である。
２１・・・真空槽、２３１．２３２−真空室、２５ａ、
２５ｂ−・・平板電極、２７−・・電磁石、２９−・・
排気管、３１・・・ｐ型シリコン基板、３２−・・フィ
ールド酸化膜、３４、多結晶シリコンからなるゲート電
極、３５・・・ｎゝ型ソース、領域°、３６・・・ｎ＋
型トドレイン領域３７−ＣＶＤ−８ｉ ０２ ＩＩ、３
８１〜３８３・・・コンタクトホール、４０〜４２・・
・多結晶シリコン配線。
第１図
第２図
（ａ）
（Ｃ）
第２図
（ｄ）
・２
（ｅ）
第３図
（ａ）
（ｂ）
（Ｃ）Figure 1 is a schematic diagram of the sputtering apparatus used in this example, and Figures 2 (a) to (e) are examples of the present invention.
3(a) to 3(C) are cross-sectional views showing the manufacturing process of a conventional n-channel MOS transistor. 21... Vacuum chamber, 231.232-Vacuum chamber, 25a,
25b--Flat electrode, 27--Electromagnet, 29--
Exhaust pipe, 31...p-type silicon substrate, 32-...field oxide film, 34, gate electrode made of polycrystalline silicon, 35...n-type source, region °, 36...n+
Type drain region 37-CVD-8i 02 II, 3
81-383...Contact hole, 40-42...
・Polycrystalline silicon wiring. Figure 1 Figure 2 (a) (C) Figure 2 (d) ・2 (e) Figure 3 (a) (b) (C)
Claims (3)
程と、この絶縁膜に前記導電層表面に達するコンタクト
ホールを選択的に開孔する工程と、前記コンタクトホー
ルから露出するシリコンの導電層を、真空槽内でのスパ
ッタエッチングにより清浄化処理を行なつた後、同一の
真空槽内でシリコンのスパッタリングを行なつてシリコ
ン膜を堆積する工程とを具備したことを特徴とする半導
体装置の製造方法。(1) A step of forming an insulating film on a conductive layer made of silicon, a step of selectively opening a contact hole in this insulating film reaching the surface of the conductive layer, and a step of forming a conductive layer of silicon exposed from the contact hole. A semiconductor device characterized by comprising the steps of performing a cleaning treatment by sputter etching in a vacuum chamber, and then depositing a silicon film by sputtering silicon in the same vacuum chamber. Production method.
を、真空槽内でスパッタエッチングするに際し、照射イ
オンの電位を３００Ｖ以下に設定することを特徴とする
特許請求の範囲第１項記載の半導体装置の製造方法。(2) The semiconductor device according to claim 1, wherein the potential of irradiated ions is set to 300 V or less when sputter etching the silicon conductive layer exposed from the contact hole in a vacuum chamber. Production method.
マ中で行なうことを特徴とする特許請求の範囲第１項又
は第２項記載の半導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that silicon sputtering is performed in Ar/H_2 plasma.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27113284A JPS61148880A (en) | 1984-12-22 | 1984-12-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27113284A JPS61148880A (en) | 1984-12-22 | 1984-12-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61148880A true JPS61148880A (en) | 1986-07-07 |
Family
ID=17495764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27113284A Pending JPS61148880A (en) | 1984-12-22 | 1984-12-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61148880A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58200533A (en) * | 1982-04-30 | 1983-11-22 | テキサス・インスツルメンツ・インコ−ポレイテツド | Method of attaching metal layer to surface of insulating layer |
| JPS59100522A (en) * | 1982-11-30 | 1984-06-09 | Kokusai Electric Co Ltd | Automatically sputtering device for formation of thin film |
-
1984
- 1984-12-22 JP JP27113284A patent/JPS61148880A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58200533A (en) * | 1982-04-30 | 1983-11-22 | テキサス・インスツルメンツ・インコ−ポレイテツド | Method of attaching metal layer to surface of insulating layer |
| JPS59100522A (en) * | 1982-11-30 | 1984-06-09 | Kokusai Electric Co Ltd | Automatically sputtering device for formation of thin film |
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