JPS6114671B2 - - Google Patents
Info
- Publication number
- JPS6114671B2 JPS6114671B2 JP8484577A JP8484577A JPS6114671B2 JP S6114671 B2 JPS6114671 B2 JP S6114671B2 JP 8484577 A JP8484577 A JP 8484577A JP 8484577 A JP8484577 A JP 8484577A JP S6114671 B2 JPS6114671 B2 JP S6114671B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- metal plate
- layer
- electrode
- bonding wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 15
- 239000003990 capacitor Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 description 20
- 239000002184 metal Substances 0.000 description 20
- 238000001465 metallisation Methods 0.000 description 12
- 239000000758 substrate Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 238000005219 brazing Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 230000002500 effect on skin Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000011796 hollow space material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
Landscapes
- Microwave Amplifiers (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】
本発明は高周波高出力トランジスタ、特に、入
力側の容器内部に整合回路を設け外部回路による
インピーダンス整合を行いやすくしてある高周波
高出力トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-frequency, high-output transistor, and particularly to a high-frequency, high-output transistor in which a matching circuit is provided inside a container on the input side to facilitate impedance matching by an external circuit.
従来高周波高出力トランジスタは高出力化に伴
い入力インピーダンスが極めて低くなり整合の際
のインピーダンス変換損失などが増大しチツプ固
有の出力を得ることは非常に困難であつた。これ
を解決するために入力側容器内部に整合回路を設
けチツプのインピーダンスを容器の入力側のイン
ピーダンスを含めてトランジスタ外部から測定し
た場合適当な抵抗成分のインピーダンスに変換す
る方法がとられるようになつた。第１図はエミツ
タ接地形において、上記の目的で、従来方法によ
つて内部整合回路を構成した高周波高出力トラン
ジスタを示している。即ち絶縁基板１上にコレク
タ用金属化層２、ベース用金属化層３およびエミ
ツタ用金属化層４が互いに絶縁されて形成され、
各々にコレクタ電極用金属板５、ベース電極用金
属板６およびエミツタ電極用金属板７がロー付け
によつて固着され、接地インダクタンスを減少さ
せるためにコレクタ用金属化層２の上方にこれと
間隔を保つて接地用金属板８が形成されてい
る。。トランジスタチツプ９はコレクタ用金属化
層２上に電気的機械的に連結され、ボンデイング
線１０によつてトランジスタチツプのエミツタ電
極１１と接地用金属板８とが電気的に接続されて
いる。一方エミツタ用金属化層４上には薄膜コン
デンサ１２が形成されておりトランジスタチツプ
９のベース電極１３はボンデイング線１４を通し
てこのコンデンサ１２に電気的に接続され、さら
にこのコンデンサ１２はボンデイング線１５によ
つてベース用金属化層３と電気的に接続されてい
る。このようにして、コンデンサ１２のキヤパシ
タンスとボンデイング線１４及び１５の各インダ
クタンスとによつて内部インピーダンス変換回路
を構成しトランジスタの入力インピーダンスが使
用周波数において純抵抗として作用するようにさ
れている。第２図はその等価回路でありトランジ
スタチツプ９のインピーダンスをZin、コンデン
サ１２のキヤパシタンスをＣ、ボンデイング線１
４及び１５のインダクタンスをそれぞれLb1およ
びLb2で示してある。しかるに例えば400MHz程度
の周波数において非常に低い入力インピーダンス
を上記構成によつて適当な高インピーダンスに変
換するような場合Lb1は非常に大きな値が必要と
なる場合がほとんどであるがそのような場合はボ
ンデイング線１４の長さを非常に長くするかその
並列数を少くしなければならない。このためにボ
ンデイング線１４の抵抗分による入力電力の損失
が増大し外部整合回路とのインピーダンス整合に
おける変換損失は小さくできるようになつたが結
果的に電力利得を改善できない場合が多かつた。
さらにボンデイング線１４相互間の相互インダク
タンスやボンデイング線１４と接地用金属化層４
とのキヤパシタンスなどは、ボンデイング線の長
さを長くした場合はその空間的配置がバラツキや
すいために非常にバラツキやすくトランジスタ内
部のインピーダンスにバラツキを生じさせて動作
の安定性を欠いたりトランジスタそのものも繰り
返し製造する場合同一の特性を得ることが比較的
困難であつた。 Conventional high-frequency, high-output transistors have extremely low input impedance as the output increases, and impedance conversion losses during matching increase, making it extremely difficult to obtain a chip-specific output. To solve this problem, a method has been adopted in which a matching circuit is installed inside the input-side container, and when the impedance of the chip, including the impedance on the input side of the container, is measured from outside the transistor, it is converted into the impedance of an appropriate resistance component. Ta. FIG. 1 shows a high-frequency, high-output transistor in an emitter-grounded configuration in which an internal matching circuit is constructed by a conventional method for the above purpose. That is, a collector metallized layer 2, a base metallized layer 3, and an emitter metallized layer 4 are formed on an insulating substrate 1 so as to be insulated from each other.
A metal plate 5 for the collector electrode, a metal plate 6 for the base electrode, and a metal plate 7 for the emitter electrode are fixed to each by brazing, and are spaced above the metallized layer 2 for the collector in order to reduce the grounding inductance. A grounding metal plate 8 is formed to maintain the same. . The transistor chip 9 is electrically and mechanically connected on the collector metallization layer 2, and the emitter electrode 11 of the transistor chip and the ground metal plate 8 are electrically connected by a bonding line 10. On the other hand, a thin film capacitor 12 is formed on the emitter metallization layer 4, and the base electrode 13 of the transistor chip 9 is electrically connected to this capacitor 12 through a bonding wire 14, and furthermore, this capacitor 12 is connected through a bonding wire 15. It is electrically connected to the base metallization layer 3. In this way, the capacitance of the capacitor 12 and the inductance of the bonding lines 14 and 15 constitute an internal impedance conversion circuit, so that the input impedance of the transistor acts as a pure resistance at the operating frequency. Figure 2 shows its equivalent circuit, where the impedance of the transistor chip 9 is Zin, the capacitance of the capacitor 12 is C, and the bonding wire 1 is
The inductances of 4 and 15 are designated Lb 1 and Lb 2 , respectively. However, for example, when converting a very low input impedance to a suitably high impedance at a frequency of about 400 MHz using the above configuration, Lb 1 will most likely require a very large value. It is necessary to make the length of the bonding wire 14 very long or to reduce the number of bonding wires in parallel. For this reason, the loss of input power due to the resistance of the bonding wire 14 increases, and although it has become possible to reduce the conversion loss in impedance matching with an external matching circuit, it is often impossible to improve the power gain as a result.
Furthermore, there is a mutual inductance between the bonding wires 14 and the grounding metallization layer 4.
When the length of the bonding wire is increased, the capacitance between the bonding wire and the capacitance of the bonding wire tends to fluctuate due to the spatial arrangement of the wires. It has been relatively difficult to obtain the same properties when manufacturing.
本発明はこのような従来の入力側整合回路の欠
点を軽減し高周波大電力で高い利得が得られる整
合回路を有する高周波高出力トランジスタを提供
することを目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to provide a high-frequency, high-output transistor having a matching circuit that can alleviate the drawbacks of the conventional input-side matching circuit and obtain high gain with high frequency and high power.
以下実施例に従い図面を参照して本発明を詳細
に説明する。第３図は本発明の高周波高出力トラ
ンジスタの一実施例の主要部の斜視図でエミツタ
接地形の場合を示す。絶縁基板１上にコレクタ用
金属化層２、ベース用金属化層３およびエミツタ
用金属化層４が互いに絶縁されて形成されコレク
タ用金属化層３とエミツタ用金属化層４の各々に
コレクタ電極用金属板５およびエミツタ電極用金
属板７がロー付けによつて固着され、同時にベー
ス電極用金属板６が、その一部がエミツタ金属化
層４上にこれとあある間隔を保つてコレクタ用金
属化層２側に延在するようにベース金属化層３上
に固着される。コレクタ用金属化層２上にはトラ
ンジスタチツプ９が機械的電気的に固着されチツ
プ９のベース電極１３はボンデイング線１６によ
つてベース電極用金属板６に接続される。さらに
ベース電極用金属板６上に薄膜コンデンサ１２が
形成されこのコンデンサ１２はボンデイング線１
７によつてエミツタ電極用金属板に接続される。 Hereinafter, the present invention will be described in detail according to examples and with reference to the drawings. FIG. 3 is a perspective view of the main parts of an embodiment of the high-frequency, high-output transistor of the present invention, and shows a case where the emitter is grounded. A collector metallized layer 2, a base metallized layer 3, and an emitter metallized layer 4 are formed on an insulating substrate 1 so as to be insulated from each other, and a collector electrode is formed on each of the collector metallized layer 3 and the emitter metalized layer 4. The metal plate 5 for the emitter electrode and the metal plate 7 for the emitter electrode are fixed together by brazing, and at the same time, the metal plate 6 for the base electrode is placed on the emitter metallized layer 4 with a certain distance therebetween. It is fixed on the base metallization layer 3 in such a way that it extends towards the metallization layer 2 side. A transistor chip 9 is mechanically and electrically fixed on the collector metallization layer 2, and the base electrode 13 of the chip 9 is connected to the base electrode metal plate 6 by a bonding wire 16. Further, a thin film capacitor 12 is formed on the base electrode metal plate 6, and this capacitor 12 is connected to the bonding wire 1.
It is connected to the emitter electrode metal plate by 7.
同一材質で断面が長方形の角柱または板状の導
体と円柱形の導体を作りそのインダクタンスを等
しくした場合表皮効果によるその抵抗分は長方形
の角柱の導体の方が小さくできる。例えば直径30
μｍの金線２本によつてナノヘンリー（以下nH
と記す）のインダクタンスを得ようとする場合実
験によれば金線相互の間隔を30μｍとした場合そ
の長さは2.3mmが必要である。線間の間隔をこれ
より広くした場合はインダクタンスは2nHよりも
小さくなつてしまう。一方幅0.4mm、厚さ0.1mmの
四角柱の導体によつて2nHを得る場合は計算によ
れば3.2mmが必要である。この両者の抵抗分を計
算するとおよそ３：１の割合となる。これから理
解できるように本発明の構成によれば従来法のＬ
b1に相当する。インダクタンス分はボンデイング
線１６とベース電極用金属板６の、ボンデイング
線１６の接着部から薄膜コンデンサ１２の固着部
までの部分によつて形成されるためボンデイング
線１４のみでＬb1を形成する従来の場合に比較し
て、抵抗分を大幅に減少でき、入力電力の損失を
小さく抑えることができ電力利得が大きく改善さ
れる。さらに入力側のボンデイング線１６は必要
最小限の長さにできるためその空間的配置におけ
るバラツキはすくなく特性が安定するばかりでな
く繰り返しの製造に対しても同一の特性が得やす
くなる。 If a prismatic or plate-shaped conductor with a rectangular cross section and a cylindrical conductor are made of the same material and their inductances are made equal, the resistance due to the skin effect can be smaller in the rectangular prismatic conductor. For example, diameter 30
NanoHenry (nH) is made by two μm gold wires.
According to experiments, if the distance between the gold wires is 30 μm, the length of the gold wires must be 2.3 mm. If the distance between the lines is wider than this, the inductance will be smaller than 2nH. On the other hand, when obtaining 2nH using a rectangular prism conductor with a width of 0.4mm and a thickness of 0.1mm, 3.2mm is required according to calculations. Calculating the resistance between the two leads to a ratio of approximately 3:1. As can be understood from this, according to the configuration of the present invention, L of the conventional method is
Corresponds to b1 . The inductance component is formed by the bonding wire 16 and the portion of the base electrode metal plate 6 from the bonding part of the bonding wire 16 to the fixed part of the thin film capacitor 12. Compared to the conventional case, the resistance component can be significantly reduced, input power loss can be suppressed, and power gain can be greatly improved. Further, since the bonding wire 16 on the input side can be made to have the minimum necessary length, there is little variation in its spatial arrangement, and the characteristics are not only stable, but also the same characteristics can be easily obtained even in repeated manufacturing.
なお本実施例はエミツタ接地形の場合であるが
ベース接地形の場合にも同様の効果があることは
いうまでもない。又、本実施例は入力電極用金属
板６の一部を絶縁基材１から離して中空に保持し
そのインダクタンスを利用した場合であるが、第
４図に、示すように他の絶縁物１８によつて入力
用金属化層３の一部を接地用金属化層４から離し
て中空に保持してもよい。この場合、図面には示
されていないが、トランジスタチツプ９と入力用
金属化層３、さらにコンデンサ１２と接地用金属
化層４とはボンデイング線によつてそれぞれ接続
されている。さらに第５図および第６図に示すよ
うに入力電極用金属板６又は入力用金属化層３が
中空に保接されている部分がなく全部が絶縁基板
１の表面上に形成されている場合や接地用金属化
層４上の絶縁物１８上に形成されている場合に
は、絶縁物１又は１８と金属化層３との接着面に
はモリブデン等の比較的抵抗率の大きな金属が使
用されているために、電力損失は大きくなるけれ
どもボンデイング線１６の空間的配置のバラツキ
による特性不安定性又は均一性は改善されるし量
産性はよいので場合により非常に効果的な構造で
ある。 Although this embodiment deals with the emitter grounding surface, it goes without saying that the same effect can be obtained in the case of the base grounding surface. Further, in this embodiment, a part of the input electrode metal plate 6 is held in a hollow space apart from the insulating base material 1, and its inductance is utilized, but as shown in FIG. A part of the input metallization layer 3 may be kept hollow and separated from the ground metallization layer 4 by the above-mentioned method. In this case, although not shown in the drawings, the transistor chip 9 and the input metallization layer 3 as well as the capacitor 12 and the ground metallization layer 4 are connected by bonding lines, respectively. Furthermore, as shown in FIGS. 5 and 6, when the input electrode metal plate 6 or the input metallized layer 3 is formed entirely on the surface of the insulating substrate 1 without any hollow and hermetically connected parts. or on the insulator 18 on the grounding metallized layer 4, a metal with relatively high resistivity such as molybdenum is used for the bonding surface between the insulator 1 or 18 and the metallized layer 3. Although the power loss is increased because of this structure, characteristic instability or uniformity due to variations in the spatial arrangement of the bonding wires 16 is improved, and mass production is good, so it is a very effective structure in some cases.
以上のように本発明によれば、入力用導体層と
トランジスタチツプの入力電極をボンデイング線
１６、入力用金属化層３又は入力用金属板のよう
な接続部材により直接接続しかつ入力用導体層と
接地用導体層の間にコンデンサを導入することに
より、高周波高出力トランジスタの入力側整合回
路の均一性ないし電力損失の改善を大幅に達成す
ることができる。 As described above, according to the present invention, the input conductor layer and the input electrode of the transistor chip are directly connected by a connecting member such as the bonding wire 16, the input metallization layer 3, or the input metal plate, and the input conductor layer By introducing a capacitor between the ground conductor layer and the ground conductor layer, it is possible to significantly improve the uniformity and power loss of the input-side matching circuit of the high-frequency, high-output transistor.
第１図は従来の内部整合回路付エミツタ接地形
高周波高出力トランジスタ主要部の平面図、第２
図はその等価回路、第３図は本発明の内部整合回
路付高周波高出力トランジスタの一実施例の主要
部の斜視図、第４図、第５図および第６図は他の
実施例の主断面図である。
１……絶縁基板、２……コレクタ用金属化層、
３……ベース用金属化層、４……エミツタ用金属
化層、５……コレクタ電極用金属板、６……ベー
ス電極用金属板、７……エミツタ電極用金属板、
８……接地用金属板、９……トランジスタチツ
プ、１０……ボンデイング線、１１……トランジ
スタチツプのエミツタ電極、１２……コンデン
サ、１３，１４，１５，１６，１７……ボンデイ
ング線、１８……絶縁物。
Figure 1 is a plan view of the main part of a conventional emitter-grounded high-frequency, high-output transistor with an internal matching circuit;
The figure shows its equivalent circuit, FIG. 3 is a perspective view of the main parts of one embodiment of the high frequency, high output transistor with internal matching circuit of the present invention, and FIGS. 4, 5 and 6 show the main parts of other embodiments. FIG. 1... Insulating substrate, 2... Metalized layer for collector,
3...metalized layer for base, 4...metalized layer for emitter electrode, 5...metal plate for collector electrode, 6...metal plate for base electrode, 7...metal plate for emitter electrode,
8... Grounding metal plate, 9... Transistor chip, 10... Bonding wire, 11... Emitter electrode of transistor chip, 12... Capacitor, 13, 14, 15, 16, 17... Bonding wire, 18... …Insulator.
Claims (1)
が絶縁部材上に形成され、前記出力用導体層にト
ランジスタチツプがとり付けられ、このトランジ
スタチツプの入力電極と前記入力用導体層が接続
部材で接続され、前記入力用導体層にコンデンサ
が取り付けられ、このコンデンサの上部電極は前
記接地用導体層に接続されていることを特徴とす
る高周波高出力トランジスタ。1. An output conductor layer, a ground conductor layer, and an input conductor layer are formed on an insulating member, a transistor chip is attached to the output conductor layer, and the input electrode of this transistor chip and the input conductor layer are connected. A high-frequency, high-output transistor, characterized in that the capacitor is connected to the input conductor layer, and the upper electrode of the capacitor is connected to the ground conductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8484577A JPS5419365A (en) | 1977-07-14 | 1977-07-14 | High frequency high output transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8484577A JPS5419365A (en) | 1977-07-14 | 1977-07-14 | High frequency high output transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5419365A JPS5419365A (en) | 1979-02-14 |
| JPS6114671B2 true JPS6114671B2 (en) | 1986-04-19 |
Family
ID=13842127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8484577A Granted JPS5419365A (en) | 1977-07-14 | 1977-07-14 | High frequency high output transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5419365A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0744514U (en) * | 1993-11-29 | 1995-11-21 | 淀化学工業株式会社 | Egg container made of synthetic resin |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56125131A (en) * | 1980-03-07 | 1981-10-01 | Nec Corp | Digital processing type transceiver for quadrature multiplex signal |
| JPH08319510A (en) * | 1995-05-24 | 1996-12-03 | Shinko Flex:Kk | Desulfurizing agent for steel refining |
-
1977
- 1977-07-14 JP JP8484577A patent/JPS5419365A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0744514U (en) * | 1993-11-29 | 1995-11-21 | 淀化学工業株式会社 | Egg container made of synthetic resin |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5419365A (en) | 1979-02-14 |
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