JPS61145867A - Matrix-type thin film transistor substrate - Google Patents
Matrix-type thin film transistor substrateInfo
- Publication number
- JPS61145867A JPS61145867A JP59267304A JP26730484A JPS61145867A JP S61145867 A JPS61145867 A JP S61145867A JP 59267304 A JP59267304 A JP 59267304A JP 26730484 A JP26730484 A JP 26730484A JP S61145867 A JPS61145867 A JP S61145867A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- wire
- insulating layer
- layer
- matrix
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims description 17
- 239000010409 thin film Substances 0.000 title claims description 10
- 239000010410 layer Substances 0.000 claims description 37
- 239000011159 matrix material Substances 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 4
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 abstract description 9
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 6
- 239000004642 Polyimide Substances 0.000 abstract description 3
- 229920001721 polyimide Polymers 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 230000009977 dual effect Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000004528 spin coating Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 12
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 101100268330 Solanum lycopersicum TFT7 gene Proteins 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 239000005262 ferroelectric liquid crystals (FLCs) Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、例えば液晶等によるマトリクス型薄膜トラン
ジスタ基板、特に薄膜トランジスタ（Ｔｈｉｎ−Ｆｉｌ
ｍ−’ｒｒａｎｓｉｓｔｅｒ ・・・以下ＴＦＴと略記
する。）アレイの配線構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to matrix type thin film transistor substrates such as liquid crystals, particularly thin film transistors (Thin-Film transistors).
m-'rransister...hereinafter abbreviated as TFT. ) relates to the wiring structure of the array.
近年、例えば液晶表示パネルの一方の基板にゲート線（
走査線）及びソース線（信号線）を多数互いに絶縁した
状態で直交させ、これら各ラインの交差点にＴＦＴをス
イッチング素子として配列し、このＴＰＴにより各交差
点毎に設けられた画素電極に信号を与え、その部分の液
晶を選択的に駆動させることにより、テレビ等の画像表
示を行う、フラットパネルディスプレイの開発が進めら
れている。最近では、特にパネルの大面積、高精細化に
伴ないＴＦＴのゲート線、ソース線の引き出し本数が増
加しゲート線とソース線が絶縁層を介して交差する部分
の数が増加している。In recent years, for example, gate lines (
A large number of scanning lines (scanning lines) and source lines (signal lines) are insulated from each other and intersected at right angles, TFTs are arranged as switching elements at the intersections of these lines, and signals are applied to pixel electrodes provided at each intersection using the TPTs. , flat panel displays are being developed that display images on televisions and the like by selectively driving liquid crystals in those areas. In recent years, the number of TFT gate lines and source lines has increased, especially as panels have become larger in area and higher in definition, and the number of portions where gate lines and source lines intersect via insulating layers has increased.
第３図に、従来のマトリクス型液晶表示パネルに用いら
れるＴＦＴ７レイ基板の構成図を示す。FIG. 3 shows a configuration diagram of a TFT7 array substrate used in a conventional matrix type liquid crystal display panel.
１はＴＦＴ側透明絶縁基板、２はゲート線、３は画素電
極、４は半導体層、５はソース線、６はドレイン線であ
る。一方第４図（ａ） 、（ｂ）は、それぞれ第３図に
おけるＡ−Ａ ’及びＢ−Ｂ’断面を示す図であり、８
は、半導体層とソース及びドレイン線とのオーミックコ
ンタクトを得るためのｎ′″層、７は、ゲート絶縁層で
ある。・７のゲート絶縁層は前述のゲート層とソース層
線の線間絶縁層も兼ねている。７の絶縁層としては、例
えばＰ−ＣＶＤ法により形成されるＳｉＮ：Ｈ膜を用い
ることができる。 Ｐ−ＣＶＤ法により形成されるＳｉ
Ｎ：Ｈ膜は低温（〜２５０℃）で形成でき、５ｉ０２等
の他の無機絶縁膜に比べて誘電率が大きい等の特徴があ
り、 ＴＦＴのゲート絶縁層として、広く用いられてい
る。しかし、 Ｐ−ＣＣＤ法により形成されるＳｉＮ：
Ｈ膜は、若干数のピンホール等が避けられず、前述の様
に、大面積、高精細化に伴ないＳｉＮ：ＨＩＩのみでは
ゲート線とソース線の交差点でのショートの危険性が増
大する。ゲート線とソース線の交差点でショートが生ず
ると、パネル上にはライン欠陥として現われ、パネル不
良の原因とな４ていた。1 is a TFT side transparent insulating substrate, 2 is a gate line, 3 is a pixel electrode, 4 is a semiconductor layer, 5 is a source line, and 6 is a drain line. On the other hand, FIGS. 4(a) and 4(b) are views showing the AA' and BB' cross sections in FIG. 3, respectively, and 8
is an n''' layer for obtaining ohmic contact between the semiconductor layer and the source and drain lines, and 7 is a gate insulating layer.The gate insulating layer 7 serves as the line-to-line insulation between the gate layer and source layer lines. As the insulating layer 7, an SiN:H film formed by the P-CVD method can be used, for example.
N:H films can be formed at low temperatures (~250° C.) and have a higher dielectric constant than other inorganic insulating films such as 5i02, and are widely used as gate insulating layers of TFTs. However, SiN formed by the P-CCD method:
The H film inevitably has some pinholes, etc., and as mentioned above, as the area becomes larger and the resolution becomes higher, the risk of short circuits at the intersection of the gate line and the source line increases with only SiN:HII. . When a short circuit occurs at the intersection of the gate line and the source line, it appears as a line defect on the panel, causing panel failure.
本発明は上記問題点に鑑みなされたもので、ＴＰＴ配線
部（ソース線とゲート線間）での電気的ショートを防止
した薄膜トランジスタ基板を提供することを目的とする
ものである。The present invention has been made in view of the above problems, and an object of the present invention is to provide a thin film transistor substrate that prevents electrical short-circuits in the TPT wiring portion (between the source line and the gate line).
〔問題点を解決するための手段及び作用〕本発明は、マ
トリクス状に配置された画素と、該画素を駆動する為の
スイッチング用薄膜トランジスタを備え、該薄膜トラン
ジスタのソース線とゲート線間の絶縁層の一部に、ゲー
ト絶縁層に加え、感光性有機絶縁層を設け、二層の層間
絶縁層としたもので、この様な基板構成をすることによ
って、ゲート線とソース線の交差点におけるショートは
減少する。[Means and effects for solving the problems] The present invention includes pixels arranged in a matrix and a switching thin film transistor for driving the pixels, and an insulating layer between the source line and gate line of the thin film transistor. In addition to the gate insulating layer, a photosensitive organic insulating layer is provided on a part of the board, creating a two-layer interlayer insulating layer. By configuring the substrate in this way, short circuits at the intersection of the gate line and source line can be prevented. Decrease.
第１図（ａ）、（ｂ）は、本発明の一実施例を示す断面
図であり、第４図（ａ）、（ｂ）と対応している。第１
図において、９が新たに、ソース線下にゲート線とソー
ス線間のショート防止の為に設けた感光性有機絶縁膜で
ある。FIGS. 1(a) and 1(b) are cross-sectional views showing one embodiment of the present invention, and correspond to FIGS. 4(a) and (b). 1st
In the figure, 9 is a photosensitive organic insulating film newly provided under the source line to prevent short circuit between the gate line and the source line.
第２図に、下ゲートスタガー型ＴＦＴを一例として、そ
の作成プロセスを示す。FIG. 2 shows the manufacturing process of a lower gate stagger type TFT as an example.
第２図（ａ）はゲート線２形成後、無機ゲート絶縁層と
してＳｉＮ：Ｈ膜又半導体層４、ｎ０層８をＰ−ＣＶＤ
法により連続形成し、 ＴＰＴとして動作させる以外の
部分のｎ′″層８、半導体層４をエツチング除去した状
態である。前述したが、従来無機ゲート絶縁層は、 Ｔ
ＰＴのゲート線２と、ソース線５間の層間絶縁層を兼ね
るものである０次に第２図（ｂ）に示す様に、本発明の
感光性有機絶縁層９として感光性ポリイミドであるフォ
トニースυＲ−３１００、（商品名、東し■製）番ＮＭ
Ｐにて、６：４（重量比）に希釈後、約２０００Ａの膜
厚にスピンコードした。８０℃で１時間プリベークした
後、 ＴＦＴのソース線下に残る様、フォト工程にてパ
ターニングした。（第２図（Ｃ））
さらにイソプロピルアルコール（ＩＰＡ）にてリンスし
た後、 １３５℃３０分間、続いて２００℃３０分間キ
ュアレ、木目的の感光性有機絶縁膜９を形成した。（第
２図（ｄ））最後に通常の工程により ＴＰＴのソース
線５、ドレイン線６等を形成し、マトリクス状ＴＦ丁基
板を作成した、（第２図（ｅ））以上の様に、作成され
たマトリクス状ＴＦＴ基板のゲート線とソース線５間の
ショートの発生率を調査したところ、従来の無機絶縁層
（ＳｉＮ：Ｈ膜）のみの場合、全交差点数の０．Ｏ１％
程度生じていたのに対し、本発明の無機絶縁層＋感光性
有機絶縁層の２層の層間絶縁層を設けたマトリクス状Ｔ
ＰＴ基板では、 ｏ、ｏｏｏｉ％以下と、従来の１／１
００以下に大幅に減少した。Figure 2 (a) shows that after the gate line 2 is formed, a SiN:H film or semiconductor layer 4 and n0 layer 8 are formed by P-CVD as an inorganic gate insulating layer.
This is a state in which the n''' layer 8 and the semiconductor layer 4 in the portions other than those to be operated as a TPT are etched away.As mentioned above, the conventional inorganic gate insulating layer is
As shown in FIG. 2(b), the photosensitive organic insulating layer 9 of the present invention, which also serves as an interlayer insulating layer between the gate line 2 and the source line 5 of the PT, is made of photosensitive polyimide. Nice υR-3100, (product name, manufactured by Toshi ■) No. NM
After diluting with P to 6:4 (weight ratio), the film was spin-coded to a film thickness of about 2000 Å. After prebaking at 80° C. for 1 hour, it was patterned using a photo process so that it remained under the source line of the TFT. (FIG. 2(C)) After rinsing with isopropyl alcohol (IPA), the photosensitive organic insulating film 9 was cured at 135° C. for 30 minutes and then at 200° C. for 30 minutes. (Fig. 2 (d)) Finally, TPT source lines 5, drain lines 6, etc. were formed by the usual process to create a matrix-shaped TF substrate. (Fig. 2 (e)) As shown above, When we investigated the incidence of short circuits between the gate line and source line 5 of the fabricated matrix TFT substrate, we found that in the case of only a conventional inorganic insulating layer (SiN:H film), the total number of intersections was 0. O1%
In contrast, the matrix T with two interlayer insulating layers of the inorganic insulating layer and the photosensitive organic insulating layer of the present invention
For PT substrates, it is less than o,oooi%, which is 1/1 of the conventional
It has decreased significantly to below 00.
又、本発明のマトリクス状ＴＦＴ基板を用いて、通常の
工程により、液晶表示パネルを作成した。Further, a liquid crystal display panel was fabricated using the matrix TFT substrate of the present invention through normal processes.
かくして得られた液晶表示パネルを高温多湿雰囲気（８
０℃、８０％ＲＨ）中で１０００時間連続動作させたと
ころ、良好な表示特性を維持した。The thus obtained liquid crystal display panel was placed in a high temperature and humid atmosphere (8
When the device was operated continuously for 1000 hours at 0° C. and 80% RH, good display characteristics were maintained.
感光性有機絶縁膜として、感光性ポリイミドを一例とし
て挙げたが、他にもゴム系フォトレジスト（例えばＯＭ
Ｒ−８３、商品名、東京応化工業■製）等も使用できる
。Although photosensitive polyimide is used as an example of the photosensitive organic insulating film, rubber-based photoresists (such as OM
R-83 (trade name, manufactured by Tokyo Ohka Kogyo ■), etc. can also be used.
また、本発明はクラークらにより発表された強誘電性液
晶素子（米国特許第４３６７８２４号公報）などにも応
用することができる。Further, the present invention can be applied to a ferroelectric liquid crystal device disclosed by Clark et al. (US Pat. No. 4,367,824).
本発明は、ゲート線とソース線間の絶縁層として、ゲー
ト絶縁層に加えソース線下に感光性有機絶縁膜を設け、
一部分二重構造としたのでゲート線とソース線間のショ
ートを大幅に減少させることができたものであって、す
ぐれた効果が認められる。The present invention provides a photosensitive organic insulating film under the source line in addition to the gate insulating layer as an insulating layer between the gate line and the source line,
Since it has a partially double structure, short circuits between the gate line and the source line can be significantly reduced, and an excellent effect can be recognized.
第１図は、本発明のマトリクス状ＴＰＴ基板の一実施例
を示す断面図、第２図は、本発明のマトリクス状ＴＰＴ
基板の作成プロセスの一例を示す断面図、第３図は、従
来のマトリクス状ＴＰＴ基板の一例を示す平面図、第４
図（ａ） （ｂ）はそれぞれ第１図におけるＡ−Ａ ’
及びＢ−Ｂ ’断面図である。
ｌ・・・基板、２・・・ゲート線、３・・・画素電極、
４・・・半導体層、５・・・ソース線、６・・・ドレイ
ン線７・・・ゲート絶縁層、８・・・３０層、９・・・
感光性有機絶縁層、ｌＯ・・・フォトマスク出願者 キ
ャノン株式会社FIG. 1 is a sectional view showing an embodiment of the matrix TPT substrate of the present invention, and FIG. 2 is a cross-sectional view of the matrix TPT substrate of the present invention.
FIG. 3 is a cross-sectional view showing an example of the substrate creation process, and FIG. 4 is a plan view showing an example of a conventional matrix TPT substrate.
Figures (a) and (b) are A-A' in Figure 1, respectively.
and BB' sectional view. 1...Substrate, 2...Gate line, 3...Pixel electrode,
4... Semiconductor layer, 5... Source line, 6... Drain line 7... Gate insulating layer, 8... 30 layers, 9...
Photosensitive organic insulating layer, IO...Photomask applicant Canon Corporation
Claims (1)
のスッチング用薄膜トランジスタを備え、該薄膜トラン
ジスタのソース線とゲート線間の絶縁層の一部にゲート
絶縁層に加えて感光性有機絶縁層を設け、二層の層間絶
縁層としたことを特徴とするマトリクス状薄膜トランジ
スタ基板。It has pixels arranged in a matrix and switching thin film transistors for driving the pixels, and a photosensitive organic insulating layer is provided in addition to the gate insulating layer as part of the insulating layer between the source line and gate line of the thin film transistor. 1. A matrix-like thin film transistor substrate characterized in that the substrate is provided with two interlayer insulating layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59267304A JPS61145867A (en) | 1984-12-20 | 1984-12-20 | Matrix-type thin film transistor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59267304A JPS61145867A (en) | 1984-12-20 | 1984-12-20 | Matrix-type thin film transistor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61145867A true JPS61145867A (en) | 1986-07-03 |
Family
ID=17442966
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59267304A Pending JPS61145867A (en) | 1984-12-20 | 1984-12-20 | Matrix-type thin film transistor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61145867A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6319876A (en) * | 1986-07-11 | 1988-01-27 | Fuji Xerox Co Ltd | Thin film transistor device |
| JPS63131569A (en) * | 1986-11-20 | 1988-06-03 | Fuji Xerox Co Ltd | Semiconductor device |
| JPH01259565A (en) * | 1988-04-11 | 1989-10-17 | Hitachi Ltd | Thin film transistor and manufacture of the same |
| US11125191B2 (en) | 2011-12-06 | 2021-09-21 | Oval Engine Ltd | Engine intake apparatus and method |
-
1984
- 1984-12-20 JP JP59267304A patent/JPS61145867A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6319876A (en) * | 1986-07-11 | 1988-01-27 | Fuji Xerox Co Ltd | Thin film transistor device |
| JPS63131569A (en) * | 1986-11-20 | 1988-06-03 | Fuji Xerox Co Ltd | Semiconductor device |
| JPH01259565A (en) * | 1988-04-11 | 1989-10-17 | Hitachi Ltd | Thin film transistor and manufacture of the same |
| US11125191B2 (en) | 2011-12-06 | 2021-09-21 | Oval Engine Ltd | Engine intake apparatus and method |
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