JPS61140134A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61140134A JPS61140134A JP26171884A JP26171884A JPS61140134A JP S61140134 A JPS61140134 A JP S61140134A JP 26171884 A JP26171884 A JP 26171884A JP 26171884 A JP26171884 A JP 26171884A JP S61140134 A JPS61140134 A JP S61140134A
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact hole
- resist
- layer
- evaporated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims 3
- 239000002184 metal Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims abstract 3
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000004544 sputter deposition Methods 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 238000010420 art technique Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体基板上に微細で深いコンタクトホール
が形成される半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device in which fine and deep contact holes are formed on a semiconductor substrate.
第２図は半導体基板上のコンタクトホール部に金属膜を
形成する従来技術を示す。急峻なテーパーを持つ、コン
タクトホールが形成された半導体基板（第２図（ａ））
上に紅をスパッター法で蒸着する。FIG. 2 shows a conventional technique for forming a metal film in a contact hole portion on a semiconductor substrate. A semiconductor substrate in which a contact hole with a steep taper is formed (Figure 2 (a))
Red is deposited on top by sputtering.
この時、絶縁層の肩部では他の平坦な部分よりもＭは薄
く蒸着される。（第２図（ｂ））次に、レジストを塗布
し、露光工程および現像工程を経て、紅電極を形成すべ
き領域にレジストを残し、ベークを行なう。（第２図（
Ｃ））次に、このレジストをマスクにして、紅のドライ
エツチングまたはウェットエツチングを行なう。（第２
図（ｄ））最後に、レジストを除去して、ＡＡ電極の形
成が完了する。At this time, M is deposited thinner on the shoulder portion of the insulating layer than on other flat portions. (FIG. 2(b)) Next, a resist is applied, and through an exposure process and a development process, the resist is left in the area where the red electrode is to be formed, and baking is performed. (Figure 2 (
C)) Next, using this resist as a mask, red dry etching or wet etching is performed. (Second
Figure (d)) Finally, the resist is removed to complete the formation of the AA electrode.
（第２図（ｅ）） この従来技術では、次に示す欠点がある。(Figure 2(e)) This conventional technique has the following drawbacks.
（１） 絶縁層の肩部では他の平坦な部分よりもＡｔ
が薄く蒸着される。これは、コンタクトホールが微細か
つ深いほど顕著に現われる。(1) At the shoulder part of the insulating layer, At
is deposited thinly. This becomes more noticeable as the contact hole becomes finer and deeper.
この場合、絶縁層肩部でのＡｔの段切れが起きる可能性
がある。In this case, there is a possibility that the At layer may break off at the shoulder portion of the insulating layer.
（２１Ａｔ電極の表面に下地基板の段差分の凹凸が現わ
れる。(Unevenness corresponding to the step difference in the underlying substrate appears on the surface of the 21At electrode.
このＡｔ電極表面の凹凸は、半導体装置の平坦性を悪く
する。This unevenness on the surface of the At electrode deteriorates the flatness of the semiconductor device.
第３図は上記の欠点を改良した従来技術を示す。FIG. 3 shows a prior art technique that improves the above-mentioned drawbacks.
急峻なテーパーを持つコンタクトホールが形成された半
導体基板（第３図（ａ））上＋ｃｈｔをバイアススパッ
ター法で積層する。（第３図（ｂ））この方法では、バ
イアススパッタ時のバイアス電圧を適当な値に設定する
ことにより、Ａｔ堆積膜の表面段差が下地基板の段差よ
りも緩和され、かつ先の従来技術の場合と比べて、絶縁
層肩部でのＡｔ層は厚く蒸着される。したがって、Ａｔ
積層後の工程を先の従来技術の工程と同様にすれば、上
記の欠点が改良されたＡｔ電極が形成される。（第３図
（Ｃ））Ｌかし、バイアススパッター法は通常のスパッ
ター法よりも下地基板に与える損傷が大きく、半導体装
置の特性劣化を起こす。+cht is laminated by bias sputtering on a semiconductor substrate (FIG. 3(a)) in which a contact hole with a steep taper is formed. (Figure 3(b)) In this method, by setting the bias voltage during bias sputtering to an appropriate value, the surface level difference of the At deposited film is made more relaxed than the level difference of the base substrate, and is different from that of the prior art. Compared to the case where the At layer is deposited thicker at the insulating layer shoulder. Therefore, At
If the steps after lamination are carried out in the same manner as those of the prior art, an At electrode with the above-mentioned drawbacks improved can be formed. (FIG. 3(C)) The bias sputtering method causes more damage to the underlying substrate than the normal sputtering method, causing deterioration of the characteristics of the semiconductor device.
本発明は、上述した従来技術の欠点を改良したもので、
微細かつ深いコンタクトホール部で金属電極が平坦に形
成されている半導体装置を提供することを目的とする。The present invention improves the drawbacks of the prior art described above, and
An object of the present invention is to provide a semiconductor device in which a metal electrode is formed flat in a fine and deep contact hole portion.
本発明は、第１金属膜の蒸着と写真蝕刻法と第１金属膜
のエツチングによって、微細かつ深いコンタクトホール
部に第１金属電極を埋め込み、次に、第２金属膜の蒸着
と写真蝕刻法と第２金属膜のエツチングによって、先の
工程で第１金属膜を埋め込んだコンタクトホールの上部
に第２金属膜を形成することにより、凹凸の少ない金属
電極を形成する。In the present invention, a first metal electrode is embedded in a fine and deep contact hole by vapor deposition of a first metal film, photolithography, and etching of the first metal film, and then a second metal film is vaporized and photolithographically etched. By etching the second metal film, the second metal film is formed over the contact hole filled with the first metal film in the previous step, thereby forming a metal electrode with less unevenness.
本発明によって、バイアスバッター法を用いる場合に比
べて、下地基板に与える損傷を少なくして、コンタクト
ホール上に、ホール段差部での金属の段切れを起こさず
、凹凸の少ない金属電極を形成できる。According to the present invention, compared to the case of using a bias batter method, it is possible to form a metal electrode with less unevenness on a contact hole, with less damage to the base substrate, and without causing breakage of the metal at the step part of the hole. .
第１図は本発明の実施例を示す。 FIG. 1 shows an embodiment of the invention.
急峻なテーパーを持つコンタクトホールが形成されてい
る半導体基板（第１図（ａ））上に例えばスパッター法
で紅を蒸着する。（第１図（ｂ））蒸着されるＡｔ層の
厚さはコンタクトホールの段差の大きさと同程度とする
。また、絶縁層であるＳｉｎ、層の肩蔀奢こ蒸着される
Ａ４層の厚さはなるたけ薄くする。Red is deposited by sputtering, for example, on a semiconductor substrate (FIG. 1(a)) in which a steeply tapered contact hole is formed. (FIG. 1(b)) The thickness of the At layer to be deposited is approximately the same as the size of the step of the contact hole. In addition, the thickness of the A4 layer, which is an insulating layer of Sin, and which is deposited on the shoulders of the layer, is made as thin as possible.
次に、ＡＡよりもエツチング速度の大きいＭＯを蒸着す
る。（第１図（Ｃ））次に、レジストを塗布し、露光工
程および現像工程を行ない、レジストパターンを形成し
、ベークを行なう。（第１図（ｄ））このレジストをマ
スクにして、 Ｍｏおよび虹のウェットエツチングを行
ない、８ｉ０．層の肩部の、Ｕ層の薄いところで、Ｍの
ウェットエツチングを止める。Next, MO, which has a higher etching rate than AA, is deposited. (FIG. 1(C)) Next, a resist is applied, an exposure process and a development process are performed to form a resist pattern, and baking is performed. (FIG. 1(d)) Using this resist as a mask, Mo and rainbow wet etching were performed to form 8i0. Stop the wet etching of M at the shoulder of the layer, where the U layer is thin.
（第１図（ｅ））次にレジスト除去し、Ａｔ上に残存す
るＭｏをエツチングして除去する。（第１図（ｆ））次
に、再びＭを蒸着し、レジストを塗布し、露光工程およ
び現像工程を行ない、レジストパターンを形成した後ベ
ークを行なう。（第１図（ｇ））次に、このレジストを
マスクにして、紅のドライあるいはウェットエツチング
を行ない、その後レジストを除去するう（第１図（ｈ）
）
本発明は多層配線間のコンタクトホール番こ適用する事
もでき、又、第１図（ｅ）〜（ｇ）の工程でＭｏ層４を
残したままＭ層７を被着しても勿論よい。(FIG. 1(e)) Next, the resist is removed, and the Mo remaining on the At is etched and removed. (FIG. 1(f)) Next, M is vapor-deposited again, a resist is applied, an exposure process and a development process are performed, a resist pattern is formed, and then baking is performed. (Fig. 1 (g)) Next, using this resist as a mask, red dry or wet etching is performed, and then the resist is removed (Fig. 1 (h)).
) The present invention can also be applied to contact holes between multilayer interconnections, and of course can be applied to cover the M layer 7 while leaving the Mo layer 4 in the steps shown in FIGS. 1(e) to (g). good.
４、 発明の詳細な説明
第１図（ａ）〜（ｈ）は、本発明の一実施例を説明する
ための工程を示す断面図、第２図（ａ）〜（ｅ）は、従
来技術を説明するための工程断面図、第３図（ａ）〜（
Ｃ）は、紅蒸着にバイアススパッター法を用いた従来技
術を説明するための工程断面図である。4. Detailed description of the invention FIGS. 1(a) to (h) are cross-sectional views showing steps for explaining one embodiment of the present invention, and FIGS. 2(a) to (e) are sectional views of the prior art Process cross-sectional diagrams for explaining the process, Figures 3(a) to (
C) is a process cross-sectional view for explaining a conventional technique using a bias sputtering method for red vapor deposition.
図において、
１．１０．１５・・・半導体基板、２，１１．１６・・
・絶縁層、３・・・第１ＡＬ層、４・・・ＭＯ層、５，
８゜１３・・・レジスト層、６・・・第１ＡＬ電極、７
・・・第２ＡＬ層、９・・・第２ＡＬ電極、１２．１７
・・・Ｍ層、１４゜１８・・−Ａｔ電極。In the figure, 1.10.15...semiconductor substrate, 2,11.16...
- Insulating layer, 3... First AL layer, 4... MO layer, 5,
8゜13...Resist layer, 6...First AL electrode, 7
...Second AL layer, 9...Second AL electrode, 12.17
...M layer, 14°18...-At electrode.
代理人 弁理士 則 近 憲 佑（他１名）第１図 第２図Agent: Patent attorney: Kensuke Chika (and 1 other person) Figure 1 Figure 2
Claims (1)
膜を設け、この絶縁膜にコンタクトホールを開けて金属
膜を被着する半導体装置の製造方法において、予め前記
金属膜被着前にコンタクトホールを覆って金属蒸着膜、
この金属蒸着膜よりエッチング速度の大きい材料膜をこ
の順に積層し、更にコンタクトホール上にマスクを設け
、このマスクを用いて前記絶縁膜上の積層膜をコンタク
トホール肩部の金属蒸着膜の薄い箇所を境にエッチング
除去することによりコンタクトホールに前記金属蒸着膜
又は前記金属蒸着膜とこの金属蒸着膜よりエッチング速
度の大きい材料膜との積層膜を埋め込む様にした事を特
徴とする半導体装置の製造方法。In a method for manufacturing a semiconductor device in which an insulating film is provided on the surface of a semiconductor substrate or a surface of a conductive film on this substrate, a contact hole is formed in the insulating film, and a metal film is deposited. metal evaporated film, covering
A material film having a higher etching rate than the metal vapor deposited film is laminated in this order, a mask is provided over the contact hole, and the laminated film on the insulating film is removed using the mask at the thin part of the metal vapor deposition film at the shoulder of the contact hole. Manufacturing a semiconductor device, characterized in that the contact hole is filled with the metal vapor deposited film or a laminated film of the metal vapor deposit film and a material film having a higher etching rate than the metal vapor deposit film by etching away at the border. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26171884A JPS61140134A (en) | 1984-12-13 | 1984-12-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26171884A JPS61140134A (en) | 1984-12-13 | 1984-12-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61140134A true JPS61140134A (en) | 1986-06-27 |
Family
ID=17365740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26171884A Pending JPS61140134A (en) | 1984-12-13 | 1984-12-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61140134A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5187119A (en) * | 1991-02-11 | 1993-02-16 | The Boeing Company | Multichip module and integrated circuit substrates having planarized patterned surfaces |
-
1984
- 1984-12-13 JP JP26171884A patent/JPS61140134A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5187119A (en) * | 1991-02-11 | 1993-02-16 | The Boeing Company | Multichip module and integrated circuit substrates having planarized patterned surfaces |
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