JPS61139854A - 2-port ram system - Google Patents

2-port ram system

Info

Publication number
JPS61139854A
JPS61139854A JP26326484A JP26326484A JPS61139854A JP S61139854 A JPS61139854 A JP S61139854A JP 26326484 A JP26326484 A JP 26326484A JP 26326484 A JP26326484 A JP 26326484A JP S61139854 A JPS61139854 A JP S61139854A
Authority
JP
Japan
Prior art keywords
port ram
main cpu
ram
data
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26326484A
Other languages
Japanese (ja)
Inventor
Kenji Hara
憲二 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yaskawa Electric Corp
Original Assignee
Yaskawa Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yaskawa Electric Manufacturing Co Ltd filed Critical Yaskawa Electric Manufacturing Co Ltd
Priority to JP26326484A priority Critical patent/JPS61139854A/en
Publication of JPS61139854A publication Critical patent/JPS61139854A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate the need for data transfer by a main CPU by giving a 2-port RAM the same addresses with a work RAM as specific addresses and using the area an an area dedicated to the writing of the main CPU. CONSTITUTION:A signal DT/R is a write/read signal, which indicates writing when at 'H' and reading when at 'L'. When the main CPU is to write data in addresses E6000-E7FFF (i.e. high-order address 1110011) of the work RAM, the select signal Sb of the 2-port RAM is also sent through the operation of newly added NAND gates 7 and 8 and an OR gate 9 through with the select signal Sa of the work RAM. Consequently, this data is written in the 2-port RAM simultaneously. A sub CPU only reads the data out of the 2-port RAM and the main CPU need not perform processing at all.

Description

【発明の詳細な説明】 〔産業上の利用分野Ｊ 本発明は、メインＣＰＵが操作を行わずにデータ転送が
可能な２ボー）　ＲＡＭシステムに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field J] The present invention relates to a 2-baud RAM system that is capable of data transfer without any operation by the main CPU.

〔従来の技術〕[Conventional technology]

第２図は、数値制御装置等において、現在頃等のデータ
をＣＲＴ表示装置等に表示するマルチＣＰＵシステムの
概念図である。FIG. 2 is a conceptual diagram of a multi-CPU system that displays current data on a CRT display device or the like in a numerical control device or the like.

すなわち、メイｙＣＰＵＩは「現在値」　「指令値」を
ワークＲＡＭ２のデータとして保有し、表示用のサブＣ
ＰＵ４から、２ポートＲＡＭ３を介してデータの要求が
あると、ワークＬＬＡＭ２のデータを２ポートＲＡＭ３
に転送するシステムである。In other words, the Mayy CPUI retains the "current value" and "command value" as data in work RAM 2, and displays them in the sub-CPU.
When there is a request for data from PU4 via 2-port RAM3, the data of work LLAM2 is transferred to 2-port RAM3.
This is a system that transfers information to

この従来システムのチャンネルデコーダは、例えば第３
図に示すよう１乙所定アドレスごとにセ　　。The channel decoder of this conventional system is, for example, a third channel decoder.
As shown in the figure, 1B is set for each predetermined address.

レフトされるＲＡＭが異なる。この例では、デコーダ５
（Ｌ、５Ｉ３Ｂ）とナントゲート６で構成しており、ア
ドレス信号ＡＩｌ〜Ａ＋３が’１１１００目″のときは
Ｙ３出力がＬ′となりワークＲＡＭがセレクトされ、同
じ＜　’＋１１０１１０−のときはＹ６出力がＬ′とな
り２ポートＲＡＭがセレクトされる。The left RAM is different. In this example, decoder 5
(L, 5I3B) and a Nant gate 6, when the address signal AIl~A+3 is '11100th', the Y3 output becomes L' and the work RAM is selected, and when the same <'+110110-, the Y6 output becomes L', and the 2-port RAM is selected.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところが、このような従来例では、データの転送はメイ
ンＣＰＵの１担となり、負荷の増大をまねき、処理効率
が低いという問題点がある。However, in such a conventional example, data transfer is carried out by the main CPU, which increases the load and reduces processing efficiency.

そこで１本発明は、メインＣＰＨによるデータの転送を
不要とする２ポートＲＡＭシステムを提供するものであ
る。One object of the present invention is to provide a two-port RAM system that eliminates the need for data transfer by the main CPH.

〔間騙点を解決するための手段〕[Means for resolving misunderstandings]

すなわち１本発明は、２ポートＲＡＭの所定アドレスを
ワークＲＡＭのアドレスと同一に設定し。That is, one aspect of the present invention is to set the predetermined address of the 2-port RAM to be the same as the address of the work RAM.

その領域をメインＣＰＵの書込み専用領域とするととも
に、チャ／ネルデコーダに工夫を加え、書込み・読出し
信号（書込み：■、読出し：Ｌ）がＨになるとき、すな
わち、メインＣＰＵがワークＲＡＭの前記所定アドレス
にデータ、書込みを行おうとすると、そのデータは、そ
のまま２ポートＲＡＭにも書込まれるようにするもので
ある。In addition to making this area a write-only area for the main CPU, we also added a device to the channel/channel decoder so that when the write/read signal (write: ■, read: L) becomes H, that is, the main CPU When an attempt is made to write data to an address, the data is also written directly to the 2-port RAM.

〔作用〕[Effect]

これによってサブＣＰＵは、２ポートＲＡＭの前記デー
タを読出すだけで良く、メインＣＰＵはデータ転送に関
し、特別の操作を必要としない。As a result, the sub CPU only needs to read the data from the 2-port RAM, and the main CPU does not need to perform any special operations regarding data transfer.

〔実施例Ｊ 本発明のチャンネルデコーダを第１図に示す。[Example J A channel decoder of the present invention is shown in FIG.

５．６は従来例第３図と同様で、これにナントゲート７
及び８とオアゲート９を付加したものである。5.6 is similar to the conventional example shown in Fig. 3, and Nant Gate 7 is added to this.
and 8 and OR gate 9 are added.

ＤＴ／Ｒは古込み・読出し信号で、′Ｈ′で書込み、′
″Ｌ′で読出しとなる。DT/R is an old read/write signal, write at 'H', '
Reading is performed at ``L''.

このゲート群のはたらきで、メインＣＰＵがワークＲＡ
ＭのアドレスｒＥ６０００〜Ｅ７ＦＦＦＪ　（すなわち
上位アドレス°１１１００１１’　）にデータを書込も
うとすると、２ポ一トＲＡＭのセレクト信号８ｂも、ワ
ークＲＡＭのセレクト信号Ｓａとともに発される。With the function of this gate group, the main CPU becomes the work RA.
When attempting to write data to addresses rE6000 to E7FFFJ (ie, upper address 01110011') of M, the 2-point RAM select signal 8b is also generated together with the work RAM select signal Sa.

これによって、このデータは、２ポートＲＡＭへも同時
に書込まれる。As a result, this data is simultaneously written to the 2-port RAM.

サブＣＰＵは、単にこれを読出すだけで良いことになり
、メインＣＰＵは何の処理も行う必要がなくなる。The sub CPU only needs to read this, and the main CPU does not need to perform any processing.

アドレス「、ＥＯＯＯＯ〜ＥＤＦＦＦＪ　（すなわち、
上位アドレス゛１１００１１０’　）のときは、従来ど
おり２ポ一トＲＡＭのみがセＶりトされ、読み書き可能
である。address ", EOOOO ~ EDFFFJ (i.e.
When the upper address is "1100110'", only the 2-point RAM is set and readable and writable as before.

〔発明の効果ｊ 以上述べたように、この発明によれば、はんのわずかな
部品を追加するだけで、メインＣＰＨの処理の負担を大
幅に軽減できるという大なる効果がある。[Effects of the Invention j] As described above, according to the present invention, there is a great effect that the processing burden on the main CPH can be significantly reduced by adding only a few parts of solder.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の具体的実施例、第２図はマルチＣＰＵ
ンステムの概念図、第３図は従来のチャ／ネルデコーダ
の例である。 ５：デコーダ 第１図Figure 1 shows a specific embodiment of the present invention, Figure 2 shows a multi-CPU
A conceptual diagram of the system, FIG. 3, is an example of a conventional channel/channel decoder. 5: Decoder Figure 1

Claims (1)

【特許請求の範囲】[Claims] ２ポートＲＡＭの所定のアドレスをワークＲＡＭのアド
レスと同一に設定し、その領域をメインＣＰＵの書込み
専用領域とするとともに、メインＣＰＵがワークＲＡＭ
の前記所定アドレスにデータの書込みを行おうとすると
、前記２ポートＲＡＭへもセレクト信号を発するチャン
ネルデコーダを備えたことを特徴とする２ポートＲＡＭ
システム。The predetermined address of the 2-port RAM is set to be the same as the address of the work RAM, and that area is designated as a write-only area for the main CPU.
A 2-port RAM characterized in that the 2-port RAM is equipped with a channel decoder that issues a select signal also to the 2-port RAM when data is to be written to the predetermined address of the 2-port RAM.
system.
JP26326484A 1984-12-12 1984-12-12 2-port ram system Pending JPS61139854A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26326484A JPS61139854A (en) 1984-12-12 1984-12-12 2-port ram system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26326484A JPS61139854A (en) 1984-12-12 1984-12-12 2-port ram system

Publications (1)

Publication Number Publication Date
JPS61139854A true JPS61139854A (en) 1986-06-27

Family

ID=17387041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26326484A Pending JPS61139854A (en) 1984-12-12 1984-12-12 2-port ram system

Country Status (1)

Country Link
JP (1) JPS61139854A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027044A (en) * 1989-04-11 1991-06-25 Mitsubishi Denki Kabushiki Kaisha Load state decision apparatus for servomotor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027044A (en) * 1989-04-11 1991-06-25 Mitsubishi Denki Kabushiki Kaisha Load state decision apparatus for servomotor

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