JPS61139854A - 2-port ram system - Google Patents
2-port ram systemInfo
- Publication number
- JPS61139854A JPS61139854A JP26326484A JP26326484A JPS61139854A JP S61139854 A JPS61139854 A JP S61139854A JP 26326484 A JP26326484 A JP 26326484A JP 26326484 A JP26326484 A JP 26326484A JP S61139854 A JPS61139854 A JP S61139854A
- Authority
- JP
- Japan
- Prior art keywords
- port ram
- main cpu
- ram
- data
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野J
本発明は、メインCPUが操作を行わずにデータ転送が
可能な2ボー) RAMシステムに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field J] The present invention relates to a 2-baud RAM system that is capable of data transfer without any operation by the main CPU.
第2図は、数値制御装置等において、現在頃等のデータ
をCRT表示装置等に表示するマルチCPUシステムの
概念図である。FIG. 2 is a conceptual diagram of a multi-CPU system that displays current data on a CRT display device or the like in a numerical control device or the like.
すなわち、メイyCPUIは「現在値」 「指令値」を
ワークRAM2のデータとして保有し、表示用のサブC
PU4から、2ポートRAM3を介してデータの要求が
あると、ワークLLAM2のデータを2ポートRAM3
に転送するシステムである。In other words, the Mayy CPUI retains the "current value" and "command value" as data in work RAM 2, and displays them in the sub-CPU.
When there is a request for data from PU4 via 2-port RAM3, the data of work LLAM2 is transferred to 2-port RAM3.
This is a system that transfers information to
この従来システムのチャンネルデコーダは、例えば第3
図に示すよう1乙所定アドレスごとにセ 。The channel decoder of this conventional system is, for example, a third channel decoder.
As shown in the figure, 1B is set for each predetermined address.
レフトされるRAMが異なる。この例では、デコーダ5
(L、5I3B)とナントゲート6で構成しており、ア
ドレス信号AIl〜A+3が’11100目″のときは
Y3出力がL′となりワークRAMがセレクトされ、同
じ< ’+110110−のときはY6出力がL′とな
り2ポートRAMがセレクトされる。The left RAM is different. In this example, decoder 5
(L, 5I3B) and a Nant gate 6, when the address signal AIl~A+3 is '11100th', the Y3 output becomes L' and the work RAM is selected, and when the same <'+110110-, the Y6 output becomes L', and the 2-port RAM is selected.
ところが、このような従来例では、データの転送はメイ
ンCPUの1担となり、負荷の増大をまねき、処理効率
が低いという問題点がある。However, in such a conventional example, data transfer is carried out by the main CPU, which increases the load and reduces processing efficiency.
そこで1本発明は、メインCPHによるデータの転送を
不要とする2ポートRAMシステムを提供するものであ
る。One object of the present invention is to provide a two-port RAM system that eliminates the need for data transfer by the main CPH.
すなわち1本発明は、2ポートRAMの所定アドレスを
ワークRAMのアドレスと同一に設定し。That is, one aspect of the present invention is to set the predetermined address of the 2-port RAM to be the same as the address of the work RAM.
その領域をメインCPUの書込み専用領域とするととも
に、チャ/ネルデコーダに工夫を加え、書込み・読出し
信号(書込み:■、読出し:L)がHになるとき、すな
わち、メインCPUがワークRAMの前記所定アドレス
にデータ、書込みを行おうとすると、そのデータは、そ
のまま2ポートRAMにも書込まれるようにするもので
ある。In addition to making this area a write-only area for the main CPU, we also added a device to the channel/channel decoder so that when the write/read signal (write: ■, read: L) becomes H, that is, the main CPU When an attempt is made to write data to an address, the data is also written directly to the 2-port RAM.
これによってサブCPUは、2ポートRAMの前記デー
タを読出すだけで良く、メインCPUはデータ転送に関
し、特別の操作を必要としない。As a result, the sub CPU only needs to read the data from the 2-port RAM, and the main CPU does not need to perform any special operations regarding data transfer.
〔実施例J 本発明のチャンネルデコーダを第1図に示す。[Example J A channel decoder of the present invention is shown in FIG.
5.6は従来例第3図と同様で、これにナントゲート7
及び8とオアゲート9を付加したものである。5.6 is similar to the conventional example shown in Fig. 3, and Nant Gate 7 is added to this.
and 8 and OR gate 9 are added.
DT/Rは古込み・読出し信号で、′H′で書込み、′
″L′で読出しとなる。DT/R is an old read/write signal, write at 'H', '
Reading is performed at ``L''.
このゲート群のはたらきで、メインCPUがワークRA
MのアドレスrE6000〜E7FFFJ (すなわち
上位アドレス°1110011’ )にデータを書込も
うとすると、2ポ一トRAMのセレクト信号8bも、ワ
ークRAMのセレクト信号Saとともに発される。With the function of this gate group, the main CPU becomes the work RA.
When attempting to write data to addresses rE6000 to E7FFFJ (ie, upper address 01110011') of M, the 2-point RAM select signal 8b is also generated together with the work RAM select signal Sa.
これによって、このデータは、2ポートRAMへも同時
に書込まれる。As a result, this data is simultaneously written to the 2-port RAM.
サブCPUは、単にこれを読出すだけで良いことになり
、メインCPUは何の処理も行う必要がなくなる。The sub CPU only needs to read this, and the main CPU does not need to perform any processing.
アドレス「、EOOOO〜EDFFFJ (すなわち、
上位アドレス゛1100110’ )のときは、従来ど
おり2ポ一トRAMのみがセVりトされ、読み書き可能
である。address ", EOOOO ~ EDFFFJ (i.e.
When the upper address is "1100110'", only the 2-point RAM is set and readable and writable as before.
〔発明の効果j
以上述べたように、この発明によれば、はんのわずかな
部品を追加するだけで、メインCPHの処理の負担を大
幅に軽減できるという大なる効果がある。[Effects of the Invention j] As described above, according to the present invention, there is a great effect that the processing burden on the main CPH can be significantly reduced by adding only a few parts of solder.
第1図は本発明の具体的実施例、第2図はマルチCPU
ンステムの概念図、第3図は従来のチャ/ネルデコーダ
の例である。
5:デコーダ
第1図Figure 1 shows a specific embodiment of the present invention, Figure 2 shows a multi-CPU
A conceptual diagram of the system, FIG. 3, is an example of a conventional channel/channel decoder. 5: Decoder Figure 1
Claims (1)
レスと同一に設定し、その領域をメインCPUの書込み
専用領域とするとともに、メインCPUがワークRAM
の前記所定アドレスにデータの書込みを行おうとすると
、前記2ポートRAMへもセレクト信号を発するチャン
ネルデコーダを備えたことを特徴とする2ポートRAM
システム。The predetermined address of the 2-port RAM is set to be the same as the address of the work RAM, and that area is designated as a write-only area for the main CPU.
A 2-port RAM characterized in that the 2-port RAM is equipped with a channel decoder that issues a select signal also to the 2-port RAM when data is to be written to the predetermined address of the 2-port RAM.
system.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26326484A JPS61139854A (en) | 1984-12-12 | 1984-12-12 | 2-port ram system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26326484A JPS61139854A (en) | 1984-12-12 | 1984-12-12 | 2-port ram system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61139854A true JPS61139854A (en) | 1986-06-27 |
Family
ID=17387041
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26326484A Pending JPS61139854A (en) | 1984-12-12 | 1984-12-12 | 2-port ram system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61139854A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5027044A (en) * | 1989-04-11 | 1991-06-25 | Mitsubishi Denki Kabushiki Kaisha | Load state decision apparatus for servomotor |
-
1984
- 1984-12-12 JP JP26326484A patent/JPS61139854A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5027044A (en) * | 1989-04-11 | 1991-06-25 | Mitsubishi Denki Kabushiki Kaisha | Load state decision apparatus for servomotor |
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