JPS61132032A - Relay for excessive or short voltage - Google Patents
Relay for excessive or short voltageInfo
- Publication number
- JPS61132032A JPS61132032A JP25429084A JP25429084A JPS61132032A JP S61132032 A JPS61132032 A JP S61132032A JP 25429084 A JP25429084 A JP 25429084A JP 25429084 A JP25429084 A JP 25429084A JP S61132032 A JPS61132032 A JP S61132032A
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- voltage
- overvoltage
- undervoltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の利田分野〕
不発明は過不足電圧継′ＩＭ、器に係り、特に電路に設
けられた断路器の投入時における異常電圧に対する保護
機能の向上に好適な過不足電圧継電器に関する。[Detailed Description of the Invention] [Toshida Field of the Invention] The invention relates to an over/under voltage relay (IM), and particularly to an over/under voltage relay suitable for improving the protection function against abnormal voltage when a disconnector installed in an electric circuit is turned on. Regarding undervoltage relays.
従来の過電圧継電器または不足電圧継電器は実公昭５６
−４９２３０号公報、実公昭５６−５２７５５号公報に
開示されているように、断路器投入以前より発生してい
た電路の異常電圧に対する対策が行なわれていなかった
。そのため、断路器投入前における異常電圧、特に過電
圧に対して、一時的く「電路電圧が正常である」という
信号を出してしまうという問題点があった。Conventional overvoltage relays or undervoltage relays are
As disclosed in Japanese Utility Model Publication No. 49230 and Japanese Utility Model Publication No. 56-52755, no countermeasures were taken against the abnormal voltage in the electrical circuit that had been occurring before the disconnector was turned on. Therefore, there is a problem in that, in response to an abnormal voltage, especially an overvoltage, before the disconnector is turned on, a signal that "the line voltage is normal" is temporarily output.
本発明の目的は、断路器投入以前から発生していた里常
電圧に対し、断路器投入後の過不足電圧継電器の制御回
路の立上り時においても誤動作を生じることのない過不
足電圧継電器を提供することＫある。An object of the present invention is to provide an over/under voltage relay that does not malfunction even when the control circuit of the over/under voltage relay starts up after the disconnector is turned on, with respect to the normal voltage that has been occurring before the disconnector is turned on. There's K things to do.
本発明は、過不足電圧継電器において、！圧検知手段と
、該電圧検知手段の出力端子（それぞれ並列に接続され
た過電圧検出手段および不足電圧検出手段と、該過電圧
検出手段および該不足電圧検出手段の少くともいずれか
一方の動作開始に同期して計数を開始する計数手段と、
該計数手段の出力と前記過電圧検出手段および前記不足
電圧検出手段の少くともいずれか一方の出力との論理撰
により出力を発生する出力手段と、前記過電圧検出手段
、不足電圧検出手段、計数手段、および出力手段に１１
Ｅ源を供給する電源供給手段とを備えて成ることを特徴
とするものである。The present invention provides over/under voltage relays. voltage detection means, an output terminal of the voltage detection means (an overvoltage detection means and an undervoltage detection means connected in parallel, respectively, and synchronized with the start of operation of at least one of the overvoltage detection means and the undervoltage detection means). a counting means for starting counting by
an output means that generates an output by a logical selection of the output of the counting means and the output of at least one of the overvoltage detection means and the undervoltage detection means; the overvoltage detection means, the undervoltage detection means, the counting means; and 11 to the output means.
The apparatus is characterized in that it comprises a power supply means for supplying an E source.
以下１本発明の実施例を第１図〜第１０図により説明す
る。第１因は本発明の１実施例の全体構成を示すブロッ
ク崗である。An embodiment of the present invention will be described below with reference to FIGS. 1 to 10. The first factor is the block diagram showing the overall configuration of one embodiment of the present invention.
次に断路器が投入されてから電源がブ上す、制御回路が
動作するまでの本実施例の動作を第２図〜第４図により
説明する。Next, the operation of this embodiment from when the disconnector is turned on until the power is turned on and when the control circuit operates will be explained with reference to FIGS. 2 to 4.
入力端子１０に印加された電圧は変圧器１１を介して整
流器１２によジ全波整流されコンデンサ１３で平滑され
る。さらに前記平滑電圧はツェナーダイオード１４の基
進電圧で安定化電源回路１５により安定化され、コンデ
ンサ１６に蓄電され制御回路１７に印加される。次に制
御電源確立検出回路１８の構成は前記安定化電源を抵抗
１９．２０により分圧し、比較器２１の反転入力端子に
入力、他方非反転入力には抵抗２２、ツェナーダイオー
ド２３による基準電圧が入力されている。The voltage applied to the input terminal 10 is full-wave rectified by a rectifier 12 via a transformer 11 and smoothed by a capacitor 13. Further, the smoothed voltage is stabilized by a stabilizing power supply circuit 15 using the base voltage of a Zener diode 14, and is stored in a capacitor 16 and applied to a control circuit 17. Next, the configuration of the control power supply establishment detection circuit 18 is such that the stabilized power supply is divided by resistors 19 and 20, and is inputted to the inverting input terminal of the comparator 21, while the reference voltage by the resistor 22 and Zener diode 23 is input to the non-inverting input terminal. It has been entered.
今、第３図（ａｔに示すような入力電圧が入力端子１０
に印加されたとすると、前述したコンデンサ１６の電位
Ｆは第３図（ｂ１４ｃ示す如く漸増する。これに伴ない
比較器２１の非反転および反転入力の電位Ｇ、 Ｈは
それぞれ第５ ＩＩ（ｂｌのＧ、Ｈのように変化する。Now, the input voltage as shown in Fig. 3 (at) is applied to the input terminal 10.
, the potential F of the capacitor 16 mentioned above gradually increases as shown in FIG. It changes like G and H.
そして両者が同図の関係になる二うツェナーダイオード
２５、抵抗１９．２０の比を選定することにより比較器
２１の出力Ａは電源電圧？がほぼ最終電圧になったとき
第２図（ｃｌに示すようにｒＨＪ レベルからｒＬＪレ
ベル〈変化する。Then, by selecting the ratio of the two Zener diodes 25 and the resistors 19.20 so that both have the relationship shown in the figure, the output A of the comparator 21 is equal to or less than the power supply voltage. When the voltage reaches almost the final voltage, the voltage changes from the rHJ level to the rLJ level, as shown in Figure 2 (cl).
制御回路１７には過電圧検出手段２４と不足電圧検出回
路２５が含でれており、それぞれ異常電圧検出時に信号
を出す。The control circuit 17 includes an overvoltage detection means 24 and an undervoltage detection circuit 25, each of which outputs a signal when an abnormal voltage is detected.
今、入力端子が過電圧整定値以下で、且つ、不足電圧整
定値以上のいわゆる正常状態の場合、第２図（１３）に
示すように一定時間経過後、比較器２１の出力ＡはｒＬ
Ｊレベルに反転するのでＮＯＴゲート２６ｆｔ介してＡ
ＮＤゲート２７への入力はｒＨＪレベルとなる。また、
過電圧、不足電圧検出回路２４．２５の出力Ｂ、 Ｃ
はいずれもｒＬＪレベルで、それぞれＮＯＴＯＲゲート
３０９ｇらにＯＲゲート３０．！ｉ１を介してＡＮＤゲ
ート２７への入力はｒＨＪレベルとなる。これによりＡ
ＮＤゲート２７の出力は「Ｈコレペルとなり、ＯＲゲ−
）３０．３１のもう一方の入力もｒＨＪレベルに変化し
、ＡＮＤゲート２７の出力がｒｌ（Ｊレベルに保持され
ることになる。Now, if the input terminal is in a so-called normal state where the voltage is below the overvoltage setting value and above the undervoltage setting value, the output A of the comparator 21 will become rL after a certain period of time as shown in FIG. 2 (13).
Since it is inverted to J level, A is passed through NOT gate 26ft.
The input to the ND gate 27 is at rHJ level. Also,
Outputs B and C of overvoltage and undervoltage detection circuits 24 and 25
are all at the rLJ level, and the NOTOR gate 309g and the OR gate 30.g are connected to each other. ! The input to the AND gate 27 via i1 becomes rHJ level. This allows A
The output of the ND gate 27 becomes "H" and becomes the OR gate.
) 30. The other input of 31 also changes to rHJ level, and the output of AND gate 27 is held at rl(J level).
また、制御回路１７には限時回路３２が含１れており、
上記正常状態から過電圧または不足電圧が発生した場合
、限時時間整定値の時間経過後に信号を出す。断路器６
投入時電路が正常状態にあるとき、限時回路の出力りは
「Ｌ」レベルでＮＯＴゲー）３５を介してＡＮ’Ｄゲー
ト３４への入力はｒｌレベルとなる。また、前記ＡＮＤ
ゲート２７の出力はｒＨＪレベルに保持されているので
ＡＩＪＤゲート６４への入力は「■」レベルで出力Ｅは
ｒＨＪレベルとなりトランジスタ３５がＯＮＩ、、て出
力リレー３６が励磁され、この時電路に設置された遮断
器の投入が可能となる。Further, the control circuit 17 includes a time limit circuit 32,
If overvoltage or undervoltage occurs from the above normal state, a signal is issued after the time limit setting value has elapsed. Disconnector 6
When the electric circuit is in a normal state at the time of turning on, the output of the time limit circuit is at the "L" level, and the input to the AND'D gate 34 via the NOT gate 35 is at the rl level. In addition, the AND
Since the output of the gate 27 is held at the rHJ level, the input to the AIJD gate 64 is at the "■" level and the output E is at the rHJ level, turning the transistor 35 ON, and the output relay 36 is energized. It becomes possible to close the circuit breaker that has been closed.
次に上記正常状態から不足電圧に移行した場合不足゛賦
圧検出回路２５からの出力はｒＨＪレベルとなるが、Ａ
ＮＤゲート２７の出力はｒＨＪレベルに保持されている
ので変化することはない。しかし限時回路３２が働き一
定時間後出力を出しＡＮＤゲート３４の出力ｌをｒＲＪ
から「１．Ｊレベルに変化させ出力リレー３６の励磁を
解いて異常電圧検出状態にする。なお正常状態から過電
圧が発生した場合も同様である。また、正常状態から停
電になった場合における電源はコンデンサ１６で補償す
る。これらのタイムチャートを第６図（ａｔに示す。Next, when the above-mentioned normal state shifts to undervoltage, the output from the undervoltage detection circuit 25 becomes rHJ level, but A
Since the output of the ND gate 27 is held at the rHJ level, it does not change. However, the time limit circuit 32 works and outputs after a certain period of time, changing the output l of the AND gate 34 to rRJ.
to 1.J level and de-energizes the output relay 36 to set the abnormal voltage detection state.The same applies when an overvoltage occurs from a normal state.Also, the power supply in the case of a power outage from a normal state are compensated by the capacitor 16. A time chart of these is shown in FIG. 6 (at).
次に電路において断路器３の投入以前に異常電圧である
場合、たとえば過電圧の時は比較器２１と不足電圧検出
回路２５のＡＮＤゲート２７への入力はｒＨＪレベルで
あるが、過電圧検出回路２４からの出力ＢはｒＨＪレベ
ルとなり、電源確立時点で「ＬコレベルであろたＡＮＤ
ゲート２７の出力はｒＨＪレベルになることはできず、
すなわち出力リレー３６は励磁されず遮断器の投入がで
きない。また、最初から停電の場合には回路が働かない
ので出力リレー５６は励磁されず、電源が確保できる位
の不足電圧に対しては前記遮断器投入前に過電圧である
場合と同様の回路動作を行う。Next, if there is an abnormal voltage in the electrical circuit before the disconnector 3 is turned on, for example, in the case of an overvoltage, the inputs to the AND gate 27 of the comparator 21 and the undervoltage detection circuit 25 are rHJ level, but the input from the overvoltage detection circuit 24 Output B becomes rHJ level, and when power is established, it is "L level AND
The output of gate 27 cannot reach rHJ level,
In other words, the output relay 36 is not energized and the circuit breaker cannot be closed. In addition, in the case of a power outage, the circuit does not work from the beginning, so the output relay 56 is not energized, and the circuit operates in the same way as in the case of overvoltage before the circuit breaker is closed, in case of an undervoltage to the extent that the power supply can be secured. conduct.
断路器３の投入時点より過電圧の場合のタイムチャート
を第４図（ｂ）に示す。なお、第４図（ａ）、 （ｂｌ
において（イ）は制御電源確立回路１８の出力、（ロ）
は過電圧検出回路２４の出力、（ハ）は不足電圧検出回
路２５の出力、に）祉限時回路３２の出力、（ホ）は出
力回路のＡＮＤゲート３４の出力を示す。A time chart in the case of overvoltage from the time when the disconnector 3 is turned on is shown in FIG. 4(b). In addition, Fig. 4(a), (bl
In (a), the output of the control power supply establishment circuit 18, (b)
(c) shows the output of the overvoltage detection circuit 24, (c) shows the output of the undervoltage detection circuit 25, (c) shows the output of the safety time limit circuit 32, and (e) shows the output of the AND gate 34 of the output circuit.
本実施例では、制御回路電源と検出電圧を同一端子から
得ているため、新路器３が投入されるまでは出力リレー
は継電器が異常電圧を検知した動作状態にある。In this embodiment, since the control circuit power source and the detection voltage are obtained from the same terminal, the output relay is in an operating state in which the relay has detected an abnormal voltage until the new circuit 3 is turned on.
断路器６の投入前からの電路の異常電圧に対しては断路
器３の投入後も出力リレーは前記継″ＴｉＬ器の動作状
態を保ち遮断器１の投入を阻止する。Even after the disconnector 3 is closed, the output relay maintains the operating state of the relay TiL switch and prevents the circuit breaker 1 from closing even after the disconnector 3 is closed.
断路器３０投入時、正常電圧である場合においては、初
期異常電圧における回路動作を解除する。。If the voltage is normal when the disconnector 30 is turned on, the circuit operation at the initial abnormal voltage is canceled. .
なお、制御電源の確立を検知する電圧レベルを比較器や
、過・不足電圧検出器及び限時回路用のカウンタなどに
用いる１Ｃの保証電源電圧下限値近辺まで下げると、電
源確立までの時間を早くすることができる。この場合、
各ゲート回路を１Ｃの保証電源電圧以下で機能する素子
（例えばダイオードやトランジスタ等）で構成すると良
い。Note that lowering the voltage level that detects the establishment of the control power supply to around the lower limit of the guaranteed power supply voltage of 1C used for comparators, over/undervoltage detectors, time-limit circuit counters, etc. will speed up the time until the power supply is established. can do. in this case,
It is preferable that each gate circuit is composed of elements (eg, diodes, transistors, etc.) that function at a guaranteed power supply voltage of 1C or less.
本実施例〈よれば検出電圧と制御回路の電源を同一ライ
ンより得ているので、制御回路の電源を別途に設ける場
合に比べて配線の手間が不要となるとともに、継電器を
小形化することができる。According to this embodiment, since the detection voltage and the power supply for the control circuit are obtained from the same line, there is no need for wiring compared to the case where the power supply for the control circuit is provided separately, and the relay can be made smaller. can.
第５図体）および第５図（Ｂｌに本実施例における過不
足電圧酵電器の全体構成の回路図を分割して示す。Figure 5 (B) and Figure 5 (Bl) show divided circuit diagrams of the overall configuration of the over/under voltage fermentor in this embodiment.
次に第５図（Ａｌ、 （Ｂ）における各部の動作を説明
するＯ
電圧検知手段５０である入力、整流回路においては、変
圧器１０１により入力電圧を降圧し、ダイオードブリッ
ジ１０２で全波整流する。過電圧検出手段５２、不足電
圧検出手段５４において、過電圧整定回路、不足電圧整
定回路の動作は次のようになる。Next, the operation of each part in FIG. 5 (Al, (B) will be explained). In the overvoltage detection means 52 and the undervoltage detection means 54, the overvoltage setting circuit and the undervoltage setting circuit operate as follows.
スイッチ１０３，１０４により、抵抗１０５゜１０６の
抵抗比を変化させ、各々過電圧、不足電圧整定を行なう
。尚、ツェナダイオード１４０゜１０７は過入力保護、
ダイオード１０８は入力投入時、信号系（変圧器１０１
）を介した信号系からもｔ源平滑コンデンサ１０９へ充
電々流ケ送り、電源確立時間を早くするものである。Switches 103 and 104 change the resistance ratio of resistors 105 and 106 to set overvoltage and undervoltage, respectively. In addition, the Zener diode 140°107 is for over-input protection.
When the input is turned on, the diode 108 connects the signal system (transformer 101
) from the signal system to the t-source smoothing capacitor 109, thereby speeding up the power supply establishment time.
過電圧レベル検出回路について説明する。The overvoltage level detection circuit will be explained.
ピークホールドコンデンサ１１０の電位を抵抗１１１、
コンデンサ１１２でさらに平滑し〜比較器１１３，１１
４の反転入力に入力し、基準電圧（各々の比較器の非反
転入力）を比較する。過電圧入力の時、比較器１１３，
１１４の反転入力電位上昇 同比較器出力［ＬＪ−ａ−
比較器１１５出力「Ｌ」、比較器１１６「ＨＪ−ａ−比
較器１１５出力ｒＬＪによりカウンタ１１７リセツト端
子「ＬＪ（リセット解除）、トランジスタ１１８ペース
ｒＬＪ （トランジスタ１１９は通常「Ｌ」］ 自
励発振開始（トランジスタ１１１３．１１９は自励発振
停止用）。尚、比較器１１５は過電圧１００チ以上で出
力反転、同１１４は同１３％以上で出力反転する機に基
準電圧を設足しである。The potential of the peak hold capacitor 110 is set by a resistor 111,
Further smoothing with capacitor 112 ~ comparators 113, 11
4 and compare the reference voltage (non-inverting input of each comparator). At the time of overvoltage input, comparator 113,
114 inverting input potential rise Comparator output [LJ-a-
Comparator 115 output "L", comparator 116 "HJ-a- Comparator 115 output rLJ causes counter 117 reset terminal "LJ (reset release), transistor 118 pace rLJ (transistor 119 is normally "L") Self-oscillation starts (Transistors 1113 and 119 are for stopping self-excited oscillation.) The comparator 115 inverts the output when the overvoltage exceeds 100%, and the comparator 114 provides a reference voltage to invert the output when the overvoltage exceeds 13%.
計数手段５６において、発振回路は比較器１２０および
増幅器として使用される比較器１２１とにより構成され
る。カウンタ回路はカウンタエＣ１１７にて構成され、
その出力を過電圧・不足電圧動作時間整定回路へ供給す
る０
出力手段の過不足判別回路は１３０％以上の過電圧信号
とカウンタ最大ピット出力の論理和をとムＡＮＤ回ｖｒ
１２６または１２７の入力へ信号を供給する。In the counting means 56, the oscillation circuit is constituted by a comparator 120 and a comparator 121 used as an amplifier. The counter circuit is composed of a counter C117,
The output is supplied to the overvoltage/undervoltage operation time setting circuit.The overvoltage/deficiency discrimination circuit of the output means logically ORs the overvoltage signal of 130% or more and the maximum pit output of the counter.
126 or 127 input.
一方比較器１１５ （１５０）ｒＬＪにより− トラ
ンジスタ１２８（１２９） コレクタｒＨＪ→ＡＮＤ１
？６ （１２７）ｒＨＪ今トランジスタ１３１コレク
タｒＬＪ＋）ランラスタ１５２コレクタｒＨＪ、−出力
リレーコイル励磁解除となる。On the other hand, by comparator 115 (150) rLJ - transistor 128 (129) collector rHJ → AND1
? 6 (127) rHJ Now transistor 131 collector rLJ +) Run raster 152 collector rHJ, - Output relay coil excitation is released.
なお、正常時にリレーコイルは励磁状襲である。Note that the relay coil is in an energized state during normal operation.
以上の構成において、入力投入時の動作は以下のように
なる。In the above configuration, the operation when input is input is as follows.
電源雷、圧（Ｖｃｃ）確立前＝比較器１４１によりＡＮ
Ｄ１２６，１２７人カ一端をダイオード１３３を介しｒ
ＬＪとする（、（Ｖ ｃ ｃ確立前のリレー動作阻止）
。又アナログスィッチ１３４，１３５非導通とする（禍
、不足動作表示ＬＥＤ点灯防止）。Power supply lightning, before voltage (Vcc) is established = AN by comparator 141
Connect one end of D126 and 127 through diode 133.
Set to LJ (, (blocking relay operation before establishing V c c)
. Also, the analog switches 134 and 135 are made non-conductive (to prevent illumination of the insufficient operation display LED).
電源電圧（ＶＣＣ）確立後 （１）正常な場合＝比較器
１１５，１３０出力は共に［ＨＪ＋ダイオード１３６ａ
アノード電位「Ｌ」、トランジスタ１３１ペース電位ｒ
ＬＪ→トランジスタ１３２導通 リレーコイル励磁 （
２）異常（過電圧又は不足電圧）の場合＝比較器１１５
．１！＋Ｏ出力のいずれかが「ＬＪ−ａｐダイオード１
５６ａアノード開→→ランジスタ１３８コレクタｒＬＪ
→リレーコイル励磁せず、となり誤動作を防止する０第
に篇６図〜第８図について説明する。After establishing the power supply voltage (VCC) (1) Normal case = comparator 115, 130 outputs are both [HJ + diode 136a
Anode potential "L", transistor 131 pace potential r
LJ→Transistor 132 conduction Relay coil excitation (
2) In case of abnormality (overvoltage or undervoltage) = comparator 115
．． 1! Either +O output is “LJ-ap diode 1
56a anode open → → transistor 138 collector rLJ
→The relay coil is not energized to prevent malfunction. 0 Firstly, Figures 6 to 8 will be explained.
本実施例は入力投入時、信号検出要素から電源要素へ通
電することにより電源確立を早くしたものである。In this embodiment, power is established quickly by supplying power from the signal detection element to the power supply element when input is turned on.
第６図において、入力２０１投入◆変圧器２０２゜ダイ
オードブリッジ２０４、コンデンサ２０５により整流平
滑噛安定化回路２０６を介し、平滑コンデンサ２０７に
蓄もこの時の電源確立の時間的推移は第７図Ａで示す。In Fig. 6, input 201 is turned on ◆Transformer 202゜ Diode bridge 204, capacitor 205 passes through rectification smoothing stabilization circuit 206, and is stored in smoothing capacitor 207.The time course of power supply establishment at this time is shown in Fig. 7A. Indicated by
（以上電源回路２２１の説明）
一方、検出回路２２２は、変圧器２０３、ダイオードブ
リッジ２０日により整流惨抵抗２０９、可変抵抗２１０
で分圧され、検出回路２””。(The above is a description of the power supply circuit 221.) On the other hand, the detection circuit 222 includes a transformer 203, a diode bridge 20, a rectifying resistor 209, a variable resistor 210,
The voltage is divided by the detection circuit 2"".
この時、検出回路入力電圧の立上９は瞬時（厳密には変
圧器等介入素子による遅れはあるが）であり、入力２０
１投入時は検出回路入力電圧が電源電圧エリ大きい。よ
ってダイオード２１２により平滑コンデンサ２０７へ電
流が流れ、第７［ＶＢのように電源確立が早くなる。以
上は、定常時（過電圧継電器等の場合は最大整定値）検
出回路入力電圧が電源電圧以上にならない場合の接続。At this time, the rise 9 of the detection circuit input voltage is instantaneous (strictly speaking, there is a delay due to intervening elements such as a transformer), and the input voltage 9
When 1 is turned on, the detection circuit input voltage is higher than the power supply voltage. Therefore, current flows to the smoothing capacitor 207 by the diode 212, and the power supply is established quickly as in the seventh [VB]. The above is a connection when the detection circuit input voltage does not exceed the power supply voltage during steady state (maximum setting value in the case of overvoltage relays, etc.).
以上になる場合は第６−破線の接続により対応できる（
検出回路入力電圧が大きくなると、コンデンサ２０５の
電位も上がる。即ち、ダイオード２１２のカソード電位
がアノード電位よりも大きい。）第８（９）は仲の実施
例を示す。定常時、電源電圧が入力信号整流値よりも大
きい場合はダイオードアノードを図示の如く接続し、さ
らに確立時間を早くできる（第７図Ｃ）。尚、第８図破
線の接続は第６図と同じため省略する。If the above is the case, it can be handled by connecting the 6th dashed line (
As the detection circuit input voltage increases, the potential of the capacitor 205 also increases. That is, the cathode potential of the diode 212 is higher than the anode potential. ) Section 8 (9) shows a middle embodiment. When the power supply voltage is larger than the input signal rectification value during normal operation, the diode anode is connected as shown in the figure to further speed up the establishment time (FIG. 7C). Note that the connections indicated by broken lines in FIG. 8 are the same as those in FIG. 6 and will therefore be omitted.
次に第９図、第１０図を説明する。Next, FIGS. 9 and 10 will be explained.
本実施例の目的は、相反する要素の遅延回路を共用し、
回路構成部品数を低減し、小形で信頼性の高い継を器を
提供することにある。The purpose of this embodiment is to share the delay circuits of contradictory elements,
The object of the present invention is to reduce the number of circuit components and provide a small and highly reliable joint.
互いに相反する要素を備えた継′を器にはたとえば過電
圧検出要素（以下Ｏｖ要素と称す）と不足電圧検出要素
（以下ＵＶｎ素と称す）を備えた過不足電圧継電器があ
る。各要素は一般に第９図に示す構成となっている。即
ちレベル検出部６０１により入力量と基蕩量を比較し、
遅延回路３０２により予め設定された時間遅蝿された後
出力回路３０３により外部出力を得る。ところでこれら
の相反する要素は同時に動作出力することはないから、
上記遅延回路２は各々独立に有する必要はなく、共用に
して回路簡略化を図ることができる。An example of a relay having mutually contradictory elements is an overvoltage/undervoltage relay having an overvoltage detection element (hereinafter referred to as Ov element) and an undervoltage detection element (hereinafter referred to as UVn element). Each element generally has the configuration shown in FIG. That is, the level detection unit 601 compares the input amount and the base indemnity amount,
After being delayed by a preset time by a delay circuit 302, an external output is obtained by an output circuit 303. By the way, these contradictory elements do not output the operation at the same time, so
The delay circuits 2 do not need to be provided independently, and can be shared to simplify the circuit.
以下、本実施例を第１０図により説明する。This embodiment will be explained below with reference to FIG.
正常時扛過電圧検出回路１人、不足電圧検出回路３０１
Ｂ共、出力が「Ｌ」、よってＯＲゲート３０４の出力は
ｒＬＪ、よってカウンタ３０２Ａはリセット状態、よっ
てカウンタ５０２Ａの出力ｒＬＪ、よって出力回路３０
３Ａ、３０３Ｂは不動作となる。1 overvoltage detection circuit during normal operation, 301 undervoltage detection circuits
Both B outputs are "L", so the output of the OR gate 304 is rLJ, so the counter 302A is in the reset state, so the output of the counter 502A is rLJ, so the output circuit 30
3A and 303B become inactive.
過電圧（不足電圧）時には５０１ Ａ（３０１Ｂ）出力
ｒＨＪ→ＯＲゲート５０ル出力ｒＨＪ今カウンタ３０２
Ａリセット解除 カウンタ３０２Ａ力ウント開始→カウ
ンタ出力ｒＨＪ→動作時間整定スイッチ３０２Ｂ （
３０２１：りを介しＡＮＤゲート５０６ （３０５）
へ入力＋ＡＮＤゲート３０６Ｔ３０５）出力ｒＨＪ◆出
力回路３０５Ａ（３０３Ｂ）動作となる。At the time of overvoltage (undervoltage), 501 A (301B) output rHJ → OR gate 50 output rHJ now counter 302
A reset release Counter 302A power count start → Counter output rHJ → Operating time setting switch 302B (
3021: AND gate 506 (305)
Input to AND gate 306T305) Output rHJ◆Output circuit 305A (303B) operates.
本実施例によれば、相反する要素の遅延回路を共用する
ことができる。According to this embodiment, delay circuits of contradictory elements can be shared.
以上説明したように本発明によれば、検出電圧と継電器
内制御斐電源を同一ラインより得ており、さらにゲート
回路の組合せにより初期異常電圧に対しては出力リレー
が無励磁状態を保つので電路の遮断器の投入が阻止され
信頼性の高い電路の保護が可能となる。As explained above, according to the present invention, the detection voltage and the relay control power source are obtained from the same line, and the combination of the gate circuit keeps the output relay in a non-excited state even in the case of an initial abnormal voltage, so the electric circuit This prevents the circuit breaker from closing, allowing highly reliable protection of the electrical circuit.
第１図は本発明の１実施例の全体構成を示すブロック図
、第２図は本発明の１実施例の回路図、第３因、第４図
は本発明の１実施例の各部の波形図−筆５図（Ａｔ、第
５ ＩＮ（Ｂｌは本発明の１実施例の具体的回路図、第
６図、第８図は′９源確立を早めるための回路を示す回
路図−第７□□□は第６図、 ＠８図の回路における波
形図、第９図は相反する要素の遅延回路を備えた継電器
の一般的構成を示すブロック図、第１０図は相反する要
素の遅延回路を共用した継電器の回路図、第１１図は高
圧受電設備の１例を示すブロック□□□である。
５０：を圧検細手段、５２：過電圧検出手段、５４：不
足電圧検出手段−５６二計数手段へ５８：出力手段、６
０：を源供給手段
一♂τ −−コτ
第 ３ 目
第 ４ 図
！−６に
第 ７ 閉
第 ８ 目
第 ９ 図
弗 ｔｏ 圀
第１１０
事件の表示
昭和５９ 年特許願第 ２５４２９０ 号発明の名
称
過不足電圧継電器
補正をする者
１件との関係 特 許 出願 人名 称
′５１０１株式会吐 日 立 製 作所代
理 人Fig. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, Fig. 2 is a circuit diagram of an embodiment of the invention, the third factor is shown, and Fig. 4 is a waveform of each part of an embodiment of the invention. Figure-Brush Figure 5 (At, 5th IN (Bl is a specific circuit diagram of one embodiment of the present invention, Figures 6 and 8 are '9 circuit diagrams showing circuits for speeding up the establishment of the source) - Figure 7 □□□ are waveform diagrams in the circuits shown in Figures 6 and @8, Figure 9 is a block diagram showing the general configuration of a relay equipped with a delay circuit of contradictory elements, and Figure 10 is a delay circuit of contradictory elements. Figure 11 is a block □□□ showing an example of high-voltage power receiving equipment. 50: voltage inspection means, 52: overvoltage detection means, 54: undervoltage detection means To counting means 58: output means, 6
0: Source supply means ♂τ --koτ 3rd item 4th figure! -6 to No. 7 Closed No. 8 No. 9 Illustration to Kuni No. 110 Display of the case 1982 Patent Application No. 254290 Name of the invention Relationship with one person who corrects over- and under-voltage relays Patent Application Name of person
'5101 Hitachi Ltd., Ltd.
person
Claims (1)
並列に接続された過電圧検出手段および不足電圧検出手
段と、該過電圧検出手段および該不足電圧検出手段の少
くともいずれか一方の動作開始に同期して計数を開始す
る計数手段と、該計数手段の出力と前記過電圧検出手段
および前記不足電圧検出手段の少くともいずれか一方の
出力との論理積により出力を発生する出力手段と、前記
過電圧検出手段、不足電圧検出手段、計数手段、および
出力手段に電源を供給する電源供給手段とを備えて成る
過不足電圧継電器。A voltage detection means, an overvoltage detection means and an undervoltage detection means connected in parallel to the output terminal of the voltage detection means, respectively, and synchronized with the start of operation of at least one of the overvoltage detection means and the undervoltage detection means. a counting means that starts counting when the count is reached; an output means that generates an output by logical product of the output of the counting means and the output of at least one of the overvoltage detection means and the undervoltage detection means; and the overvoltage detection means. An over/under voltage relay comprising: a means for detecting undervoltage, an undervoltage detecting means, a counting means, and a power supply means for supplying power to the output means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25429084A JPS61132032A (en) | 1984-11-30 | 1984-11-30 | Relay for excessive or short voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25429084A JPS61132032A (en) | 1984-11-30 | 1984-11-30 | Relay for excessive or short voltage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61132032A true JPS61132032A (en) | 1986-06-19 |
| JPH0519373B2 JPH0519373B2 (en) | 1993-03-16 |
Family
ID=17262909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25429084A Granted JPS61132032A (en) | 1984-11-30 | 1984-11-30 | Relay for excessive or short voltage |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61132032A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014199724A (en) * | 2013-03-29 | 2014-10-23 | パナソニック株式会社 | Undervoltage tripper for circuit breaker and overvoltage/undervoltage tripper |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5649230U (en) * | 1979-09-25 | 1981-05-01 | ||
| JPS57187256A (en) * | 1981-05-02 | 1982-11-17 | Heidelberger Druckmasch Ag | Electric safety device controlling printer |
-
1984
- 1984-11-30 JP JP25429084A patent/JPS61132032A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5649230U (en) * | 1979-09-25 | 1981-05-01 | ||
| JPS57187256A (en) * | 1981-05-02 | 1982-11-17 | Heidelberger Druckmasch Ag | Electric safety device controlling printer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014199724A (en) * | 2013-03-29 | 2014-10-23 | パナソニック株式会社 | Undervoltage tripper for circuit breaker and overvoltage/undervoltage tripper |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0519373B2 (en) | 1993-03-16 |
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