JPS61129853A - Manufacture of hybrid ic - Google Patents
Manufacture of hybrid icInfo
- Publication number
- JPS61129853A JPS61129853A JP59252403A JP25240384A JPS61129853A JP S61129853 A JPS61129853 A JP S61129853A JP 59252403 A JP59252403 A JP 59252403A JP 25240384 A JP25240384 A JP 25240384A JP S61129853 A JPS61129853 A JP S61129853A
- Authority
- JP
- Japan
- Prior art keywords
- titanium
- pattern
- substrate
- thin film
- treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
- H01L27/013—Thick-film circuits
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路の製造方法、特に信頼性の優れ念
高品質なタンタル薄膜ＲＣ回路の製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a hybrid integrated circuit, and particularly to a method for manufacturing a tantalum thin film RC circuit of excellent reliability and high quality.
従来、同一絶縁基板上に形成された薄膜コンデンサと薄
膜抵抗からなる薄膜回路の製造方法は、大路次のとおり
である。先ずガラス又はセラミック等の絶縁基板上にベ
ータ又はアルファーメンタル層をスパッタ法によシ被着
させ該タンタル層を選択エツチングにより所望のコンデ
ンサーパターンを形成する。次にコンデンサとして用い
るべく定められた領域中の該タンタル層を選択的に陽極
酸化し、エツチングストップ層を形成し、この後、基板
金体くスパッター法により抵抗体用タンタル薄膜層を被
着し、続いてチタン金属層を被着させる。次に該チタン
金属及び抵抗体用メンタル層をフォトレジスト処理及び
エツチング技術により段階的選択処理し、所望とするパ
ターンを形成する。Conventionally, a method for manufacturing a thin film circuit consisting of a thin film capacitor and a thin film resistor formed on the same insulating substrate is as follows. First, a beta or alpha layer is deposited on an insulating substrate such as glass or ceramic by sputtering, and the tantalum layer is selectively etched to form a desired capacitor pattern. Next, the tantalum layer in the area defined to be used as a capacitor is selectively anodized to form an etching stop layer, and then a tantalum thin film layer for the resistor is deposited on the metal substrate by sputtering. , followed by the deposition of a titanium metal layer. Next, the titanium metal and the resistor mental layer are selectively processed in stages by photoresist processing and etching techniques to form a desired pattern.
次にチタン金属パターンを保護マスクとしメンタ
゛ル抵抗パターンを大気中で熱酸化した後、チタン保護
マスクを硫酸ボイル処理によシ除去し、コンデンサ領域
の所定の箇所をフォトレジス）１−保護マスクとし、再
び陽極酸化し、マスクを公知の方法で剥離する。次に上
記により得られた基板全体にニクロム合金、パラジュー
ム、金から成る上部電極を被着させ、フォトレジスト処
理によシ所望のパターンを形成した後、タンタル抵抗パ
ターン面を陽極酸化又はレーザトリミング方法によシ所
望の抵抗値に調節することＫよ）薄ｊｉ［３０回路を製
造していた。Next, use the titanium metal pattern as a protective mask and use a mentor.
After thermally oxidizing the resistor pattern in the atmosphere, the titanium protective mask is removed by sulfuric acid boiling treatment, a predetermined portion of the capacitor area is made into a photoresist (1) protective mask, and the mask is anodized again. Peel it off using the following method. Next, an upper electrode made of nichrome alloy, palladium, and gold is deposited on the entire substrate obtained above, and a desired pattern is formed by photoresist treatment, and then the tantalum resistor pattern surface is anodized or laser trimmed. (Please adjust the resistance to the desired value.)Thin 30 circuits were manufactured.
上述した従来の製造方法は、チタン金属を保護マスクと
し、タンタル抵抗パターン面を大気中で熱処理する工程
に於いて該チタン保護マスクをフォトレジスト処理及び
エツチング処理によシ形成し、公知の方法でフォトレジ
ストを剥離除去するが、この方法ではチタン保饅マスク
パターン上には有機残渣を完全に除去することはできず
、この状態で大気中で熱処理するため、パターン上に有
機残渣が焼付き、次工程の硫酸ボイル処理でのチタンマ
スクの除去が非常に困難となシ、チタンエツチング残シ
となる。この状態の上に上部電極膜が被着されることＫ
なる。このようＫして得られ九電極膜は下層薄膜との密
着性が著しく劣り、電極膜表面に熱圧着ボンディングす
る外部リードの接合強度が低下するという大きな欠点が
ある。The conventional manufacturing method described above uses titanium metal as a protective mask, and in the process of heat-treating the tantalum resistor pattern surface in the atmosphere, the titanium protective mask is formed by photoresist treatment and etching treatment, and then the titanium protective mask is formed by a known method. The photoresist is peeled off, but this method cannot completely remove the organic residue on the titanium protective mask pattern, and since it is heat-treated in the air in this state, the organic residue is burned onto the pattern. It is very difficult to remove the titanium mask in the next step of sulfuric acid boiling, leaving a titanium etching residue. The upper electrode film is deposited on top of this state.
Become. The nine-electrode film obtained in this manner has a major drawback in that its adhesion to the underlying thin film is extremely poor, and the bonding strength of the external lead bonded to the surface of the electrode film by thermocompression is reduced.
本発明の目的はウェット処理でのフォトレジスト剥離で
は避けられない有機残渣が原因となる上記製造方法の欠
点を是正した新しい混成集積回路の製造方法を提供する
ことＫある。即ち、本発明は、所望とするチタン保護マ
スクパターン及びメンタル抵抗ハターンをフォトレジス
ト及ヒエツチング処理によシ段階的に形成した後、パタ
ーン上のフォトレジストをウェット方式によシ剥離し、
次にパターン面を紫外線洗浄処理を施し、大気中で熱処
理するととを特徴とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a new method for manufacturing a hybrid integrated circuit, which corrects the drawbacks of the above manufacturing method caused by organic residues that are unavoidable in photoresist stripping by wet processing. That is, in the present invention, after forming a desired titanium protective mask pattern and a mental resistance pattern in stages by a photoresist and etching process, the photoresist on the pattern is peeled off by a wet method.
Next, the patterned surface is subjected to ultraviolet cleaning treatment and heat treated in the atmosphere.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）乃至第１図（０１は本発明の一実施例の断
面図である。充分に洗浄された絶縁基板１上にスパッタ
リング法によシタンタル系薄膜２ｔ−約４，０００人の
厚さく形成する（第１図（ａ））。次ＫＡ知のエツチン
グ法に基づいてタンタル系薄膜２ｔ−除去し、所望のコ
ンデンサーパターンを形成する（第１図（ｂ））。次に
ポジ型フォトレジスト３を約１０〜１３μｍの厚さに塗
布した後、１００℃、３０分のプリベークを施し、この
フォトレジストを露光、現偉シ、所望のフォトレジスト
パターンを形成する（第１図（Ｃ））。次に前記基板ｔ
−０，０１％クエン酸溶液中で陽極酸化することによシ
誘電体となるべき箇所に酸化膜を形成し、タンタルエツ
チング液のエツチング液のエツチングストップ層４を形
成する（第１図（ｄ））。次にスパッタリング法によシ
抵抗体用メンタル系薄膜５（例えば窒化タンタル又は酸
素ドープ窒化タンタル）及びチタン金属薄膜６を基板上
全面に付着せしめ（第１図（６） ） 、フォトレジス
ト及びエツチング処理によシ選択的に所望の抵抗パター
ン及びチタン保護マスクパターンを形成する（第１図（
ｆ）〜（ｈ））。次に上記パターン上のフォトレジスト
を剥離液例えば東京応化製のＯＭＲ剥離液÷５０２を用
いて除去した後、波長１８４．９ｎｍの紫外線７を照射
し、チタン金属面及び抵抗パター、ン面上の有機残渣を
分解除去する（第１図（ｉ））。次に前記チタン金属膜
を保護マスクとしてタンタル抵抗パターン面を大気中”
ｔ’３００〜３５０℃の熱処理をした後（第１図（ｊ）
）、表面に酸化チタン８が生成されたチタン保護マスク
を１８９℃硫酸中で除去する（第１図（ｋ））。次に前
述と同様の方法でポジ型フォトレジストを塗布し、エツ
チングストップ層が露出する様にフォトレジストパター
ンを形成し九後（第１図（ｊり）、再度０．０１％クエ
ン酸溶液中で陽極酸化することＫよシ陽極酸化膜９を形
成する（第１図−）。次に基板全体にスパッタリング法
によシェフロム合金属１０．パラジューム１１．金層１
２を付着せしめ公知のフォトレジスト及びエツチング処
理によりコンデンサ及び抵抗を含む回路網を形成する（
第１図（ｎ））。最後に１５０℃又２５０℃大気中で５
時間の熱処理を施した後、レーザトリミング法により所
望の抵抗値に調節を行う。1(a) to 1(01) are cross-sectional views of one embodiment of the present invention. A tantalum-based thin film 2t is deposited on a thoroughly cleaned insulating substrate 1 by sputtering. The tantalum thin film 2t is removed based on the etching method known by KA to form a desired capacitor pattern (Fig. 1(b)).Next, a positive type capacitor is formed. After applying photoresist 3 to a thickness of approximately 10 to 13 μm, prebaking is performed at 100° C. for 30 minutes, and this photoresist is exposed to light to form a desired photoresist pattern (see Fig. 1 (C). )) Next, the substrate t
An oxide film is formed at the location to become a dielectric by anodizing in a -0.01% citric acid solution, and an etching stop layer 4 for tantalum etching solution is formed (see Fig. 1 (d). )). Next, a resistor thin film 5 (for example, tantalum nitride or oxygen-doped tantalum nitride) and a titanium metal thin film 6 are deposited on the entire surface of the substrate by sputtering (see FIG. 1 (6)), followed by photoresist and etching treatment. A desired resistor pattern and a titanium protective mask pattern are selectively formed (see FIG. 1).
f) to (h)). Next, the photoresist on the above pattern is removed using a stripping solution such as OMR stripping solution ÷502 manufactured by Tokyo Ohka, and then UV 7 with a wavelength of 184.9 nm is irradiated to remove the photoresist on the titanium metal surface and the resistor pattern surface. The organic residue is decomposed and removed (FIG. 1(i)). Next, using the titanium metal film as a protective mask, the tantalum resistor pattern surface was exposed to the atmosphere.
After heat treatment at t'300 to 350°C (Fig. 1 (j)
), the titanium protective mask with titanium oxide 8 formed on its surface is removed in sulfuric acid at 189° C. (FIG. 1(k)). Next, a positive photoresist was applied in the same manner as described above, and a photoresist pattern was formed so that the etching stop layer was exposed. An anodic oxide film 9 is formed by anodizing with K (see Fig. 1).Next, a Scheffrom alloy 10, palladium 11, and gold layer 1 are deposited on the entire substrate by sputtering.
2 is deposited and a circuit network including capacitors and resistors is formed by a known photoresist and etching process (
Figure 1(n)). Finally, at 150℃ or 250℃ in the atmosphere,
After heat treatment for a period of time, the resistance value is adjusted to a desired value by laser trimming.
以上説明したように本発明は、抵抗体用タンタル薄膜パ
ターンをチタン金属膜を保護マスクとして大気中で高温
熱処理する際あらかじめ紫外線処理を施し抵抗パターン
とチタン保護マスク上の有機残渣を除去することＫよ９
１８９℃硫酸処理でのチタン金属除去が容易となり、従
来の方法では避けられなかつたチタン金属膜長シによる
外部リードボンディングでの密着不良が解消され信頼性
の優れた高品質な混成集積回路の製造が可能となった。As explained above, the present invention provides a method for removing organic residues on the resistor pattern and the titanium protective mask by applying ultraviolet light treatment in advance when subjecting the tantalum thin film pattern for a resistor to high-temperature heat treatment in the atmosphere using a titanium metal film as a protective mask. Yo9
Titanium metal can be easily removed by 189°C sulfuric acid treatment, and poor adhesion in external lead bonding due to titanium metal film length, which was unavoidable with conventional methods, has been eliminated, making it possible to manufacture high-quality hybrid integrated circuits with excellent reliability. became possible.
第１図（ａｌ乃至第１図（ｎｌは本発明の詳細な説明す
るための混成集積回路の製造工程の断面図である。１・
・・・・・絶縁基板、２・・・・・・タンタル系薄膜、
３・・・・・・ポジ型フォトレジスト、４・・・・・・
エツチングストップ層、５・・・・・・抵抗体、６・・
・・・・チタン金属膜、７・・・・・・紫外線、８・・
・・・・チタン酸化物、９・・・・・・陽極酸化膜、１
０・・・・・・ニクロム合金層、１１・・・・・・パラ
ジ、−ム層、１２・・・・・・金層、である。
沼（ビ
卒１回1 (al to 1 (nl) are cross-sectional views of the manufacturing process of a hybrid integrated circuit for explaining the present invention in detail. 1.
...Insulating substrate, 2...Tantalum-based thin film,
3...Positive photoresist, 4...
Etching stop layer, 5...Resistor, 6...
...Titanium metal film, 7...Ultraviolet light, 8...
...Titanium oxide, 9...Anodic oxide film, 1
0...nichrome alloy layer, 11...palladium layer, 12...gold layer. Swamp (1 time B graduate)
Claims (1)
金属薄膜を保護マスクとし、大気中で高温熱処理する工
程に於いて、該保護マスクをフォトレジスト処理により
形成し、該パターン面を紫外線洗浄処理し、有機残渣を
除去した後、熱処理することを特徴とした混成集積回路
の製造方法。In the step of heat-treating a part of the tantalum-based thin film formed on the insulating substrate using a titanium metal thin film as a protective mask in the atmosphere at high temperature, the protective mask is formed by photoresist treatment, and the patterned surface is subjected to ultraviolet cleaning treatment. A method for manufacturing a hybrid integrated circuit, comprising: removing organic residue, and then performing heat treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59252403A JPS61129853A (en) | 1984-11-29 | 1984-11-29 | Manufacture of hybrid ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59252403A JPS61129853A (en) | 1984-11-29 | 1984-11-29 | Manufacture of hybrid ic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61129853A true JPS61129853A (en) | 1986-06-17 |
Family
ID=17236850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59252403A Pending JPS61129853A (en) | 1984-11-29 | 1984-11-29 | Manufacture of hybrid ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61129853A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7059041B2 (en) * | 2000-08-14 | 2006-06-13 | United Monolithic Semiconductors Gmbh | Methods for producing passive components on a semiconductor substrate |
| CN114040598A (en) * | 2021-11-02 | 2022-02-11 | 江门崇达电路技术有限公司 | Method for removing flash of metalized half hole of electric gold plate |
-
1984
- 1984-11-29 JP JP59252403A patent/JPS61129853A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7059041B2 (en) * | 2000-08-14 | 2006-06-13 | United Monolithic Semiconductors Gmbh | Methods for producing passive components on a semiconductor substrate |
| CN114040598A (en) * | 2021-11-02 | 2022-02-11 | 江门崇达电路技术有限公司 | Method for removing flash of metalized half hole of electric gold plate |
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