JPS61125150A - Manufacture of three dimensional semiconductor device - Google Patents
Manufacture of three dimensional semiconductor deviceInfo
- Publication number
- JPS61125150A JPS61125150A JP24631084A JP24631084A JPS61125150A JP S61125150 A JPS61125150 A JP S61125150A JP 24631084 A JP24631084 A JP 24631084A JP 24631084 A JP24631084 A JP 24631084A JP S61125150 A JPS61125150 A JP S61125150A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- layer
- forming
- film
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、３次元半導体装置の製造方法に係わり、特に
層間接続の改良をはかった３次元半導体装置の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a three-dimensional semiconductor device, and particularly to a method for manufacturing a three-dimensional semiconductor device that improves interlayer connections.
最近、電子ビームやレーザ・アニールによって絶縁膜上
にＳｉ単結晶を形成する技術（所謂Ｓｏｌ技術）の開発
が盛んに行われている。更に、Ｓｉウェハ表面に形成さ
れた素子（下層素子）上に層間絶縁膜を形成したのち、
該ＳＯＩ技術によって形成された単結晶３ｉ層を形成す
る。しかるのちに、該単結晶層に素子（上層素子）を形
成し、２層素子構造を形成することが可能となっている
。Recently, a technology for forming a Si single crystal on an insulating film using an electron beam or laser annealing (so-called Sol technology) has been actively developed. Furthermore, after forming an interlayer insulating film on the elements (lower layer elements) formed on the Si wafer surface,
A single crystal 3i layer formed by the SOI technique is formed. Thereafter, an element (upper layer element) is formed on the single crystal layer, making it possible to form a two-layer element structure.
ところで、多層素子構造における層間接続は、第２図に
示すように、上下層の素子を形成したのらに行う方法が
採られている。しかし、該接続方法を用いると、上ｗ４
素子形成後に接続用コンタクトホール２９を開孔する際
に、上下素子及び軸間絶縁膜１６．２４のそれぞれの厚
さ分の絶縁膜、を□、
エツチングする必要がある。このように深い穴を一度に
開孔するためには、開孔面積が大きくなり、素子面積を
大きくしてしまう。また、３！＝４層とより多層化した
場合、Ｒ１５に一度に開孔することは殆ど不可能となる
。従って、埋込み配線技術により、各層素子と平行して
、各層毎に埋込んでゆく必要がある。By the way, as shown in FIG. 2, interlayer connections in a multilayer element structure are performed after forming the elements of the upper and lower layers. However, using this connection method, the upper w4
When forming the connection contact hole 29 after forming the element, it is necessary to etch the insulating film by the thickness of each of the upper and lower elements and the inter-axis insulating film 16, 24. In order to open such deep holes at once, the area of the holes becomes large, which increases the area of the device. Also, 3! When the number of layers is increased to 4, it becomes almost impossible to open a hole in R15 at once. Therefore, it is necessary to embed each layer in parallel with the elements in each layer using the embedding wiring technique.
しかしながら、各層毎に埋込み配線を形成する場合、第
３図に示す如く埋込み配線１８の上端が５ＯＩＩｆ＊２
０と直接接触することになる。このため、ビームアニー
ルによって溶融・再結晶化する際、前記接触部での下部
への熱伝導が層間絶縁膜１６上より大きくなり、再結晶
化が速く、Ｓｏｌ膜の多結晶化３１を引き起こす。これ
により、上層素子の特性劣化を招く虞れがあった。However, when forming buried wiring for each layer, the upper end of the buried wiring 18 is 5OIIf*2 as shown in FIG.
0 will come into direct contact. Therefore, when melting and recrystallizing by beam annealing, heat conduction to the lower part at the contact portion is greater than that on the interlayer insulating film 16, recrystallization is rapid, and polycrystallization 31 of the Sol film is caused. This may lead to deterioration of the characteristics of the upper layer element.
（発明の目的〕
本発明の目的は、唐間Ｐ＠縁膜上のシリコン層の単結晶
化を妨げることなく、上下層の素子間接続のためのコン
タクトホールを容易に開孔することができ、ｍｍ度の向
上及び上層素子の素子特性向上等をはかりＬ９る３次元
半導体の製造方法を提供することにある。(Objective of the Invention) An object of the present invention is to easily form a contact hole for connection between elements in the upper and lower layers without hindering the single crystallization of the silicon layer on the Karama P@edge film. An object of the present invention is to provide a method for manufacturing a three-dimensional semiconductor, which improves the degree of L9, mm, and the characteristics of upper layer elements.
本発明の骨子は、３０１ｙＩの多結晶化の要因となる埋
込み配線と層間絶縁膜上に堆積するシリコン簿膜との接
触を防止することにある。The gist of the present invention is to prevent contact between the buried wiring and the silicon film deposited on the interlayer insulating film, which causes polycrystallization of 301yI.
即ち本発明は、半導体素子を積層してなる３次元半導体
装置の製造方法において、下層素子及び第１の層間絶縁
膜を形成したのち該絶縁膜に層間接続のためのコンタク
トホー・ルを開孔し、このコンタクトホール内に埋込み
ｉｉ！線を形成し、次いで全面に厚さ０，２（μＴｒＬ
］以下の保護用絶縁膜を形成した後肢保護用絶縁膜上に
単結晶シリコン層を形成するし、次いでこの単結晶シリ
コン層上に上層素子を形成した後肢上層素子上に第２の
膚間絶ｎ膜を形成し、しかるのら上記第２の層間絶縁膜
及び保護用絶縁膜に前記埋込み配線の上端部までコンタ
クトホールを開孔し、上下層素子を配線により接続する
ようにした方法である。That is, the present invention provides a method for manufacturing a three-dimensional semiconductor device formed by stacking semiconductor elements, in which a lower layer element and a first interlayer insulating film are formed, and then a contact hole for interlayer connection is formed in the insulating film. and embed it in this contact hole ii! A line is formed, and then a thickness of 0.2 (μTrL) is formed on the entire surface.
] A single crystal silicon layer is formed on the hindlimb protection insulating film on which the following protective insulating film is formed, and then a second skin barrier layer is formed on the hindlimb upper layer element with the upper layer element formed on this single crystal silicon layer. In this method, a contact hole is formed in the second interlayer insulating film and the protective insulating film up to the upper end of the buried wiring, and the upper and lower layer elements are connected by the wiring. .
本発明によれば、各層の素子毎に埋込み配線を形成して
いるので、層間接続のためのコンタクトホールの深さを
浅＜（ｉｆ！１１１！：縁１１！Ｊ１層分の厚さ）する
ことができ、その加工が容易となり集積度の向上に有効
である。さらに、多層化してもコンタクトホール深さは
増えないので、多層化にも十分適合できる。また、埋込
み配線の上端部がＳＯ■膜に直接接触していないので、
ＳＯＩ膜の単結晶化に対しては、ビームアニール等によ
る！！！結晶化工程で不均一アニールが生じ、一部子結
晶する等の不都合はない。このため、上層素子の素子特
性の向上をはかり得る。According to the present invention, since embedded wiring is formed for each element in each layer, the depth of the contact hole for interlayer connection is shallow<(if!111!: thickness of edge 11!J1 layer). This makes processing easier and is effective in improving the degree of integration. Furthermore, since the depth of the contact hole does not increase even if the structure is multilayered, it is fully suitable for multilayering. In addition, since the upper end of the embedded wiring does not directly contact the SO film,
For single crystallization of SOI film, use beam annealing, etc.! ! ! There are no inconveniences such as non-uniform annealing occurring in the crystallization process and single-molecule crystallization. Therefore, it is possible to improve the element characteristics of the upper layer element.
以下、本発明の詳細を図示の実施例によって説明する。 Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.
第１図（ａ）〜（「）は本発明の一実施例に係わる３次
元半導体装置の製造工程を示す断面図である。まず、第
１図（ａ）に示す如くＰ型単桔品Ｓ１基板１１の素子分
離領域上にフィールド絶縁膜１２を形成し、素子形成領
域上にゲート酸化膜１３、ゲート電極１４及びソース・
ドレイン順賊５ａ、１５ｂからなるＮチャンネルＭＯＳ
トランジスタ（下層素子）を形成した。次いで、第１図
（ｂ）に示す如く全面に厚さ１［μＴｒＬ］の第１の層
間絶縁膜１６を形成し、写真蝕刻法等により１．５［μ
ｍφ］のコンタクトホール１７を開孔した、続いて、層
間接続配線となる導電膜、例えばリン添加多結晶３ｉを
全面に厚さ０．８［μ７７Ｌ］形成し、エッチバック法
等により埋込み配線１８を形成した。1(a) to 1(') are cross-sectional views showing the manufacturing process of a three-dimensional semiconductor device according to an embodiment of the present invention. First, as shown in FIG. 1(a), a P-type single frame product S1 A field insulating film 12 is formed on the element isolation region of the substrate 11, and a gate oxide film 13, a gate electrode 14 and a source film are formed on the element forming region.
N-channel MOS consisting of drain Junki 5a and 15b
A transistor (lower layer element) was formed. Next, as shown in FIG. 1(b), a first interlayer insulating film 16 having a thickness of 1 [μTrL] is formed on the entire surface, and a thickness of 1.5 [μTrL] is formed by photolithography or the like.
A contact hole 17 of [mφ] was opened, and then a conductive film that would become an interlayer connection wiring, for example, a phosphorus-doped polycrystalline 3i, was formed to a thickness of 0.8 [μ77L] over the entire surface, and a buried wiring 18 was formed by an etch-back method or the like. was formed.
次に、第１図（Ｃ）に示す如く全面に厚さ０．２ ［μ
ｌのＣＶＤ−８ｉ ０２ ｍ （保護用絶縁ＩＦＪ）、
１９を形成し、この５ｉ０２膜１９上にＳＯｔ用多用品
結晶３ｉ模２０さ０．６Ｅμ７７Ｌ］に形成した。次い
で、この多結晶Ｓ１膜２０を電子ビームアニール若しく
はレーザアニール等により単結晶化した。ここで、上記
多結晶３ｉ膜２０が前記埋込み配線１８と接触していな
いので、均一アニールを行うことができ、良質の単結晶
３ｉ層２０′を得ることができた。Next, as shown in FIG. 1(C), a layer with a thickness of 0.2 [μ
l CVD-8i 02 m (protective insulation IFJ),
19 was formed, and on this 5i02 film 19, a general purpose crystal 3i pattern 20 (0.6Eμ77L) for SOt was formed. Next, this polycrystalline S1 film 20 was made into a single crystal by electron beam annealing, laser annealing, or the like. Here, since the polycrystalline 3i film 20 was not in contact with the buried wiring 18, uniform annealing could be performed and a high quality single crystal 3i layer 20' could be obtained.
次に、第１図（ｄ）に示す如く単結晶Ｓｉ膜２０’上に
ゲートｎ化膜２１．ゲート電極２２及びソース・ドレイ
ン１ｔａ２３ａ、２３ｂを形成してＰチャンネルＭＯＳ
トランジスタ（上層素子）を形成した。次いで、第１図
（ｅ）に示す如く全面に厚さ１．２ ［μｌのＣＶＤ−
８ｉ０２膜（第２の層間絶縁膜）２４を形成し、表面平
坦化を行った。続いて、ＲＩＥ（リアクティブ・イオン
・エツチング）法等を用いてコンタクトホール２５を開
孔した。その後、第１図（ｆ）に示す如くリン添加多結
晶Ｓｉ等からなる配線層２６を形成し、上下層の素子間
接続を行うことによって３次元半導体装置が完成するこ
とになる。Next, as shown in FIG. 1(d), a gate n-oxide film 21 is placed on the single crystal Si film 20'. A P-channel MOS is formed by forming the gate electrode 22 and source/drain 1ta23a, 23b.
A transistor (upper layer element) was formed. Next, as shown in FIG.
An 8i02 film (second interlayer insulating film) 24 was formed and the surface was planarized. Subsequently, a contact hole 25 was formed using RIE (reactive ion etching) or the like. Thereafter, as shown in FIG. 1(f), a wiring layer 26 made of phosphorus-doped polycrystalline Si or the like is formed and connections are made between elements in the upper and lower layers, thereby completing a three-dimensional semiconductor device.
かくして本実施例方法によれば、第１図（Ｃ）に示す工
程において、埋込み配置１８の上端が多結晶Ｓｉ膜２０
接触していないので、多結晶Ｓｉ膜２０の単結晶化を効
果的に行うことができ、良質の単結晶３ｉ膜２０’ を
形成することができる。Thus, according to the method of this embodiment, in the step shown in FIG.
Since there is no contact, the polycrystalline Si film 20 can be effectively single-crystallized, and a high-quality single-crystal 3i film 20' can be formed.
このため、該単結晶Ｓｉ膜２り′上に形成する上層素子
の素子特性向上をはかり得る。さらに、コンタクトホー
ルの開孔に際しては、眉間絶縁膜１６．２４の１層の深
さエツチングすればよいので、コンタクトホールの開孔
面積を小さくすることができる。このため、集積度の向
上にも有効である。Therefore, it is possible to improve the device characteristics of the upper layer device formed on the single crystal Si film 2'. Further, when forming the contact hole, it is sufficient to etch the glabella insulating film 16, 24 to a depth of one layer, so that the area of the contact hole can be reduced. Therefore, it is also effective in improving the degree of integration.
なお、本発明は上述した実施例に限定されるものではな
い。例えば、前記埋込み配線層はリン添加多結晶シリコ
ンに限るものではなく、コンタクトホールを埋込める技
術であれば高融点金属或いは多層膜でもよい。また、上
下層の配線接続には−込み配線とＡｌ１による平面配線
を用いることもできる。その他、本発明の要旨を逸脱し
ない範囲丙で、種々の変形して実施することができる。Note that the present invention is not limited to the embodiments described above. For example, the buried wiring layer is not limited to phosphorus-doped polycrystalline silicon, but may be a high melting point metal or a multilayer film as long as the technology allows burying the contact hole. Moreover, embedded wiring and planar wiring made of Al1 can also be used for wiring connections between the upper and lower layers. In addition, various modifications can be made without departing from the gist of the present invention.
第１図（ａ）〜（ｆ）は本発明の一実施例方法ド係わる
３次元半導体装置の製造工程を示す断面図、第２図は従
来装置の概略構造を示す断面図、第３図は従来の問題点
を説明するための模式図である。
１１・・・単結晶＄１基板、１２・・・フィールド絶縁
膜、１３・・・下層ゲート酸化膜、１４・・・下層ゲー
ト電極、１５ａ、１５ｂ・・・下層ソース・ドレイン領
域、１６・・・第１の層間絶縁膜、１７．２５・・・コ
ンタクトホール、１８・・・埋込み配線層、１９・・・
保護用絶縁膜、２０・・・多結晶３ｉ膜、２０′・・・
単結晶ＳｉｗＡ（Ｓｏｌ膜） 、 ２１ ・ｆｌｔ’７
’−ト１ｆ＆、２２・・・上層ゲート電極、２３ａ、２
３ｂ・・・上層ソース・ドレイン領域、２４・・・第２
の層間絶縁膜、２６・・・配線層。
出願人 工業技術院長 等々力 達
第１図
第１図
第１図
第２図FIGS. 1(a) to (f) are cross-sectional views showing the manufacturing process of a three-dimensional semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the schematic structure of a conventional device, and FIG. It is a schematic diagram for explaining the conventional problem. DESCRIPTION OF SYMBOLS 11... Single crystal $1 substrate, 12... Field insulating film, 13... Lower layer gate oxide film, 14... Lower layer gate electrode, 15a, 15b... Lower layer source/drain region, 16...・First interlayer insulating film, 17.25... Contact hole, 18... Buried wiring layer, 19...
Protective insulating film, 20... Polycrystalline 3i film, 20'...
Single crystal SiwA (Sol film), 21 ・flt'7
'-T 1f&, 22... Upper layer gate electrode, 23a, 2
3b... Upper source/drain region, 24... Second
interlayer insulating film, 26... wiring layer. Applicant: Director of the Agency of Industrial Science and Technology Tatsu Todoroki Figure 1 Figure 1 Figure 2
Claims (2)
造方法において、下層素子及び第１の層間絶縁膜を形成
したのち該絶縁膜に層間接続のためのコンタクトホール
を開孔する工程と、上記コンタクトホール内に埋込み配
線を形成する工程と、次いで全面に厚さ０．２［μｍ］
以下の保護用絶縁膜を形成する工程と、上記保護用絶縁
膜上に単結晶シリコン層を形成する工程と、上記単結晶
シリコン層上に上層素子を形成する工程と、上記上層素
子上に第２の層間絶縁膜を形成する工程と、上記第２の
層間絶縁膜及び保護用絶縁膜に前記埋込み配線の上端部
までコンタクトホールを開孔し上下層素子を配線により
接続する工程とを含むことを特徴とする３次元半導体装
置の製造方法。(1) In a method for manufacturing a three-dimensional semiconductor device formed by stacking semiconductor elements, a step of forming a lower layer element and a first interlayer insulating film and then opening a contact hole for interlayer connection in the insulating film; A step of forming a buried wiring in the above contact hole, and then a thickness of 0.2 [μm] on the entire surface.
The following steps include forming a protective insulating film, forming a single crystal silicon layer on the protective insulating film, forming an upper layer element on the single crystal silicon layer, and forming a second layer on the upper layer element. forming a second interlayer insulating film; and forming a contact hole in the second interlayer insulating film and the protective insulating film up to the upper end of the buried wiring, and connecting the upper and lower layer elements by wiring. A method for manufacturing a three-dimensional semiconductor device, characterized by:
る工程として、前記保護用絶縁膜及び第１の層間絶縁膜
に結晶方位制御のための開孔部を形成したのち、全面に
多結晶若しくは非晶質のシリコン薄膜を堆積し、次いで
このシリコン膜を電子ビームアニール若しくはレーザア
ニールにより単結晶化することを特徴とする特許請求の
範囲第１項記載の３次元半導体装置の製造方法。(2) In the step of forming a single crystal silicon layer on the protective insulating film, after forming an opening for crystal orientation control in the protective insulating film and the first interlayer insulating film, a polycrystalline silicon layer is formed on the entire surface. A method for manufacturing a three-dimensional semiconductor device according to claim 1, characterized in that a crystalline or amorphous silicon thin film is deposited, and then this silicon film is made into a single crystal by electron beam annealing or laser annealing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24631084A JPS61125150A (en) | 1984-11-22 | 1984-11-22 | Manufacture of three dimensional semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24631084A JPS61125150A (en) | 1984-11-22 | 1984-11-22 | Manufacture of three dimensional semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61125150A true JPS61125150A (en) | 1986-06-12 |
| JPH023301B2 JPH023301B2 (en) | 1990-01-23 |
Family
ID=17146648
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24631084A Granted JPS61125150A (en) | 1984-11-22 | 1984-11-22 | Manufacture of three dimensional semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61125150A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0613575A (en) * | 1990-07-31 | 1994-01-21 | Internatl Business Mach Corp <Ibm> | Stack-type semiconductor structure and formation thereof |
| US5489554A (en) * | 1992-07-21 | 1996-02-06 | Hughes Aircraft Company | Method of making a 3-dimensional circuit assembly having electrical contacts that extend through the IC layer |
| US7375401B2 (en) | 1996-02-23 | 2008-05-20 | Semiconductor Energy Laboratory Co., Ltd. | Static random access memory using thin film transistors |
-
1984
- 1984-11-22 JP JP24631084A patent/JPS61125150A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0613575A (en) * | 1990-07-31 | 1994-01-21 | Internatl Business Mach Corp <Ibm> | Stack-type semiconductor structure and formation thereof |
| US5489554A (en) * | 1992-07-21 | 1996-02-06 | Hughes Aircraft Company | Method of making a 3-dimensional circuit assembly having electrical contacts that extend through the IC layer |
| US7375401B2 (en) | 1996-02-23 | 2008-05-20 | Semiconductor Energy Laboratory Co., Ltd. | Static random access memory using thin film transistors |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH023301B2 (en) | 1990-01-23 |
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