JPS61123175A - Manufacture of hetero-junction bipolar transistor - Google Patents
Manufacture of hetero-junction bipolar transistorInfo
- Publication number
- JPS61123175A JPS61123175A JP24323684A JP24323684A JPS61123175A JP S61123175 A JPS61123175 A JP S61123175A JP 24323684 A JP24323684 A JP 24323684A JP 24323684 A JP24323684 A JP 24323684A JP S61123175 A JPS61123175 A JP S61123175A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- base
- emitter
- bipolar transistor
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 8
- 150000001875 compounds Chemical class 0.000 claims description 4
- 229910052749 magnesium Inorganic materials 0.000 claims description 2
- 229910052725 zinc Inorganic materials 0.000 claims description 2
- 229910052793 cadmium Inorganic materials 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 11
- 230000010354 integration Effects 0.000 abstract description 5
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract description 2
- 238000000137 annealing Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract 3
- 229910001425 magnesium ion Inorganic materials 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は化合物半導体を用いたヘテロ接合バイポーラト
ランジスタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a heterojunction bipolar transistor using a compound semiconductor.
Ｇａｐｓ等の化合物半導体を用いたヘテロ接合バイポー
ラトランジスタは次代の高速デバイスとして注目されて
いる。ヘテロ接合バイポーラトランジスタは極めて薄い
ベース層と良質なヘテロ接合の形成が不可欠であり、現
在分子線エピタキシー（ＭＢＥ）法、有機金属気相成長
（ＭＯＣｖＤ）法等のエピタキシャル成長技術が用いら
れている。コレクタ、ベース、エミッタとなる半導体層
をエピタキシャル成長させたウェハを用いてヘテロ接合
バイポーラトランジスタを形成する際（はコレクタ及び
エミッタの２つの半導体層にはさまれたベース層にコン
タクトを形成する必要があり、そのための方法の１つと
してイオン注入技術を用いて外部ベースを形成すること
が行なわれている。このバイポーラトランジスタにおい
てはエミッタ、ベース。Heterojunction bipolar transistors using compound semiconductors such as Gaps are attracting attention as next-generation high-speed devices. For a heterojunction bipolar transistor, it is essential to form an extremely thin base layer and a high-quality heterojunction, and epitaxial growth techniques such as molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCvD) are currently used. When forming a heterojunction bipolar transistor using a wafer on which semiconductor layers to become the collector, base, and emitter are epitaxially grown, it is necessary to form a contact on the base layer sandwiched between the two semiconductor layers, the collector and emitter. One method for this purpose is to use ion implantation technology to form an external base.In this bipolar transistor, the emitter and base are formed.
コレクタの各コンタクト抵抗の大小は素子性能に大きな
影響を及ぼすことは周知である。ヘテロ接合バイポーラ
トランジスタにおいても同様であり、イオン注入によっ
て形成した外部ベース上のべ−スコンタクト抵抗の低減
が求められている。It is well known that the magnitude of each contact resistance of the collector has a large effect on device performance. The same applies to heterojunction bipolar transistors, and there is a need to reduce the base contact resistance on the external base formed by ion implantation.
本発明の目的は微細化による高性能高集積化に適したヘ
テロ接合バイポーラトランジスタの製造方法を提供する
ことにある。An object of the present invention is to provide a method for manufacturing a heterojunction bipolar transistor suitable for high performance and high integration through miniaturization.
本発明にがかるヘテロ接合バイポーラトランジスタの製
造方法は、化合物半導体基板にエミッタ接合、コレクタ
接合の少なくとも一方がヘテロ接合となるように半導体
層をエミッタ、ベース、コレクタもしくはコレクタ、ベ
ース、エミッタ接合に順次エピタキシャル成長させたウ
ェハを用いて構成されるものであって、イオン注入によ
って外部ベースを形成するに際し、第一の不純物のイオ
ン注入によって外部ベースを形成し、さらに第２の不純
物をイオン注入して外部ベースの表面近傍を高濃度化す
ることによって外部ベースのコンタクト抵抗を低減せし
めたヘテロ接合バイポーラトランジスタを得ることを特
徴とする。The method for manufacturing a heterojunction bipolar transistor according to the present invention involves epitaxially growing a semiconductor layer on a compound semiconductor substrate in order of emitter, base, collector or collector, base, emitter junction so that at least one of the emitter junction and the collector junction becomes a heterojunction. When forming the external base by ion implantation, the external base is formed by ion-implanting a first impurity, and the external base is formed by ion-implanting a second impurity. The present invention is characterized by obtaining a heterojunction bipolar transistor in which the contact resistance of the external base is reduced by increasing the concentration near the surface of the transistor.
本発明により得られるヘテロ接合バイポーラトランジス
タは、外部ベース表面が高濃度層となっているため、素
子面積を縮小してもベースのコンタクト抵抗を低く抑え
られ、微細化による高性能高集積化が可能となる。Since the heterojunction bipolar transistor obtained by the present invention has a highly doped layer on the external base surface, the contact resistance of the base can be kept low even if the element area is reduced, and high performance and high integration can be achieved through miniaturization. becomes.
第１図はエミッタ接合にＡｌＧａＡｓ／ＧａＡｓのヘテ
ロ接合を用いた一実施例のヘテロ接合バイポーラトラン
ジスタの構造を示す。第２図（８１〜（ｃｌはその製造
工程を示す。以下その構造と製造工程を第２図 ′（ａ
ｌ〜ｆｃｌを参照して説明する。半絶縁性基板１１にコ
レクタ層となるｎｆｉＧａＡｓ層１２及びｎ型ＧａＡｓ
層１３、ベース層となるｐｆｉＧａＡｓ層１４、エミツ
タ層となるｎ 屋ｋｌＧａｋｓ層１５、エミッタのオー
ミックコンタクトを収りやすくするためのキャップ層と
なるｎ＋型ＧａＡｓ層１６を順次ＭＢＥ法によりエピタ
キシャル成長させる（第２図（ａ））。例えばｎ＋型Ｇ
ａＡｓ層１２は８ｉを２ Ｘ １０” ｃｍ−” ドー
プした５ｏｏｏＫのｎ＋層、ｎ型層１３は同じ（８ｉを
５ＸＩＯ１６ｃＩｒＬ−３ドープした５０００人のｎｆ
ｉ層とし、ｐｍ層１４はＢｅを３Ｘ１０”、−ｍ−３ド
ープした１０００λのｐ型層とし、ｎ型層１５は３ｉを
Ｉ Ｘ １０１？ｃｍ−”ドープしたｎ型層（ＡＪの％
に比は０．３）とし、ｎ＋層１６はＳｉｋ ２ ｘ １
０”ＣＩｒＬ−’ ）−−プした１０００λのｎ＋層と
する。次にエミッタ領域にマスク（図示せず）ｔｌ−形
成し、不要なｎ＋層をエツチング除去した後、Ｍｇを２
ｘｉＯ”ｃｍ−” ２００ＫｅＶ ティオン注入し、さ
らにＺｎを１ｘｌＯ”ｃｍ−２１００ＫｅＶでイオン注
入した後９００’０２秒の赤外線（よるフラッシュアニ
ールを施してｐ＋型の外部ベースを形成する（第２図（
ｂ））。この外部ベース層の深さ方向の濃度分布は第３
図に示すととくで表面から１００ＯＡの閑さまでは約９
Ｘ１０”ｃｍ−’ １０００λから５００ ＯＡの深さ
までは約７ Ｘ １０” ｃｍ−’のｐ型となる。FIG. 1 shows the structure of an embodiment of a heterojunction bipolar transistor using an AlGaAs/GaAs heterojunction for the emitter junction. Figure 2 (81~(cl) indicates its manufacturing process.The structure and manufacturing process are shown in Figure 2'(a
This will be explained with reference to l to fcl. A semi-insulating substrate 11 has an nfiGaAs layer 12 serving as a collector layer and an n-type GaAs layer.
The layer 13, the pfiGaAs layer 14 that will become the base layer, the n+ type GaAs layer 15 that will become the emitter layer, and the n+ type GaAs layer 16 that will become the cap layer to make it easier to fit the emitter ohmic contact are epitaxially grown by the MBE method. Figure 2(a)). For example, n+ type G
aAs layer 12 is a 5oooK n+ layer doped with 8i 2 X 10"cm-", n-type layer 13 is the same (5000nf 8i doped with 5XIO16cIrL-3)
The pm layer 14 is a 1000λ p-type layer doped with Be 3X10", -m-3, and the n-type layer 15 is a 1000λ p-type layer doped with 3i I x 101?cm-" (% of AJ).
The ratio is 0.3), and the n+ layer 16 is Sik 2 x 1
0"CIrL-')-- to form a 1000λ n+ layer. Next, a mask (not shown) tl- is formed in the emitter region, and after removing the unnecessary n+ layer by etching, Mg is etched by 2
After ion implantation at xiO"cm-" 200KeV and further Zn ion implantation at 1xlO"cm-2100KeV, a p+ type external base is formed by flash annealing using infrared radiation for 900'02 seconds (see Fig. 2).
b)). The concentration distribution in the depth direction of this external base layer is the third
As shown in the figure, the distance from the surface to 100OA is approximately 9
From a depth of 1000λ to a depth of 500 OA, it becomes p-type with a depth of approximately 7×10” cm.
次いでコンクタコ／タクト形成のためコレクタ接合層ま
でメサエッチングを施し、さら罠素子分離のため半絶縁
性基板１１までメサエッチングを施す（第２図（Ｃ））
。この後、エミッタ及びコレクタにライてばＡｕＧｅ／
Ａｕ 、ベースについてはＡｕ／ＡｕＺｎからなる各成
ｌ３１８ 、１９ 、２０を形成し、最後に素子間の内
部配線をＴｉ／Ｐｔ／Ａｕにより形成して完成する（第
１図）。Next, mesa etching is performed to the collector junction layer to form a contactor/tact, and further mesa etching is performed to the semi-insulating substrate 11 to separate the trap elements (Fig. 2 (C)).
. After this, lay AuGe/on the emitter and collector.
For the base, each component 1318, 19, 20 made of Au/AuZn is formed, and finally, the internal wiring between the elements is formed of Ti/Pt/Au to complete the process (FIG. 1).
こうして得られたＡＪＧａＡｓ／１３ａＡｓヘテロバイ
ポーラトランジスタは、ｆ−１０ＧＨｚ ｈ、Ｉｉ中３
００ と優れた性能を示した。この時外部ベース上の
ベースコンタクトは熱処理なしでオーミックコンタクト
が得られ、コンタクト抵抗率はＩ Ｘ １０−’ （ｌ
ｃｒｒＬ” と楊めて低い値を示し、本発明による製造
方法を用いない場合に比ベ−スコンタクト抵抗は著しく
低減できた。また通常ｎ型とｐ型のオーミックコンタク
トのための熱処理を同時に行なうため熱処理条件のマツ
チングをとる必要があるが、本発明による製造方法によ
り熱処理条件をｎ型のエミッタ及びコレクタコンタクト
のだめの最適条件とすることができ、エミッタ及びコレ
クタコンタクト抵抗も低減することができた。The thus obtained AJGaAs/13aAs hetero bipolar transistor has a f-10 GHz h, Ii medium 3
00 and showed excellent performance. At this time, an ohmic contact can be obtained for the base contact on the external base without heat treatment, and the contact resistivity is I x 10-' (l
crrL'', and the specific base contact resistance was significantly reduced when the manufacturing method of the present invention was not used.Also, heat treatment for n-type and p-type ohmic contacts is usually performed at the same time. Therefore, it is necessary to match the heat treatment conditions, but the manufacturing method according to the present invention allows the heat treatment conditions to be optimal for the n-type emitter and collector contacts, and also reduces the emitter and collector contact resistance. .
さらに本発明による製造方法を用いれば、素子寸法を縮
小し、ベースコンタクト面積が減少してもベースコンタ
クト抵抗が低いためコンタクト抵抗の大小に起因する性
能の低下を抑制でき、微細化による高性能化、高集積化
が可能となる。Furthermore, by using the manufacturing method according to the present invention, even if the element dimensions are reduced and the base contact area is reduced, the base contact resistance is low, so it is possible to suppress performance degradation caused by large or small contact resistance, and improve performance due to miniaturization. , high integration becomes possible.
本実施例では外部ベース形成のための注入不純物として
ＭｇとＺｎを用いた場合について述べたが、例えば前者
をＢｅとしても同樺の効果が得られる。In this embodiment, a case has been described in which Mg and Zn are used as the implanted impurities for forming the external base, but the same effect can be obtained even if the former is Be, for example.
例えばＢｅ ｔ−ｌＸｌ０”ｃｉ−’ １５０ＫｅＶ、
ＺｎをＩ Ｘ １０”Ｃｍ ’ １００ＫｅＶでイオ
ン注入し、９５０’０１秒の赤外線によるフラッシュア
ニールを施す。この時形成された外部ベース層は表面か
ら１００ＯＡの深さまで約９ｘｌＯ”ｍ−” １０００
＾から５０００＾の深さまでは約８Ｘ１０”Ｃ７ｎ″の
ｐｍとなり、コンタクト抵抗率はほぼＩ Ｘ １０′−
となる。For example, Be t-lXl0"ci-' 150KeV,
Zn is ion-implanted at I x 10"Cm' 100KeV and flash annealed using infrared rays for 950'01 seconds. The external base layer formed at this time has a thickness of about 9xlO"m-" 1000 from the surface to a depth of 100OA.
From ^ to 5000^ depth, the pm is approximately 8X10"C7n", and the contact resistivity is approximately I X 10'-
becomes.
また実施例では表面側がエミッタであり、かつエミッタ
にヘテロ接合を用いたヘテロ接合バイポーラトランジス
タについて述べたが、表面側がコレクタとなった。半絶
縁性基板−二ミツタ−ベース−コレクタという構造の場
合やコレクタ又はエミッタ及びコレクタの両方の接合に
ヘテロ接合を用いた場合にも本発明が有効であることは
言うまでもない。Further, in the embodiment, a heterojunction bipolar transistor in which the emitter is on the front side and a heterojunction is used for the emitter is described, but the collector is on the front side. It goes without saying that the present invention is also effective in the case of a semi-insulating substrate-two-meter-base-collector structure or in the case of using a heterojunction for the collector or both the emitter and collector junctions.
第１図は本発明の方法で得られたヘテロ接合バイポーラ
トランジスタの断面図、第２図は本発明の一実施例の製
造方法を説明するだめの工程断面図、第３図は本発明の
一実施例のイオン注入における不純物濃度の変化を示し
た図である。
１１二半絶縁性基板、１２：ｎ＋型ＧａＡｓ ４ （−
ｒ ｖフタ）。
１３：ｎ型ＧａＡｓ層（コレクタ）、１４．ｎ型ＧａＡ
ｓ層（ベース）、１５：ｎ型ＧａＡ／Ａｓ層（エミッタ
）、１６：ｎ＋型ＧａＡｓ層。
代理人 弁理士 則 近 憲 佑 （ばか１名）第
２ 図 （α２
第 ２ 図FIG. 1 is a cross-sectional view of a heterojunction bipolar transistor obtained by the method of the present invention, FIG. FIG. 3 is a diagram showing changes in impurity concentration during ion implantation in an example. 11: Two semi-insulating substrates, 12: n+ type GaAs 4 (-
r v lid). 13: n-type GaAs layer (collector), 14. n-type GaA
s layer (base), 15: n-type GaA/As layer (emitter), 16: n+-type GaAs layer. Agent Patent Attorney Kensuke Chika (Idiot 1) No.
Figure 2 (α2 Figure 2
Claims (1)
少なくとも一方がヘテロ接合となるようにコレクタ、ベ
ース、エミッタとなる半導体層をエピタキシャル成長さ
せて構成されるヘテロ接合バイポーラトランジスタにお
いて、少なくとも２種類の不純物元素をイオン注入する
ことによつて外部ベースを形成することを特徴とするヘ
テロ接合バイポーラトランジスタの製造方法。 ２、前記外部ベース形成のための注入不純物元素はＢｅ
、Ｍｇ、Ｚｎ、Ｃｄのうちのいずれかであることを特徴
とする特許請求の範囲第１項記載のヘテロ接合バイポー
ラトランジスタの製造方法。[Scope of Claims] 1. A heterojunction bipolar transistor formed by epitaxially growing semiconductor layers serving as a collector, a base, and an emitter on a compound semiconductor substrate so that at least one of the emitter junction and the collector junction becomes a heterojunction, comprising at least A method for manufacturing a heterojunction bipolar transistor, characterized in that an external base is formed by ion-implanting two types of impurity elements. 2. The implanted impurity element for forming the external base is Be.
, Mg, Zn, and Cd, the method for manufacturing a heterojunction bipolar transistor according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24323684A JPS61123175A (en) | 1984-11-20 | 1984-11-20 | Manufacture of hetero-junction bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24323684A JPS61123175A (en) | 1984-11-20 | 1984-11-20 | Manufacture of hetero-junction bipolar transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61123175A true JPS61123175A (en) | 1986-06-11 |
Family
ID=17100859
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24323684A Pending JPS61123175A (en) | 1984-11-20 | 1984-11-20 | Manufacture of hetero-junction bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61123175A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61198776A (en) * | 1985-02-28 | 1986-09-03 | Fujitsu Ltd | Hetero-junction bipolar transistor and manufacture thereof |
| JPH02254728A (en) * | 1989-03-28 | 1990-10-15 | Matsushita Electric Ind Co Ltd | Manufacture of compound semiconductor device |
-
1984
- 1984-11-20 JP JP24323684A patent/JPS61123175A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61198776A (en) * | 1985-02-28 | 1986-09-03 | Fujitsu Ltd | Hetero-junction bipolar transistor and manufacture thereof |
| JPH0458703B2 (en) * | 1985-02-28 | 1992-09-18 | Fujitsu Ltd | |
| JPH02254728A (en) * | 1989-03-28 | 1990-10-15 | Matsushita Electric Ind Co Ltd | Manufacture of compound semiconductor device |
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