JPS6112176A - Noise reduction circuit of video signal - Google Patents

Noise reduction circuit of video signal

Info

Publication number
JPS6112176A
JPS6112176A JP59132649A JP13264984A JPS6112176A JP S6112176 A JPS6112176 A JP S6112176A JP 59132649 A JP59132649 A JP 59132649A JP 13264984 A JP13264984 A JP 13264984A JP S6112176 A JPS6112176 A JP S6112176A
Authority
JP
Japan
Prior art keywords
level
signal
output
circuit
comb
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59132649A
Other languages
Japanese (ja)
Other versions
JPH0358232B2 (en
Inventor
Norio Ubukata
生方 典夫
Kasuke Iwafune
岩船 嘉助
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Nippon Victor KK
Original Assignee
Victor Company of Japan Ltd
Nippon Victor KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd, Nippon Victor KK filed Critical Victor Company of Japan Ltd
Priority to JP59132649A priority Critical patent/JPS6112176A/en
Priority to KR1019850004111A priority patent/KR900003078B1/en
Priority to IN487/MAS/85A priority patent/IN164384B/en
Publication of JPS6112176A publication Critical patent/JPS6112176A/en
Publication of JPH0358232B2 publication Critical patent/JPH0358232B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/14Picture signal circuitry for video frequency region
    • H04N5/21Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
    • H04N5/213Circuitry for suppressing or minimising impulsive noise
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/14Picture signal circuitry for video frequency region
    • H04N5/21Circuitry for suppressing or minimising disturbance, e.g. moiré or halo

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Picture Signal Circuits (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

PURPOSE:To make the output signal frequency characteristic flat and to improve the S/N by providing a small/medium level expanding circuit, expanding a signal of comparatively small level, adding it to the output of a comb-line filter and extracting the added result. CONSTITUTION:Switches S1, S2 are thrown to the Rec side at recording. A small - medium level signal below the slice level of a slice circuit 15 among outputs of a feedback comb-line filter is expanded by a small/medium level expanding circuit 17, added to the output of an equalizer 13 by an adder 16 and extracted. Thus, the small - medium level signal is extracted beyond the slice level, the signal of the vertical component from the terminal 6 is extracted beyond the slice level without loss and the characteristic is made flat beyond the slice level. Thus, when the input signal is at a noise level, a medium level and a large level, the frequency characteristic of the output signal shows no comb- line characteristic but flat, and the deterioration in the vertical resolution is not caused.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は映像信号の雑音低減回路に係り、例えばヘリカ
ルスキャンニング方式VTRに用いられ、特に、入力信
号が小レベル、中レベルの時出力信号周波数特性を平坦
とし得、SN比を改善し得、垂直方向解像度の劣化の少
ない雑音低減回路を提供することを目的とする。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video signal noise reduction circuit, which is used, for example, in a helical scanning VTR. It is an object of the present invention to provide a noise reduction circuit that can flatten the signal, improve the signal-to-noise ratio, and cause less deterioration of vertical resolution.

従来技術及びその問題点 第5図は例えばV T Rの輝度信号再生系に設けられ
ている従来め雑音低減回路の一例のブロック系統図を示
す。同図において、端子1に入来した信号a (第6図
(A))は高域フィルタ2にて例えばIMHz以上の周
波数の信号b (同図(B))とされ、リミッタ3で振
幅制限されて略雑音成分C(同図(C))とされた後係
数回路4を介して減算器5に供給され、ここで信号aか
ら雑音成分を減算されて信号d (同図(D))とされ
て端子6より取出される。
PRIOR ART AND THEIR PROBLEMS FIG. 5 shows a block system diagram of an example of a conventional noise reduction circuit provided in a luminance signal reproduction system of a VTR, for example. In the figure, a signal a (Figure 6 (A)) that enters the terminal 1 is converted into a signal b (Figure 6 (B)) with a frequency of, for example, IMHz or higher by a high-pass filter 2, and the amplitude is limited by a limiter 3. After the signal is converted into a noise component C ((C) in the same figure), it is supplied to the subtracter 5 via the coefficient circuit 4, where the noise component is subtracted from the signal a, resulting in a signal d ((D) in the same figure). is taken out from the terminal 6.

このものは、エツジ部分に雑音成分が残る一方、1 M
)Iz以下の低域雑音が残る問題点があった。
In this case, while noise components remain in the edge portion, 1 M
) There was a problem that low-frequency noise below Iz remained.

第7図は従来のト1相関雑音低減回路の一例のブロック
系統図を示す。同図において、端子1に入来した信号は
1H遅延回路7にて11−1遅延されて減算器8に供給
され、ここで、入力信号から減算された後リミッタ3で
振幅制限されて略雑音成分どされる。減算器5において
入力信号からリミッタ3の出力が減算されて雑音成分を
低減された信号が取出される。
FIG. 7 shows a block diagram of an example of a conventional T1 correlation noise reduction circuit. In the same figure, the signal input to the terminal 1 is delayed by 11-1 in the 1H delay circuit 7 and then supplied to the subtracter 8. Here, after being subtracted from the input signal, the amplitude is limited by the limiter 3 and the signal becomes almost noise. Ingredients are determined. A subtracter 5 subtracts the output of the limiter 3 from the input signal to obtain a signal with reduced noise components.

このものは、ライン相関がある場合では雑音成分を十分
に低減し得、第6図示の回路に比してエツジ部分に雑音
成分が残ることはなく、又、低域雑音を十分に低減し得
る。然るに、S N比の改善度に関しては論理的には3
c18程度とれるところ、例えば1H遅延回路7の特性
による劣化秀のために実際には1.5〜2.0dB程度
しかとれず、第8図(A)に示す如く、入力信号が小レ
ベルの時の出力信号はくし形特性が顕著となり、入力信
号が人レベルで出力信号レベルが人の時(同図(B))
に比して垂直方向解像度が劣化する等の問題点があった
、。
This circuit can sufficiently reduce noise components when there is line correlation, does not leave any noise components at the edge parts compared to the circuit shown in Figure 6, and can sufficiently reduce low-frequency noise. . However, the degree of improvement in the S/N ratio is logically 3.
For example, due to the deterioration due to the characteristics of the 1H delay circuit 7, it can actually be only about 1.5 to 2.0 dB, and as shown in Figure 8 (A), when the input signal is at a small level. The output signal has a pronounced comb-shaped characteristic, and when the input signal is human level and the output signal level is human level ((B) in the same figure)
There were problems such as a decrease in vertical resolution compared to .

第9図は本出願人が先に昭和58年11月28日付の特
許願「映像信号の雑音低減回路」で提案した回路の回路
図を示す。同図において、端子1に入来した信号を加算
器9,10.1H遅延回路7、及び高域フィルタ11.
係数回路12を挿入された帰還路からなる帰還形くし形
フィルタ及びイコライザ13を通し、この信号を減算器
14にて入ノ〕信号から減算し、この信号をスライス回
路15を通して得た信号とイコライザ13の出力とを加
算器16にて加算して取出すように構成されている。
FIG. 9 shows a circuit diagram of a circuit previously proposed by the present applicant in a patent application entitled "Video Signal Noise Reduction Circuit" dated November 28, 1981. In the figure, a signal input to terminal 1 is passed through adder 9, 10.1H delay circuit 7, and high-pass filter 11.
This signal is passed through a feedback comb filter and equalizer 13 consisting of a feedback path in which a coefficient circuit 12 is inserted, and a subtracter 14 subtracts this signal from the input signal, and this signal is combined with a signal obtained through a slice circuit 15 and an equalizer. 13 in an adder 16 and the output is taken out.

このものは、特に高周波数帯域でのSN比を例えば6〜
10dB程度に大幅に改善し得、又、第10図(C)に
示す如く、入力信号が大レベルの時では出力信号レベル
を大にとり得、垂直方向解像度の劣化が少ない。然るに
、第10図(B)に示す入力信号が中レベルの時及び同
図(C)に示す入力信号が小レベルの時では出力信号は
夫々くし形特性をもつようになり、垂直方向解像度が劣
化し、くし形特性を鋭くする分だけ第7図示の回路より
も垂直方向解像度が劣化する等の問題点があった。  
− 問題点を解決するための手段及びその作用本発明は、入
力映像信号を1H期間遅延してIffだ信号と該入力映
像信号とを加算して取出す第1のくし形フィルタと、入
力映像信号から第1のくし形フィルタの出力を減算して
取出J′第2のくし形フィルタと、記録時第2のくし形
フィルタの出力中仕較的小レベルの信号を伸長して上記
第1のくし形フィルタの出力と加算して取出す伸長回路
と、再生時上記第2のくし形フィルタの出力を圧縮して
上記第1のくし形フィルタの出力と加算して取出す回路
とからなる構成として上記問題点を解決したものであり
、以下、図面と共にその一実施例について説明する。
This product has an S/N ratio of, for example, 6 to 6, especially in high frequency bands.
This can be significantly improved by about 10 dB, and as shown in FIG. 10(C), when the input signal is at a high level, the output signal level can be increased, and there is little deterioration in vertical resolution. However, when the input signal shown in FIG. 10 (B) is at a medium level and when the input signal shown in FIG. 10 (C) is at a small level, the output signal has a comb-shaped characteristic, and the vertical resolution increases. There were problems such as the vertical resolution being worse than that of the circuit shown in FIG. 7 due to the sharpening of the comb characteristic.
- Means for solving the problem and its operation The present invention provides a first comb filter that delays an input video signal by 1H period and adds and extracts the If signal and the input video signal; The output of the first comb filter is subtracted from J', and the output signal of the second comb filter is expanded and the output of the first comb filter is expanded. The above configuration includes an expansion circuit that adds the output to the output of the comb filter and extracts the output, and a circuit that compresses the output of the second comb filter during reproduction and adds the output to the output of the first comb filter to extract the output. This problem has been solved, and one embodiment thereof will be described below with reference to the drawings.

実施例 第1図は本発明回路の一実施例のブロック系統図を示し
、同図中、第9図と同一構成部分には同一番号を付して
その説明を省略する。このものは、減算器14と加算器
16との間に、連動のスイッチS+ 、82 、スライ
ス回路15小中レベル伸長回路17(スライス回路15
におけるスライスレベル以下の小〜中レベル信号を伸長
するように構成されている)を設けたもので、その他の
構成は第9図示の回路と同様である。
Embodiment FIG. 1 shows a block system diagram of an embodiment of the circuit of the present invention. In the figure, the same components as those in FIG. 9 are given the same numbers and their explanations will be omitted. This device includes an interlocking switch S+, 82 between the subtracter 14 and the adder 16, a slice circuit 15, a small/medium level expansion circuit 17 (slice circuit 15
(The circuit is configured to expand small to medium level signals below the slice level in the circuit), and the other configuration is the same as the circuit shown in FIG.

記録時、スイッチS1.SzをReC側に接続する。帰
還形くし形フィルタの出力のうちスライス回路15のス
ライスレベル以下の小〜中レベル信号は小中レベル伸長
回路17にて伸長され、加算器16にてイコライザ13
の出力と加算されて取出される。このようにすると、小
〜中レベル信号もスライスレベルを越えて取出され、第
2図の特性■に示す如く、端子6よりの垂直方向成分の
信号はスライスレベル以上では損失なく取出され、第9
図示の回路の特性■に比してスライスレベル以上では平
坦となる。
During recording, switch S1. Connect Sz to ReC side. Among the outputs of the feedback comb filter, small to medium level signals below the slice level of the slice circuit 15 are expanded by a small to medium level expansion circuit 17, and then sent to an equalizer 13 by an adder 16.
is added to the output of In this way, small to medium level signals are also extracted beyond the slice level, and as shown in characteristic (2) in FIG.
Compared to characteristic (2) of the circuit shown in the figure, it becomes flat above the slice level.

これにより、入力信号がノイズレベル、中レベル、大レ
ベルの時の出力信号の周波数特性はくし形特性とはなら
ず、夫々第3図(B)、(C)。
As a result, the frequency characteristics of the output signal when the input signal is at a noise level, a medium level, and a large level do not have a comb-shaped characteristic, as shown in FIGS. 3(B) and 3(C), respectively.

(D)に示す如く平坦となり、垂直方向解像度の劣化を
生じない。なお、同図(A>は入力信号がノイズレベル
以下の極く小レベルの場合の出力信号レベルであり、く
し形特性をもつ。
As shown in (D), it becomes flat and no deterioration of vertical resolution occurs. Note that (A> in the figure) is the output signal level when the input signal is at an extremely low level below the noise level, and has a comb-shaped characteristic.

又、第2図の特性■に示す如く、垂直方向成分入力レベ
ルがスライスレベル以下の場合、特性■に比してその成
分が失なわれる割合が少く1い1.一般に、スライスレ
ベルは映像信号レベルに対して十分小に選定されている
ので、スライス回路15による垂直方向成分の損失は殆
ど目立lcない。
Also, as shown in characteristic (2) in FIG. 2, when the vertical component input level is below the slice level, the rate at which that component is lost is smaller than in characteristic (1). Generally, the slice level is selected to be sufficiently small compared to the video signal level, so the loss of vertical components caused by the slice circuit 15 is hardly noticeable.

゛  これに対して再生雑音は記録後に生じるので、再
生時にはスイッチS+ 、82をPB側に接続して第9
図示の回路と同じ糸路を介して鈴音を低減する。このよ
うな信号処理を行なうと、垂直方向解像度の劣化を第9
図示のものに比して少な(し得、帰還形くし形フィルタ
の大ぎなSN比改善度を生かし得、大幅なSN比改善を
行ない得る。
゛ On the other hand, playback noise occurs after recording, so during playback, switch S+ and 82 are connected to the PB side and the 9th
The ringing is reduced through the same thread as the circuit shown. When such signal processing is performed, the degradation of vertical resolution becomes
Although it is smaller than the one shown in the figure, it is possible to take advantage of the large S/N ratio improvement of the feedback comb filter, and it is possible to significantly improve the S/N ratio.

なお、スライス回路15の代りに小中レベル圧縮回路で
もよく、小中レベル伸長回路15の特性と小中レベル圧
縮回路の特性とを適当に選定すれば、映像信号の損失を
零にし得る。
Note that a small/medium level compression circuit may be used instead of the slice circuit 15, and if the characteristics of the small/medium level expansion circuit 15 and the characteristics of the small/medium level compression circuit are appropriately selected, the loss of the video signal can be reduced to zero.

又、小中レベル伸長回路17とスイッチS!との間、或
いは小中レベル伸長回路17とスイッチS2との間に低
域フィルタを接続すれば、減算器14の出力の高域成分
を低減し得、出力信号の周波数特性は第4図に示す如く
、低域では平坦、高域ではくし形特性にし得る。
Also, small and medium level expansion circuit 17 and switch S! If a low-pass filter is connected between the subtracter 14 and the subtractor 14, or between the small and medium level expansion circuit 17 and the switch S2, the high-frequency components of the output of the subtracter 14 can be reduced, and the frequency characteristics of the output signal are shown in FIG. As shown, the characteristics can be flat in the low range and comb-shaped in the high range.

又、上記低域フィルタのカットオフ周波数を適当に選定
することにより、高域くし形フィルタを実現でき、記録
時このような高域フィルタを用いると周知のように輝痕
信号の帯域を広くとり得、帯域が広く、SN比の高い再
生信号を得ることができる。
In addition, by appropriately selecting the cutoff frequency of the above-mentioned low-pass filter, a high-pass comb filter can be realized, and as is well known, when such a high-pass filter is used during recording, the band of the bright spot signal can be widened. Therefore, it is possible to obtain a reproduced signal with a wide band and a high signal-to-noise ratio.

効果 上述の如く、本発明になる映像信号の雑音低減回路は、
入力映像信号を1H期間遅延して得た信号と入力映像信
号とを加算して取出す第1のくし形フィルタと、入力映
像信号から第1のくし形フィルタの出力を減算して取出
す第2のくし形フィルタと、記録時第2のくし形フィル
タの出力中比較的小レベルの信号を伸長して上記第1の
くし形フィルタの出力と加算して取出す伸長回路と、再
生時上記M2のくし形フィルタの出力を圧縮して上記第
1のくし形フィルタの出力と加C7L、て取出寸回路と
より開成したため、出力信号の垂直方向成分の損失は圧
縮する際のスライスレベル以上で生じることはなく、こ
れにより、周波数特性はスライスレベル以上ではくし形
特性に1.tらずに平坦になり、特に、入ツノ信号が小
レベル、中レベルの時出力信号周波数特性を平坦とし得
、SN比を大幅に改善し得、垂直方向解像度の劣化が少
ない等の特長を有する。
Effects As mentioned above, the video signal noise reduction circuit according to the present invention has the following effects:
A first comb filter that extracts a signal obtained by delaying the input video signal by 1H period and the input video signal, and a second comb filter that extracts the output by subtracting the output of the first comb filter from the input video signal. a comb filter; an expansion circuit that expands a relatively low-level signal in the output of the second comb filter during recording and adds it to the output of the first comb filter; Since the output of the comb-shaped filter is compressed and the output of the first comb-shaped filter is added to the extraction size circuit using C7L, the loss of the vertical component of the output signal will not occur above the slice level during compression. As a result, the frequency characteristic becomes a comb-like characteristic above the slice level. In particular, when the input horn signal is at a small or medium level, the output signal frequency characteristics can be made flat, the S/N ratio can be greatly improved, and there is little deterioration in vertical resolution. have

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は夫々本発明回路の一実施例のブロッ
ク系統図及び垂直方向成分入力レベル対垂直方向の出力
レベル/入力レベル比特性図、第3図は本発明回路の動
作説明用出力信号周波数特性図、第4図は本発明回路に
おいて記録時に低域フィルタを用いた場合の出力信号周
波数特性図、第5図及び第6図は夫々従来回路の一例の
ブロック系統図及び動作説明用信号波形図、第7図及び
第8図は夫々従来回路の他の例のブロック系統図及び出
力信号周波数特性図、第9図及び第10図は夫々従来回
路の更に他の例のブロック系統図及び出ツノ信号周波数
特性図である。 1・・・映像信号入力端子、6・・・出力端子、7・・
・1H遅延回路、9.10.16・・・加算器、11・
・・高域フィルタ、12・・・係数回路、13・・・イ
コライザ、14・・・減算器、15・・・スライス回路
、17・・・小中レベル伸長回路、S+ 、32・・・
スイッチ。 第1図 褐3図 第4図 百塵一般→ 第5図 第6図 第9図
1 and 2 are a block system diagram and a vertical component input level versus vertical output level/input level ratio characteristic diagram of an embodiment of the circuit of the present invention, respectively, and FIG. 3 is for explaining the operation of the circuit of the present invention. An output signal frequency characteristic diagram; FIG. 4 is an output signal frequency characteristic diagram when a low-pass filter is used during recording in the circuit of the present invention; FIGS. 5 and 6 are block diagrams and operational explanations of an example of a conventional circuit, respectively. Figures 7 and 8 are block diagrams and output signal frequency characteristic diagrams of other examples of the conventional circuit, respectively, and Figures 9 and 10 are block diagrams of still other examples of the conventional circuit, respectively. FIG. 1...Video signal input terminal, 6...Output terminal, 7...
・1H delay circuit, 9.10.16...adder, 11.
...High-pass filter, 12...Coefficient circuit, 13...Equalizer, 14...Subtractor, 15...Slice circuit, 17...Small and medium level expansion circuit, S+, 32...
switch. Figure 1 Brown Figure 3 Figure 4 Hyakujin General → Figure 5 Figure 6 Figure 9

Claims (3)

【特許請求の範囲】[Claims] (1)入力映像信号を1H期間遅延して得た信号と該入
力映像信号とを加算して取出す第1のくし形フィルタと
、該入力映像信号から該第1のくし形フィルタの出力を
減算して取出す第2のくし形フィルタと、記録時該第2
のくし形フィルタの出力中比較的小レベルの信号を伸長
して上記第1のくし形フィルタの出力と加算して取出す
伸長回路と、再生時上記第2のくし形フィルタの出力を
圧縮して上記第1のくし形フィルタの出力と加算して取
出す回路とより構成してなることを特徴とする映像信号
の雑音低減回路。
(1) A first comb filter that adds and extracts a signal obtained by delaying the input video signal by 1H period and the input video signal, and subtracts the output of the first comb filter from the input video signal. a second comb-shaped filter to be taken out, and a second comb-shaped filter
an expansion circuit that expands a relatively low-level signal in the output of the comb filter and adds it to the output of the first comb filter to extract it; and an expansion circuit that compresses the output of the second comb filter during playback. A video signal noise reduction circuit comprising: a circuit that adds the output of the first comb filter and extracts the output.
(2)該第1のくし形フィルタは、帰還形くし形フィル
タであることを特徴とする特許請求の範囲第1項記載の
映像信号の雑音低減回路。
(2) The video signal noise reduction circuit according to claim 1, wherein the first comb filter is a feedback comb filter.
(3)該伸長回路は、その入力側又は出力側に低域フィ
ルタを設けてなることを特徴とする特許請求の範囲第1
項又は第2項記載の映像信号の雑音低減回路。
(3) Claim 1, characterized in that the expansion circuit is provided with a low-pass filter on its input side or output side.
3. The video signal noise reduction circuit according to item 1 or 2.
JP59132649A 1984-06-27 1984-06-27 Noise reduction circuit of video signal Granted JPS6112176A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP59132649A JPS6112176A (en) 1984-06-27 1984-06-27 Noise reduction circuit of video signal
KR1019850004111A KR900003078B1 (en) 1984-06-27 1985-06-12 Noise reduction circuit for video signal
IN487/MAS/85A IN164384B (en) 1984-06-27 1985-06-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59132649A JPS6112176A (en) 1984-06-27 1984-06-27 Noise reduction circuit of video signal

Publications (2)

Publication Number Publication Date
JPS6112176A true JPS6112176A (en) 1986-01-20
JPH0358232B2 JPH0358232B2 (en) 1991-09-04

Family

ID=15086256

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59132649A Granted JPS6112176A (en) 1984-06-27 1984-06-27 Noise reduction circuit of video signal

Country Status (3)

Country Link
JP (1) JPS6112176A (en)
KR (1) KR900003078B1 (en)
IN (1) IN164384B (en)

Also Published As

Publication number Publication date
IN164384B (en) 1989-03-04
KR900003078B1 (en) 1990-05-07
JPH0358232B2 (en) 1991-09-04
KR860000772A (en) 1986-01-30

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