JPS61117845A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61117845A
JPS61117845A JP59238391A JP23839184A JPS61117845A JP S61117845 A JPS61117845 A JP S61117845A JP 59238391 A JP59238391 A JP 59238391A JP 23839184 A JP23839184 A JP 23839184A JP S61117845 A JPS61117845 A JP S61117845A
Authority
JP
Japan
Prior art keywords
die
voids
semiconductor element
attacher
support
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59238391A
Other languages
Japanese (ja)
Inventor
Hiroshi Tate
宏 舘
Michiaki Furukawa
古川　道明
Kanji Otsuka
寛治 大塚
Toshihiro Tsuboi
敏宏 坪井
Takayuki Okinaga
隆幸 沖永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP59238391A priority Critical patent/JPS61117845A/en
Publication of JPS61117845A publication Critical patent/JPS61117845A/en
Pending legal-status Critical Current

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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To prevent cracks from generating in the semiconductor element by the intensive growth of voids, by a method wherein a die attacher which traps voids is interposed between a semiconductor element and a supporter. CONSTITUTION:An Au foil 7 interposed on the die attacher 6 is heated, and an Si chip 8 is bonded by press from the arrow direction, thus producing an Au-Si eutectic alloy; then, the Si chip 8 is bonded on the supporter 5. The die attacher 6 has the function of trapping voids 12 generating at the time of pellet attachment by dispersing them, and of allowing them not to move. Substance like a metallic conductor 10 with many punched holes 9 or substance like a wire sheet 11 can be used for the die attacher 6. Besides, a metallic wave plate 16 with arrayed projections 14 and recesses 15 can be used. The sizes and shapes of a mesh 13 and a hole 9 of the die attacher 6 are suitably determined by considering desired purposes.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は、半導体装置に関し、特に、半導体素子をセラ
ミック基板などの支持体上に接合する技術である、いわ
ゆるダイボンディング（ベレット付）において、発生す
るボイド（気泡）不良を回避する技術に関する。[Detailed Description of the Invention] [Technical Field] The present invention relates to semiconductor devices, and in particular, to the voids that occur in so-called die bonding (with pellets), which is a technique for bonding semiconductor elements onto a support such as a ceramic substrate. (Bubble) Concerning technology to avoid defects.

〔背景技術〕[Background technology]

ダイボンディングには、各種の方法がとられている。共
晶合金法は、一般に、ＡｕとＳｌとの反応により、Ａｕ
−８ｔ共晶を形成する反応を利用したベレット付法であ
る。Various methods are used for die bonding. The eutectic alloy method generally produces Au by reaction between Au and Sl.
This is a pelleting method that utilizes a reaction that forms a -8t eutectic.

ガラス法は、一般に、ソルダガラスを基板上で溶融させ
ておいて半導体素子を押付はベレット付する方法である
。The glass method is generally a method in which solder glass is melted on a substrate and a semiconductor element is pressed onto the substrate using a bullet.

導電性接着剤法は、導電性接着剤例えばＡｇぺ−ストな
どによりペレット付する方法である。The conductive adhesive method is a method in which pellets are attached using a conductive adhesive such as Ag paste.

これらダイボンディングにお（・て、その接合部内にボ
イドを生ずることが多い。These die bonding operations often produce voids within the bonded portion.

例えば、共晶合金法は、例えばセラミック基板上に、Ｗ
−ＮｉＴ地メツメツキｕメッキ表面とより成る厚膜導体
を形成しておき、Ａｕ箔を介在させて、例えばＳｉ単結
晶基板より成る半導体素子（以下Ｓｔチップとい５）を
、約４００”ＧＫ加熱圧着してＡｕ−８ｔ共晶を形成さ
せてペレット付するが、その際に接合部にボイドが生ず
る。このボイドは比較的小さくこまかく分散していれば
よいが、このボイドが集まり、比較的大なるボイドに成
長すると、ベレット付面の濡れ性が不均一となり、その
為、Ａｕ−８ｔ共晶とベレットないしチップの界面に温
度ティクルなどにより応力が集中し、ベレット（チップ
）が割れるなどの問題を起こす。For example, in the eutectic alloy method, W
- A thick film conductor consisting of a NiT base and a U-plated surface is formed, and a semiconductor element (hereinafter referred to as an "St chip" 5) made of, for example, a Si single crystal substrate is bonded with heat and pressure by approximately 40" GK with an Au foil interposed. The Au-8t eutectic is formed and pelletized, but at that time voids are generated at the joint.These voids need only be relatively small and finely dispersed, but if these voids gather together and become relatively large. When voids grow, the wettability of the surface with which the pellet is attached becomes non-uniform, which causes stress to concentrate at the interface between the Au-8t eutectic and the pellet or chip due to temperature tickling, resulting in problems such as cracking of the pellet (chip). wake up

このボイドの成長は、ペレット付の際にいきなりそうな
ることもあるが、次工程の各種パッケージング工程によ
り増長される。This void growth may occur suddenly when pelletizing, but it will be increased by various subsequent packaging steps.

すなわち、約４５０℃位のガラス封止や約３７００Ｃ位
のＡｕ−８ｎ封止などでの熱履歴や約２００〜３００℃
位で行われる半田付は工程での熱履歴などにより成長が
促進される。なお、グイボンディング技術について詳し
く述べである公知例として１９８０年１３１５日工業調
査会発行ｒＩＣ化実装技術ＪＰ１００〜１０１がある。In other words, the thermal history in glass sealing at about 450°C, Au-8n sealing at about 3700°C, etc., and the thermal history at about 200 to 300°C
When soldering is performed at low temperatures, growth is promoted by the heat history during the process. Incidentally, as a publicly known example which describes the Gui bonding technique in detail, there is rIC implementation technology JP 100-101 published by the Industrial Research Institute on 1315/1980.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、ボイドの発生は半導体素子の特性劣化
などを引き起こすので、できるだけその発生は阻止した
方がよいが、ボイドの発生は、ベレット付工程特に前記
Ａｕ−８ｉ共晶法において、なかなかさけられず、そこ
で、分散したボイドが集中し、成長することにより半導
体素子圧制れを生じることを防止し、信頼性の向上した
半導体装置を提供せんとするものである。The purpose of the present invention is that since the generation of voids causes deterioration of the characteristics of semiconductor elements, it is better to prevent their generation as much as possible. Therefore, it is an object of the present invention to prevent the scattered voids from concentrating and growing, thereby suppressing the semiconductor element, and to provide a semiconductor device with improved reliability.

本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらか釦なるであ
ろう。The above and other objects and novel features of the present invention include:
It will be clear from the description of this specification and the accompanying drawings that the button is a button.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.

すなわち、本発明では発生したボイドをトラップ（捕捉
）シ、他に移動させないようなダイアタッチャー例えば
、メッシェ状金属体である金網や　。That is, the present invention uses a die attacher that traps (captures) the generated voids and prevents them from moving elsewhere, such as a wire gauze that is a mesh-like metal body.

多数の小孔が開けられた金属薄板のごときを、例えば、
半導体素子とセラミック基板との間に介在させ、ペレッ
ト封圧よりＡｕ箔が溶融し、接合部にボイドが発生して
も、これらボイドをメク７工空間や孔（ホール）白和ト
ラップしておけば、他のホールなど忙移動せず、したが
って、封止工程などでの熱履歴によっても、ボイドが、
集′まり成長することがないようにしたものである。For example, a thin metal plate with many small holes drilled into it.
By interposing the Au foil between the semiconductor element and the ceramic substrate, even if the pellet sealing pressure melts the Au foil and generates voids at the joint, these voids can be trapped in the mechanical space or holes. For example, other holes are not busy, and therefore voids may be caused by heat history during the sealing process, etc.
This is to prevent them from gathering and growing.

〔実施例〕〔Example〕

次に、本発明の実施例を図面忙基づき説明する。 Next, embodiments of the present invention will be described with reference to the drawings.

実施例１ 第１図に示すよ５Ｋ、上から順次Ａｕ層１．Ｎｉ層２お
よびＷ層３より成るメタライズ層４を、その表面に有す
る支持体（実装基体）５上に、ダイアタラチャ−６、そ
の上部に、Ａｕ箔７を介在させて、半導体素子（Ｓｔチ
ップ）８をペレット付する。Example 1 As shown in FIG. A semiconductor element (St chip) is placed on a support (mounting base) 5 having a metallized layer 4 consisting of a Ni layer 2 and a W layer 3 on its surface, a diaterature 6, and an Au foil 7 interposed above it. 8 is attached with pellets.

ペレット付は、周知の共晶合金法により行えばよい。Pellet attachment may be performed by the well-known eutectic alloy method.

すなわち．ダイアタッチャー６上部に介在させたＡｕ箔
７を、約４５０℃位度に加熱された加熱炉中で、加熱し
、矢標方向からＳｉチップ８を圧着させ、Ａｕ−８ｔ共
晶合金を生成させ、Ｓｉチップ８を支持体５上に接合さ
せる。In other words. The Au foil 7 interposed on the top of the die attacher 6 is heated in a heating furnace heated to about 450° C., and the Si chip 8 is pressed from the direction of the arrow to produce an Au-8t eutectic alloy. Then, the Si chip 8 is bonded onto the support 5.

支持体５は例えばセラミック基板により構成される。The support body 5 is composed of, for example, a ceramic substrate.

メタライズ層４は、例えば金属蒸着、金属メッキなどの
方法により形成し得る。The metallized layer 4 can be formed, for example, by metal vapor deposition, metal plating, or the like.

ダイアタラチャ−６は、上記ペレット付の際に生じるボ
イドな分散させておき、成長させないような、換言すれ
ばかかるボイドなトラップし、移動させないような機能
を有するものであれば何でもよい。The diatarater 6 may be of any type as long as it has the function of dispersing the voids generated during pellet attachment and preventing them from growing, in other words, trapping the voids and preventing them from moving.

例えば、かかるダイアタラチャ−６には、第２図に示す
ような多数の孔９がパンチングされた金属薄体１０のご
ときもの、あるいは、第３図に示すような金網１１のご
ときものが使用できる。尚Ｗｃ３図には、ボイド１２が
メッシユ（空間）１３にトラップされている様子を併記
しである。For example, such a diameter starter 6 may be a thin metal body 10 punched with a large number of holes 9 as shown in FIG. 2, or a wire mesh 11 as shown in FIG. 3. Note that the Wc3 diagram also shows how the void 12 is trapped in the mesh (space) 13.

また、かかるダイアタッチャー６には、第４図に例示す
るような、断面を有する、プレス機械などくより凸部１
４および凹部１５をアレイ状に形成した金属製波板１６
も使用できる。In addition, the die attacher 6 has a convex portion 1 having a cross section as illustrated in FIG.
4 and a corrugated metal plate 16 having recesses 15 formed in an array.
can also be used.

かかるダイアタラチャ−６を構成する材料には、Ｓｉチ
ップにクラックが生ずることを防止する上で、Ｓｉチッ
プ８に対し、その熱膨張係数差の近いものを使用するこ
とが好ましい。例えば、Ｍｏ、４２７０イ（４２％Ｎｉ
含有合金）、コバール合金を使用することが好ましい。In order to prevent cracks from occurring in the Si chip, it is preferable to use a material that has a thermal expansion coefficient similar to that of the Si chip 8 as the material constituting the diatarrature 6. For example, Mo, 4270i (42% Ni
It is preferable to use a Kovar alloy.

ダイアタラチャ−６のメッシユ１３や孔９などの大きさ
、形状などは本発明所望の目的を考慮して適宜定められ
る。The size, shape, etc. of the mesh 13 and holes 9 of the dial chart 6 are appropriately determined in consideration of the desired purpose of the present invention.

半導体素子８は、上記例示のごとく例えばシリコン単結
晶基板から成り、周知の技術によりてこのチップ内には
多数の回路素子が形成され、１つの回路機能が与えられ
ている。As illustrated above, the semiconductor element 8 is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed within this chip using well-known techniques to provide one circuit function.

回路素子の具体例は、例えばＭＯＳ）ランジスタから成
り、これらの回路素子によって、例えばメモリや論理回
路の回路機能が形成されている。A specific example of the circuit element is, for example, a MOS (MOS) transistor, and these circuit elements form the circuit function of, for example, a memory or a logic circuit.

第５図に、かかるベレット付後に、ワイヤボンディング
工程や封止工程などを経て作られたデエアルインライン
（ＤＩＬ）タイプのセラミックパッケージを例示した。FIG. 5 shows an example of a DIL type ceramic package that is made through a wire bonding process, a sealing process, etc. after attaching the bullet.

Ｋ５図にて、１７は例えばセラミックにより構成された
キャップ、１８は例えばガラス材料により構成された封
止材料、１９は例えばＡＪＩ［により構成されたボンデ
ィングワイヤ、２０は例えばコバール合金により構成さ
れたリードを示す。In Figure K5, 17 is a cap made of ceramic, for example, 18 is a sealing material made of glass material, 19 is a bonding wire made of AJI, and 20 is a lead made of Kovar alloy, for example. shows.

尚ａ！１図に共通する符号は同一の機能を示すので、そ
の説明を省略する。Nao a! Since the symbols common to FIG. 1 indicate the same functions, their explanations will be omitted.

実施例２ 次忙、本発明の他の実施例を説明する。Example 2 Next, another embodiment of the present invention will be explained.

第１図〜第４図忙示す実施例は、本発明を、樹脂封止型
半導体装！のリードフレームに適用した例を示す。The embodiments shown in FIGS. 1 to 4 demonstrate the present invention as a resin-sealed semiconductor device! An example of application to a lead frame is shown below.

第６図は、かかる装置の完成断面図で、この装置は、例
えば次のようにして作られる。FIG. 6 is a completed sectional view of such a device, which is manufactured, for example, as follows.

すなわち、先ず、支持体（リードフレーム）２１のタブ
２２上に半導体素子２３を周知の共晶合金法などにより
ペレット付（ダイボンディング）し、該素子２３の電極
２４とリードフレーム２１とをボンディングワイヤ２５
によりボンディングし、周知のトランスファーモールド
法などによりエポキシ樹脂などのレジンをモールドし、
該レジンより成る封止体２６を生成させて、第６図に示
すような樹脂封止型半導体装置２０を得る。That is, first, the semiconductor element 23 is pelletized (die bonded) onto the tab 22 of the support (lead frame) 21 by a well-known eutectic alloy method, and the electrode 24 of the element 23 and the lead frame 21 are connected with a bonding wire. 25
Bonding is carried out, and resin such as epoxy resin is molded using the well-known transfer molding method.
A sealing body 26 made of the resin is produced to obtain a resin-sealed semiconductor device 20 as shown in FIG.

第７図は、当該リードフレーム２１０半導体素子２３を
ペレット付する部分（タブ２２）に、同図に示すように
、ダイアタッチ部（孔）２７を穿設し、かかるリードフ
レーム２１上に半導体素子２３をペレット付する様子を
、拡大断面にて示したものである。As shown in FIG. 7, a die attach portion (hole) 27 is bored in the part (tab 22) to which the semiconductor element 23 is attached to the pellet of the lead frame 210, and the semiconductor element 23 is attached onto the lead frame 21. 23 is an enlarged cross-sectional view showing how 23 is attached to pellets.

また、第８図は、前記第４図と同様にして、リードフレ
ーム２１のベレット付面にダイアタッチ部として凹部２
８凸部２９を形成し、かかるす＋ドフレーム２１のタブ
２２上に半導体素子２３をペレット付した様子を示す。FIG. 8 also shows a concave portion 2 as a die attach portion on the bulleted surface of the lead frame 21 in the same manner as in FIG. 4 above.
This figure shows how eight convex portions 29 are formed and a semiconductor element 23 is pelletized onto the tab 22 of the frame 21.

ＷＸ９図は、リードフレーム２１のタブ２２を、前記第
３図と同様にして、メッシェ状（メツシュ空１’１ｆｉ
３０）に構成して成るダイアタッチ部を有するリードフ
レームの平面図を示す。尚第９図にて、３１はタブ２２
を支持しているタブ吊リードを示す。Figure WX9 shows that the tab 22 of the lead frame 21 is shaped like a mesh (mesh empty 1'1fi) in the same way as in Figure 3 above.
30) is a plan view of a lead frame having a die attach portion configured as shown in FIG. In Fig. 9, 31 is the tab 22.
Shows the tab suspension lead supporting the.

〔効果〕〔effect〕

（１）本発明によれば、第６図〜第９図に示すように、
ダイボンディングの際に生ずるボイドをトラップする孔
などのダイアタッチ部を支持体に形成し、この支持体上
に、グイボンディングするようにし、または、第１図〜
第４図に示すように、金網などの前記ボイドなトラップ
するダイアタッチャーを、グイボンディングの際に、半
導体素子と支持体との間に介装して行うようにしたので
、前記ボイドがこれらダイアタッチ部などにトラップさ
れ、固定されるので、ボイド成長によるチップのクラッ
クを防止し、信頼性の向上した半導体装置を得ることが
できた。(1) According to the present invention, as shown in FIGS. 6 to 9,
A die attachment part such as a hole that traps voids generated during die bonding is formed on the support, and the die attaching part is formed on the support, or the die attach part is formed on the support, or
As shown in FIG. 4, a die attacher such as a wire mesh that traps the voids is interposed between the semiconductor element and the support during bonding, so that the voids are trapped. Since it is trapped and fixed in the die attach area, cracks in the chip due to void growth are prevented, and a semiconductor device with improved reliability can be obtained.

本発明は特に、クラックの発生が問題となる大型ペレッ
トに適用すると著効がある。The present invention is particularly effective when applied to large pellets where cracking is a problem.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

例えば、前記実施例では．ダイアタッチャーを、ダイボ
ンディングの際に、Ａｕ箔の下部に介在させる例を示し
たが、これをその上部にもっていってもよい。For example, in the above embodiment. Although an example has been shown in which the die attacher is interposed at the lower part of the Au foil during die bonding, it may also be placed at the upper part.

〔利用分野〕[Application field]

本発明はセラミックパッケージやプラスチックパッケー
ジなど広くダイボンディングを必要とする半導体装置や
電子装置１部品に適用できる。The present invention can be applied to a wide variety of semiconductor devices and electronic device parts that require die bonding, such as ceramic packages and plastic packages.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本発明の実施例を示す、ベレット付工程にお
ける半導体装置の要部断面図、第２図は、本発明に使用
されるダイアタッチャーの斜視図、 第３図は同地の例を示す平面図、 第４図は同地の例を示す断面図、 第５図はセラミックパッケージの一例を示す一部破断斜
視図、 第６図は本発明の他の実施例を示す断面図、第７図は第
６因果部断面図、 第８図は同第６図要部断面図、 第９図は本発明に使用されるリードフレームの要部平面
図である。 １・・・Ａｕ層、２・・・Ｎｉ層、３・・・Ｗ層、４・
・・メタライズ層、５・・・支持体（実装基体）、６・
・・ダイアタッチャー、７・＝　Ａ　ｕ箔、８・・・半
導体素子、９・・・孔、１０・・・金属薄板、１１・・
・金網、１２・・・ボイド、１３・・・メッ７Ｓ（空間
）、１４・・・凸部、１５・・・凹部、１６・・・波板
、１７・・・キャップ、１８・・・封止材料、１９・・
・ボンディングワイヤ、２０・・・リード、２１・・・
リードフレーム、２２・・・タブ、２３・・・半導体素
子、２４・・・電極、２５・・・ボンディングワイヤ、
２６・・・封止体、２７・・・孔、２８・・・凹部、２
９・・・凸部、３０・・・メッシェ空間、３１・・・タ
ブ吊リード。 代理人　弁理士　　高　橋　明　夫゛、＼、ノ ゝ−−ノ／ 第　　４　　図 第　　５　　図 第　　６　　図 第　　７　　図 第　　８　　図FIG. 1 is a sectional view of a main part of a semiconductor device in a bulleting process showing an embodiment of the present invention, FIG. 2 is a perspective view of a die attacher used in the present invention, and FIG. 3 is a view of the same area. FIG. 4 is a plan view showing an example; FIG. 4 is a sectional view showing an example of the same area; FIG. 5 is a partially cutaway perspective view showing an example of a ceramic package; FIG. 6 is a sectional view showing another embodiment of the present invention. , FIG. 7 is a sectional view of the sixth causal part, FIG. 8 is a sectional view of the main part shown in FIG. 6, and FIG. 9 is a plan view of the main part of the lead frame used in the present invention. 1...Au layer, 2...Ni layer, 3...W layer, 4...
... Metallized layer, 5... Support (mounting base), 6.
...Die attacher, 7. = Au foil, 8.. Semiconductor element, 9.. Hole, 10.. Thin metal plate, 11..
・Wire mesh, 12... Void, 13... Met 7S (space), 14... Convex portion, 15... Concave portion, 16... Corrugated plate, 17... Cap, 18... Seal Stopping material, 19...
・Bonding wire, 20...Lead, 21...
Lead frame, 22... Tab, 23... Semiconductor element, 24... Electrode, 25... Bonding wire,
26... Sealing body, 27... Hole, 28... Concave portion, 2
9...Convex portion, 30...Mesh space, 31...Tab suspension lead. Agent Patent Attorney Akio Takahashi゛＼、ノゝ－－ノ/ Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (6)

【特許請求の範囲】[Claims] １．支持体上に半導体素子を接合するダイボンディング
において、発生するボイドをトラップし、固定するダイ
アタッチ部を形成した支持体上に半導体素子をダイボン
ディングして成るか、または、前記ボイドをトラップし
、固定するダイアタッチャーを支持体と半導体素子との
間に介装してダイボンディングを行って成ることを特徴
とする半導体装置。1. In die bonding for bonding a semiconductor element onto a support, the semiconductor element is die-bonded onto a support on which a die attach part is formed to trap and fix the voids that occur, or trap the voids, A semiconductor device characterized in that die bonding is performed by interposing a fixing die attacher between a support and a semiconductor element. ２．ダイアタッチャーが、パンチングによる多数の穿孔
を有る金属薄板である、特許請求の範囲第１項記載の装
置。2. 2. The device of claim 1, wherein the die attacher is a sheet metal plate having a large number of perforations formed by punching. ３．ダイアタッチャーが、金網である特許請求の範囲第
１項記載の装置。3. 2. The device according to claim 1, wherein the die attacher is a wire mesh. ４．ダィアタッチャーが、波板である、特許請求の範囲
第１項記載の装置。4. 2. The device of claim 1, wherein the die attacher is a corrugated plate. ５．支持体が、セラミック基板である、特許請求の範囲
第１項記載の装置。5. 2. The device of claim 1, wherein the support is a ceramic substrate. ６．支持体が、リードフレームであり、かつ、該フレー
ム表面にプレス機械により凹凸より成るダイアタッチ部
を形成して成る、特許請求の範囲第１項記載の装置。6. 2. The device according to claim 1, wherein the support is a lead frame, and a die attach portion consisting of concavities and convexities is formed on the surface of the frame by a press machine.
JP59238391A 1984-11-14 1984-11-14 Semiconductor device Pending JPS61117845A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59238391A JPS61117845A (en) 1984-11-14 1984-11-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59238391A JPS61117845A (en) 1984-11-14 1984-11-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61117845A true JPS61117845A (en) 1986-06-05

Family

ID=17029496

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59238391A Pending JPS61117845A (en) 1984-11-14 1984-11-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61117845A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0259035A2 (en) * 1986-08-28 1988-03-09 Stc Plc Solder joint between an electrical component and a substrate
US5089439A (en) * 1990-02-02 1992-02-18 Hughes Aircraft Company Process for attaching large area silicon-backed chips to gold-coated surfaces
GB2450230A (en) * 2007-06-06 2008-12-17 Boeing Co Patterned die attach layer
CN104465578A (en) * 2013-09-13 2015-03-25 株式会社东芝 Semiconductor device and semiconductor module

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0259035A2 (en) * 1986-08-28 1988-03-09 Stc Plc Solder joint between an electrical component and a substrate
US5089439A (en) * 1990-02-02 1992-02-18 Hughes Aircraft Company Process for attaching large area silicon-backed chips to gold-coated surfaces
GB2450230A (en) * 2007-06-06 2008-12-17 Boeing Co Patterned die attach layer
CN104465578A (en) * 2013-09-13 2015-03-25 株式会社东芝 Semiconductor device and semiconductor module

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