JPS61114558A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS61114558A JPS61114558A JP23621084A JP23621084A JPS61114558A JP S61114558 A JPS61114558 A JP S61114558A JP 23621084 A JP23621084 A JP 23621084A JP 23621084 A JP23621084 A JP 23621084A JP S61114558 A JPS61114558 A JP S61114558A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- integrated circuit
- circuit device
- semiconductor integrated
- wirings
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
１１） 技術分野
本発明は半導体集積回路装置に於ける電極配線方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION 11) Technical Field The present invention relates to an electrode wiring method in a semiconductor integrated circuit device.
（２） 従来技術
従来高速パルスが印加される第１の配線と他第２配線が
交差する場合、第１の配線のクロック動作に従って、両
線線間の絶縁膜容量を介して、ｇ２の配線に電位変動を
引き起す。この容量結合の影響をさけるために両線線間
の絶縁膜を厚くするかもしくは絶縁ｊ良に誘電率の小さ
な絶縁物を用いて電位変動を低減している。しかし該絶
縁膜に覆われた第１の配線を半導体集積回路装置のケー
スのリード端子に接続するために該絶縁膜を開口し他の
第３の金属配線に接続せねばならず、絶縁膜が厚いと第
４の金１Ａ１１Ｌ極が開口部段で段切れせずに第１の配
線に接続することは難しく、又絶υ膜を誘電率の小さな
ものを使用することは製造上制約を受ける。(2) Prior art When a first wiring to which conventional high-speed pulses are applied intersects with another second wiring, the g2 wiring is causes potential fluctuations. In order to avoid the influence of this capacitive coupling, potential fluctuations are reduced by increasing the thickness of the insulating film between the two wires or by using an insulator with a small dielectric constant for the insulation. However, in order to connect the first wire covered with the insulating film to the lead terminal of the case of the semiconductor integrated circuit device, the insulating film must be opened and connected to another third metal wire, and the insulating film is If it is thick, it is difficult to connect the fourth gold 1A11L pole to the first wiring without breaking at the opening step, and there are manufacturing restrictions on using an insulation film with a small dielectric constant.
（３） 発明の目的
本発明の目的は半導体集積回路装置の’ｆｌ憔配線が互
に絶縁交差する部分に於て一方の配線の電位変動が容量
結合により他方の配線の電位変動を生じさせることのな
い配線交差法を提供することにある。(3) Purpose of the Invention The purpose of the present invention is to provide a semiconductor integrated circuit device in which a potential fluctuation of one wiring causes a potential fluctuation of the other wiring due to capacitive coupling at a portion where the 'fl wiring of a semiconductor integrated circuit device intersects with each other in insulation. The purpose of the present invention is to provide a wire crossing method that does not require wire crossing.
（４）発明の構成
本発明は具体的には、電極配線および信号制御配線とな
る第１の配線と第２の配線が互に絶縁交差する部分を有
し、該配線の少くとも一方の配線にクロックパルス等の
電位変動を伴う半導体集積回路装置に於て、前記配線の
交差部に該配線とは互に絶縁された第３の配線を第１の
配線と第２の配線間に配置し、該第３の配線を直流電位
に接続した半導体集積回路装置である。(4) Structure of the Invention Specifically, the present invention has a portion where a first wiring and a second wiring serving as an electrode wiring and a signal control wiring intersect with each other in an insulating manner, and at least one of the wirings In a semiconductor integrated circuit device that is subject to potential fluctuations such as clock pulses, a third wiring that is insulated from the wiring is placed between the first wiring and the second wiring at the intersection of the wiring. , is a semiconductor integrated circuit device in which the third wiring is connected to a DC potential.
（５）発明の作用効果
第１の配線と第２の配線が絶縁膜を介して交査する部分
計ては容量結合を持ち、従って一方の配線の電位変動が
起ると、該容量結合により他方の配線がそれにつられて
電位変動を生ずるが、両線線の交差部分に、それぞれの
配線と絶縁された第３の配線を挿入し、該配線を直流電
位に固定すると第１と第２の配線間の容量結゛合がなく
なり一方の配線の電位変動が他方の配線の電位変動を引
き起すことのない半導体集積回路装置が得られるもので
ある。(5) Effects of the Invention The portion where the first wiring and the second wiring intersect through the insulating film has capacitive coupling. Therefore, when a potential fluctuation occurs in one of the wirings, the capacitive coupling causes The potential of the other wire will vary accordingly, but if you insert a third wire insulated from each wire at the intersection of both wires and fix this wire to a DC potential, the potential of the first and second wires will change. It is possible to obtain a semiconductor integrated circuit device in which capacitive coupling between wirings is eliminated and potential fluctuations in one wiring do not cause potential fluctuations in the other wiring.
（６）発明の実施例 本発明の一実施例を図を参照して説明する。(6) Examples of the invention An embodiment of the present invention will be described with reference to the drawings.
第１図に本発明の実施例の半導体集積回路装置の一交差
配線部分の平面図を示す。図中１は第１の配線となる多
結晶シリコン［＆配線、２は第２の配線となるアルミ電
極配線、３は前記両線線間に絶縁酸化膜を介して配置さ
れた多結晶シリコン電極配線を表わし、斜線領域は第１
の配線と第２の配線との交差領域を表わす。FIG. 1 shows a plan view of a cross-wiring portion of a semiconductor integrated circuit device according to an embodiment of the present invention. In the figure, 1 is the polycrystalline silicon [& wiring that will be the first wiring, 2 is the aluminum electrode wiring that will be the second wiring, and 3 is the polycrystalline silicon electrode that is placed between the two lines with an insulating oxide film interposed between them. represents the wiring, and the shaded area is the first
represents the intersection area between the wiring and the second wiring.
第２図に第１５！Ｊの交差領域を含むＡ−Ｂでの素子断
面図を示す。第２図に於て記号１−３は第１図と同じ配
線を表わし、４，１４．２４は絶縁酸化膜、５はシリコ
ン半導体基板を表わす。Number 15 in Figure 2! A cross-sectional view of the device along AB including the intersection area of J is shown. In FIG. 2, symbols 1-3 represent the same wiring as in FIG. 1, 4, 14, and 24 represent insulating oxide films, and 5 represents a silicon semiconductor substrate.
図に示した如く、第３の配線３は第１の配線と第２の配
線の交差部の両線線間に配置し、かつ該配線を直流電位
の接地電位に接続する。このような構造をとることによ
り第１の配線と第２の配線との容量結合がなくなり、該
両線線の一方の電位変動が他方の配線の電位変動が生じ
ない半導体集積回路装置が得られる。実施例では第１の
配線と第２の配線は多結晶シリコン電極配線、第３の配
線はアルミ電極配線としたが、各配線はその材質は問わ
ず配線材質であるなら何を用いてもよいことは言うまで
もなく、特に最下層の配線である第１の配線は基板と逆
導電型不純物を拡散形成された拡散層配線でもよい。As shown in the figure, the third wiring 3 is disposed between the first wiring and the second wiring at the intersection thereof, and is connected to the ground potential of the DC potential. By adopting such a structure, capacitive coupling between the first wiring and the second wiring is eliminated, and a semiconductor integrated circuit device can be obtained in which potential fluctuations in one of the two wires do not cause potential fluctuations in the other wiring. . In the embodiment, the first wiring and the second wiring are polycrystalline silicon electrode wiring, and the third wiring is aluminum electrode wiring, but the material of each wiring does not matter and any wiring material may be used. Needless to say, especially the first wiring, which is the lowest layer wiring, may be a diffusion layer wiring formed by diffusing impurities of a conductivity type opposite to that of the substrate.
第１ｇＡは本発明の一実施例による半導体集積回路装置
の交差配線部を有する一表面図を示し、図中１は８ｇ１
の配線の多結晶シリコン配線、２は第２の配線のアルミ
配線、３は前記第１の配線と第２の配線間に絶縁配置さ
れ、かつ直流電位に接続される第３の配線の多結晶シリ
コン配線を表わし、斜線領域は第１と第２の配線の交差
鎖酸を表わす。
第２図は第１図のＡ−Ｂ切断面での素子断面図であって
記号１〜３はそれぞれ第１図と同一のものを表わし４，
１４．２４は絶縁酸化膜、５は半導体基板を表わす。
代理人 弁理士 内 原 晋 ・平１図
障２区1gA shows a surface view of a semiconductor integrated circuit device according to an embodiment of the present invention having a cross wiring part, and 1 in the figure is 8g1.
2 is a polycrystalline silicon wiring as a wiring, 2 is an aluminum wiring as a second wiring, and 3 is a polycrystalline wiring as a third wiring which is insulated between the first wiring and the second wiring and is connected to a DC potential. The silicon wiring is represented, and the shaded area represents the cross-chain acid between the first and second wirings. FIG. 2 is a cross-sectional view of the element taken along the line A-B in FIG. 1, and symbols 1 to 3 represent the same elements as in FIG.
14 and 24 represent an insulating oxide film, and 5 represents a semiconductor substrate. Agent: Susumu Uchihara, Patent Attorney, Hei 1 Zusho 2 Ward
Claims (1)
と第２の配線を有し、該配線交差する部分を有する半導
体集積回路装置に於て、前記配線の交差部に、該配線と
は互に絶縁された第３の配線を第１の配線と第２の配線
間に配し、該第３の配線を直流電位に接続したことを特
徴とする半導体集積回路装置。In a semiconductor integrated circuit device having a first wiring and a second wiring serving as a signal wiring and a signal control wiring or an electrode, and having a portion where the wirings intersect, the wirings are mutually connected to each other at the intersection of the wirings. 1. A semiconductor integrated circuit device, characterized in that a third wiring insulated between the first wiring and the second wiring is arranged between the first wiring and the second wiring, and the third wiring is connected to a DC potential.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23621084A JPS61114558A (en) | 1984-11-09 | 1984-11-09 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23621084A JPS61114558A (en) | 1984-11-09 | 1984-11-09 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61114558A true JPS61114558A (en) | 1986-06-02 |
Family
ID=16997404
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23621084A Pending JPS61114558A (en) | 1984-11-09 | 1984-11-09 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61114558A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01235256A (en) * | 1988-03-15 | 1989-09-20 | Nec Corp | Semiconductor integrated circuit device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4940889A (en) * | 1972-08-25 | 1974-04-17 | ||
| JPS5125984A (en) * | 1974-08-28 | 1976-03-03 | Nippon Denso Co | Mos shusekikairo |
-
1984
- 1984-11-09 JP JP23621084A patent/JPS61114558A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4940889A (en) * | 1972-08-25 | 1974-04-17 | ||
| JPS5125984A (en) * | 1974-08-28 | 1976-03-03 | Nippon Denso Co | Mos shusekikairo |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01235256A (en) * | 1988-03-15 | 1989-09-20 | Nec Corp | Semiconductor integrated circuit device |
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