JPS61113272A - Ultraviolet ray elimination type semiconductor memory - Google Patents
Ultraviolet ray elimination type semiconductor memoryInfo
- Publication number
- JPS61113272A JPS61113272A JP59235759A JP23575984A JPS61113272A JP S61113272 A JPS61113272 A JP S61113272A JP 59235759 A JP59235759 A JP 59235759A JP 23575984 A JP23575984 A JP 23575984A JP S61113272 A JPS61113272 A JP S61113272A
- Authority
- JP
- Japan
- Prior art keywords
- phosphorus glass
- electrical connection
- coated film
- glass coated
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 230000008030 elimination Effects 0.000 title 1
- 238000003379 elimination reaction Methods 0.000 title 1
- 239000011521 glass Substances 0.000 claims abstract description 41
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 36
- 150000004767 nitrides Chemical class 0.000 claims abstract description 28
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 23
- 239000011574 phosphorus Substances 0.000 claims abstract description 23
- 230000002093 peripheral effect Effects 0.000 claims abstract description 22
- 238000007667 floating Methods 0.000 claims abstract description 20
- 239000011347 resin Substances 0.000 claims abstract description 16
- 229920005989 resin Polymers 0.000 claims abstract description 16
- 239000011248 coating agent Substances 0.000 claims description 14
- 238000000576 coating method Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 abstract description 3
- 230000007797 corrosion Effects 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 150000002739 metals Chemical class 0.000 abstract description 2
- 239000004020 conductor Substances 0.000 abstract 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 241001385733 Aesculus indica Species 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000000443 aerosol Substances 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、メモリ部に書き込まれネでいる記憶情報を
紫外線を照射して消去する紫外線消去型半導体記憶素子
の半導体チップ、例えばＫＰＲＯＭ （Ｋｒａｓａｂｌ
ｅ ａｎｄ Ｐｒｏｇｒａｍａｂｌｅ Ｒｅａｄ 艶ン
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor chips of ultraviolet erasable semiconductor memory elements, such as KPROM (Krasabl.
e and Programmable Read Atsushi no Naru.
この種ｍＰＲＯＭ全面をモールド樹脂にて被覆し、封止
する紫外線消去型半導体記憶装置ｔは、紫外線透過用の
窓を付けず通常のモールド樹脂封止方法で封止をする几
めに低価格であり、かつ１回のみの記憶情報書き込みが
用途に応じて自由に行えるために同一記憶情報をもつＲ
ＯＭｔ−少ない数で必要とするニーデーにとっては非常
ＶＣ何効なものである。This kind of ultraviolet erasable semiconductor memory device t, in which the entire surface of an mPROM is covered and sealed with a molding resin, is low-cost and is encapsulated using a normal molding resin sealing method without adding a window for transmitting ultraviolet rays. Yes, and R with the same memory information can be written only once depending on the purpose.
OMt - Very effective VC for those who need it in small quantities.
第３図及び第４図は各々上記の様な紫外線消去型半導体
記憶装置の従来装置の全体構成図及び半導体チップの断
面図であり、１！１はシリコンからなる半導体基板、
（Ｓｌａ）（１）（ｇｃ）はこの半導体基板＋１１の
一生面に拡散形成された不純物拡散層、（３）は上記半
導体基板＋１１の一生面上に形成された二酸化シリコン
からなる酸化膜、（４）は１対の上記不純物拡散層（２
ａ）（２ｂ）間の酸化膜（３）中に１つづつ配設され半
４体チップの中央部にマトリクス状に複数設けられてメ
モリ部を構成するポリシリコンからなる電荷蓄積用の７
０−テイングゲート、ｌｆｉ＋はこのフローティングゲ
ート（４）上に酸化膜（３）ヲ介して設けられたメモリ
のコントロールゲート、（５）は不純物拡散層（２ａ）
（２ｂ）間の酸化膜（３）中７０−テイングゲート（４
１周辺に設けられ、かつ半導体チップ（１０）の周端部
より内側に設けられて周辺回路部を構成するトランジス
タのゲートとなる周辺回路部トランジスタゲート、（７
）は上記不純物拡散層（２ａ）（２ｂ）（２ｃ）に接す
る部分をもち、上記周辺回路部及び上記フローティング
ゲート（４）上部の一部を除くメモリ部の酸化膜（３）
上に設けられ、上記周辺回路部及び上記メモリ部の素子
を電気的に接続するアルミニウムからなる電気接続線、
（８）はこの電気接続線（７）にボンディングワイヤ（
ｌすを接続するためのポンディングパッド窓、（９ａ）
はこのポンディングパッド窓（８）を除く、上記メモリ
部、周辺回路部及び半導体チップ（１０）周端部上全面
に上記電気接続線（７）を介して設けられて半導体チッ
プｔｌｏ１表面を保護し、かつ紫外線を透過し得る厚さ
ｌｐｍ程度のリンガラスコート膜である。（ｌＯ）は上
記の様に構成されたｌＰＲＯＭ等の半導体チップ、（１
１）はこの半導体チップ（ｌＯ）のポンディングパッド
窓（８）に接続されるボンディングワイヤ、 （１２ｈ
このボンディングワイヤ（１１）に接続され外部に対す
る電極となるリードフレーム、囮はこれら半導体チップ
ｆｌｏＩ 、ボンディングワイヤ（１１）及びリートフ
レームロをモールド樹月旨によって覆い封止するモール
ド樹脂体である。3 and 4 are an overall configuration diagram and a sectional view of a semiconductor chip of a conventional ultraviolet erasable semiconductor memory device as described above, respectively, and 1!1 is a semiconductor substrate made of silicon;
(Sla) (1) (gc) is an impurity diffusion layer diffused and formed on the whole surface of the semiconductor substrate +11, (3) is an oxide film made of silicon dioxide formed on the whole surface of the semiconductor substrate +11, ( 4) is a pair of the above impurity diffusion layers (2).
a) A plurality of charge storage sevens made of polysilicon are disposed in the oxide film (3) between (2b) and are disposed in a matrix in the center of the half-quad chip to form the memory section.
0-ting gate, lfi+ is the memory control gate provided on this floating gate (4) via the oxide film (3), and (5) is the impurity diffusion layer (2a).
(2b) oxide film between (3) and 70-teing gate (4)
a peripheral circuit section transistor gate (7) which is provided around the periphery of the semiconductor chip (10) and is provided inside the peripheral edge of the semiconductor chip (10) and serves as a gate of a transistor constituting the peripheral circuit section;
) has a portion in contact with the impurity diffusion layers (2a), (2b, and 2c), and is an oxide film (3) in the memory area excluding the peripheral circuit area and a part of the upper part of the floating gate (4).
an electrical connection line made of aluminum that is provided on the top and electrically connects the elements of the peripheral circuit section and the memory section;
(8) is a bonding wire (
bonding pad window, (9a) for connecting the
is provided over the entire surface of the memory section, peripheral circuit section and peripheral edge of the semiconductor chip (10), excluding this bonding pad window (8), via the electrical connection line (7) to protect the surface of the semiconductor chip tlo1. It is a phosphorus glass coated film having a thickness of about 1 pm and capable of transmitting ultraviolet rays. (lO) is a semiconductor chip such as lPROM configured as above, (1
1) is a bonding wire connected to the bonding pad window (8) of this semiconductor chip (lO), (12h
The lead frame and decoy connected to the bonding wire (11) and serving as electrodes to the outside are molded resin bodies that cover and seal the semiconductor chip floI, the bonding wire (11), and the lead frame with a mold base.
上記の様に構成された紫外線消去型半導体記憶装置は半
導体チップ（ｌＯ）を形成してからモールド樹脂体１１
３にて半導体チップ（１０１を封止するまでの工程を以
下の様に行うものである。In the ultraviolet erasable semiconductor memory device configured as described above, after forming the semiconductor chip (lO), the mold resin body 11 is
The steps up to sealing the semiconductor chip (101 in step 3) are performed as follows.
まず、半導体チップ１０１の電気的特性のテスト全行う
が、この電気的特性のテストに於ては電荷蓄積用のフロ
ーティングゲート（４）に電子を注入しデータ情報の書
き込み全行い、正常な記憶情報の書き込みが行われたか
どうかをテストする。そして、このテストが終了した後
、紫外線を照射して書き込んだ記憶情報を行う。次に記
憶情報が消去された半導体チップ（１０）とり一ド７レ
ーム凹とをボンディングワイヤ（川にて接続し、これを
モールド樹脂封止の之めの金型に入れ、高温に溶解した
モールド樹脂をこの金型に流し込む、そして、このモー
ルド１Ｍ脂が冷却した後、これを金型から収り出し、紫
外線消去型半導体記憶装置を得る。First, the electrical characteristics of the semiconductor chip 101 are fully tested. In this electrical characteristics test, electrons are injected into the floating gate (4) for charge storage, all data information is written, and normal storage information is detected. Test whether writing was performed. After this test is completed, the written information is read by irradiating it with ultraviolet light. Next, the semiconductor chip (10) from which the memory information has been erased is connected to the 7-frame recess by bonding wire (wire), and this is placed in a mold for sealing with mold resin, and the mold is melted at a high temperature. Resin is poured into the mold, and after the mold 1M resin has cooled, it is taken out of the mold to obtain an ultraviolet erasable semiconductor memory device.
上記のような従来の紫外線消去型半導体記憶装置は半導
体チップ（ｌＯ）表面に設けたリンガラスコート膜（９
ａ）がモールド樹脂体（＋３）に接しているためモール
ド樹脂体（１３）形成時にモールド樹脂がリンガラスコ
ート膜（９ａ）を圧迫した時、機械的圧力に弱いリンガ
ラスコート膜（９ａ）の半導体チツブｆｉｏ＋ ８端部
よりり２ツクが生じることがあり、このクラックによっ
てパッケージ内部或いは一リードフレームとモールド樹
脂体との間に生じるわずかなすき間から浸入した湿気が
電気接続線（７）等の金１４を腐食させ、入出力端子の
リーク電流の増大、または電気接続線（７）の断線をま
ねくという問題点があった。The conventional ultraviolet erasable semiconductor memory device as described above uses a phosphor glass coating film (9) provided on the surface of a semiconductor chip (1O).
a) is in contact with the molded resin body (+3), so when the molded resin presses the phosphorous glass coated film (9a) during the formation of the molded resin body (13), the phosphorous glass coated film (9a), which is weak against mechanical pressure, A crack may occur from the edge of the semiconductor chip FIO+ 8, and this crack may cause moisture to enter the inside of the package or from the small gap created between the lead frame and the molded resin body and cause damage to electrical connection wires (7), etc. There is a problem in that the gold 14 is corroded, leading to an increase in leakage current at the input/output terminals or breakage of the electrical connection line (7).
この発明はかか一問題点を解決するためになされたもの
で、半導体チップ間端部からリンガラスコート膜（９）
にクラックが生じることを防ぎ金属の腐食による問題が
生じない紫外線消去型半導体記憶装置を得ることを目的
としている。This invention was made in order to solve the above problem.
The object of the present invention is to obtain an ultraviolet erasable semiconductor memory device which prevents cracks from occurring in the semiconductor memory device and which does not cause problems due to metal corrosion.
この発明に係る紫外線消去型半導体記憶装置は、半導体
基板上におけるフローティングゲート上部を除いた少な
くとも周辺部にリンガラスコート膜を介して窒化膜を形
成したものである。In the ultraviolet erasable semiconductor memory device according to the present invention, a nitride film is formed on at least the peripheral portion of the semiconductor substrate, excluding the upper part of the floating gate, with a phosphor glass coat film interposed therebetween.
この発明においては、機械的圧力に強い窒化膜がモール
ド樹脂形成時におけるリンガラスフート膜の周辺部にク
ラックが生じるのを抑制しひいては湿気による電気接続
線等の金属における腐食を抑制するものである。In this invention, the nitride film, which is resistant to mechanical pressure, suppresses the occurrence of cracks around the phosphor glass foot film during mold resin formation, and further suppresses corrosion of metals such as electrical connection wires due to moisture. .
以下にこの発明の一実施例第１図＋ｌＬｌ ［ｂｌに基
づいて説明すると、図において（１）ｉポンディングパ
ッド窓（８）を除く周辺回路部上及びメモリ部上全面に
電気接続線（７）を介して設けられたリンガラスコート
膜であり、特に半導体チップ＋１０１ ＠端部には設け
ていないものである。（１４ａ）は半導体チップ（１０
１四端部の酸化膜（３）上及び周辺回路部のリンガラス
コート膜（９ｂ）上、更にメモリ部のフローティングゲ
ート（４）上Ｎ５を除くリンガラスコート膜（９ｂ）上
全面に付着して半導体チップ（１０）表面に設けられた
機械的圧力に強く、湿気を吸収しない窒化酸である。An embodiment of the present invention will be described below based on FIG. ), and is not particularly provided on the edge of the semiconductor chip. (14a) is a semiconductor chip (10
1, on the oxide film (3) at the four ends, on the phosphorus glass coat film (9b) on the peripheral circuit part, and on the entire surface of the phosphorus glass coat film (9b) except for N5 on the floating gate (4) in the memory part. It is a nitriding acid that is resistant to mechanical pressure and does not absorb moisture.
上記の様に構成された紫外線消去型半導体記憶装置は、
半導体チップ（１ωのリンガラスコート膜（９ｂ）形収
後連続して窒化膜Ｈを形成し、その後記憶情報を書き込
んで電気的特性のテストを行いテストか終了した後紫外
線を照射して記憶情報の消去を行うものであるが、この
際、電荷蓄積用のフローティングゲート（４）上部には
窒化膜（１４ａ）がないので紫外線が篭られることはな
く、通常の紫外線による記憶情報の消去と全く同様の条
件で行えるものであり、更に、メモリ部上に網目状に設
けられた窒化膜（１４ａ）がメモリ部上のリンガラスコ
ートｇ（１）の補強をし、モールド樹脂体賎形成時の圧
力によるリンガラスコート膜（９ｂ）のクラック発生を
更に防止するものである。The ultraviolet erasable semiconductor memory device configured as described above is
After the semiconductor chip (1ω phosphorus glass coating film (9b)) is formed, a nitride film H is continuously formed, and then memory information is written and the electrical characteristics are tested. After the test is completed, ultraviolet rays are irradiated to erase the memory information. However, at this time, since there is no nitride film (14a) above the floating gate (4) for charge storage, ultraviolet rays are not trapped, and the erasure of stored information is completely different from normal ultraviolet rays. It can be carried out under the same conditions, and the nitride film (14a) provided in a mesh shape on the memory part reinforces the phosphor glass coat g (1) on the memory part, and when forming the mold resin body. This further prevents the occurrence of cracks in the phosphor glass coated film (9b) due to pressure.
また、素子の形成されない半導体チップ（１０）同端邪
にはリンガラスコート膜（９ｂ）を形成せず窒化膜（１
４ａ）のみを形成したので、リートフレームロから侵入
する湿気の入口に最も近い半導体チップ（］Ｏ）側面か
らの湿気の侵入は全くなく、その上機械的強度も非常に
高まるものである。Further, the phosphor glass coat film (9b) is not formed on the same end of the semiconductor chip (10) on which no element is formed, and the nitride film (10) is not formed.
Since only 4a) is formed, there is no intrusion of moisture from the side surface of the semiconductor chip (]O) which is closest to the inlet of moisture intruding from the Rietflame, and furthermore, the mechanical strength is greatly increased.
史に、リンガラスコート膜（９ｂ）端部を窒化膜（１４
１Ｌ）が広く覆っているのでリンガラスコート膜（９ｂ
）と窒化膜（１４ａ）との界面から湿気が浸入すること
はないものである。Historically, the end of the phosphorus glass coated film (9b) was coated with a nitride film (14).
1L) is widely covered, so the phosphorus glass coating film (9b
) and the nitride film (14a), moisture will not infiltrate from the interface.
第２図（ＩＬ）及びｆｂ＋は各々この発明の他の実施例
を示す半導体記憶素子（１０１の断面及び上面図であり
、（１４１））はフローティングゲート（４１上部に於
る電気接ａ線（７）の設けられていない部分を除くリン
ガラスコート膜（９ｂ）上全面に付着して設けられ、従
って上記のフローティングゲート（４１上であってもア
ルミ等の電気接続線（７）上ては付着して設けられた機
械的圧力に強く、ａ気を吸収しない窒化膜である。FIG. 2 (IL) and fb+ are a cross-sectional view and a top view of a semiconductor memory element (101) showing other embodiments of the present invention, respectively, (141) is a floating gate (41) with an electric tangent a line ( 7) is attached to the entire surface of the phosphor glass coating film (9b) except for the part where it is not provided, so even if it is on the floating gate (41), it will not be on the electrical connection wire (7) made of aluminum or the like. It is a nitride film that is resistant to mechanical pressure and does not absorb aerosols.
電気接続線（７）は紫外線を遮るものであるから電荷蓄
積用の７０−ティングケート（４）上には必ず４気接続
線（７）の無い部分が存在し、この部分に窒化膜（１４
１））が付着されていない部分を設けたものであり、こ
の様な窒化膜（ｌａｂ）の付着されていない部分かたと
乏、極値かな面積であっても、紫外線のように短い波長
の光は、その極値かな面積部分を通り抜け、電荷蓄積用
のフローティングゲート（４１に到達し記憶情報全消去
するものである。従って、湿気が窒化膜（ｔ４ｂ）で峨
られ、リンガラスコート膜（１）に触れることはほとん
どなく、たとえ触れたとしても、リンガラスコート膜（
９ｂ）の湿気が触れた部分の下には電気接続線（７）が
ないので、電気接続線（７）が腐食されることはないも
のであり、更に機械的強度に優れた窒化膜（１４１））
がリンガラスコート膜（９）のほとんど全面を覆ってい
るので、リンガラスコート膜（９ｂ）にクラックが生じ
ることはほとんどないものである。Since the electrical connection line (7) is for blocking ultraviolet rays, there is always a part on the 70-ring gate (4) for charge storage where there is no 4-wire connection line (7), and this part is covered with a nitride film (14).
1))) is provided, and even if the area to which the nitride film (LAB) is not attached is small or extremely large, it will not be able to absorb short wavelengths such as ultraviolet rays. The light passes through the area of the extreme value, reaches the floating gate (41) for charge storage, and erases all stored information.Therefore, moisture is accumulated in the nitride film (t4b), and the phosphor glass coating film ( 1) is rarely touched, and even if it is, the phosphorus glass coating film (
Since there is no electrical connection wire (7) under the part of 9b) that is exposed to moisture, the electrical connection wire (7) will not be corroded, and the nitride film (141 ))
covers almost the entire surface of the phosphorous glass coated film (9), so cracks are almost never generated in the phosphorous glass coated film (9b).
なお、上記実施例ではリンガラスコート膜（９ｂ）上の
フローティングゲート（４）上部にのみ窒化膜（１４ａ
）（１４’ｂ）の付着されていない部分を設けたが、窒
化膜をリンガラスコート膜（９ｂ）全面に設は電荷蓄積
用のフローティングゲート（４１の上及びその池の部分
に紫外線が通過できる程度の極値かな面積の窒化膜が付
着されていない部分を数多く設けても艮い。In the above embodiment, the nitride film (14a) is formed only on the upper part of the floating gate (4) on the phosphorus glass coat film (9b).
) (14'b) is not attached, but a nitride film is provided on the entire surface of the phosphorus glass coated film (9b) so that ultraviolet rays pass through the floating gate (41 and its pond area) for charge accumulation. It is no problem even if there are many parts to which the nitride film is not attached, the area of which is the extreme value possible.
また、上記実施例に於ては、リンガラスコート膜（９ｂ
）ｆ：半導体チップ（１０）の同端部及びポンディング
パッド窓（８）を除いて形成されたものとしたが、半導
体チップ（１０１の同端部にリンガラスコート膜を設け
、第４図に放るリンガラスコート膜（９ａ）と同様にし
ても良いものである〇更に、上記実施例に：ＪＡては、
窒化膜（１４ａ Ｑ４ｂ）をメモリ部上に設けたが、そ
れらを削除しても良く、その場合でも半導体チップｔｉ
ｏ＋の同端部及び周辺回路部上には窒化膜が存在してい
るため、半導体チップ（１０）の周端部からリンガラス
コート膜のクラックが生じることを防止できるものであ
る。In addition, in the above embodiment, the phosphorus glass coated film (9b
)f: Formed except for the same end of the semiconductor chip (10) and the bonding pad window (8), but a phosphorus glass coating film was provided on the same end of the semiconductor chip (101), as shown in FIG. 〇Furthermore, in the above example: JA,
Although the nitride film (14a Q4b) is provided on the memory part, it is also possible to remove it, and even in that case, the semiconductor chip ti
Since the nitride film exists on the same end of the o+ and the peripheral circuit section, it is possible to prevent the phosphor glass coating film from cracking from the peripheral end of the semiconductor chip (10).
この発明は以上説明したとおり、半導体基板上における
フローティングゲート上部を除いた少なくとも周辺部に
リンガラスコート膜を介して、窒化膜を設は念ので、紫
外線による記憶情報の消去を妨げることなく、かつ半導
体チップの同端部からリンガラスコート膜のクラックが
生じることを防ぐことができる効果がある。As explained above, in this invention, a nitride film is provided on at least the peripheral part of the semiconductor substrate except for the upper part of the floating gate through a phosphorus glass coating film, so that the erasure of stored information by ultraviolet rays is not hindered, and This has the effect of preventing cracks in the phosphor glass coating film from occurring from the same end of the semiconductor chip.
第１図ｆａｔはこの発明の一実施例を示す紫外線消去型
半導体記憶素子の第１図ｆｂ＋のＩ −Ｉ’を示す断面
図、第１図（ｋｎはこの一実施例に於るフローティング
ゲート、リンガラスコート膜及び窒化膜の形状を示す上
面図、第２図ｆｌＬｌはこの発明の他の実施例を示す紫
外線消去型半導体記憶素子のＪ２図ｔｂ＋のＩＩ−ＩＩ
’部を示す断面図、第２図（ｂｌはこの他の実施例に於
るフローティングゲート、電気接続線、リンガラスコー
ト膜及び窒化膜の形状を示す上面図、Ｍ８図は紫外線消
去型半導体記憶装置の全体構成を示す断面図、第４図は
従来の紫外線消去型半導体素子を示す断面図である。
図において、１１１は半導体基板、（４）はマトリクス
状に配設された複数のフローティングゲート、（７）は
電気接続線、（９ａ）（９ｂ）はリンガラスコート膜、
（１０）は半導体チップ、ｔ１３ｆｌモールド欄脂体、
Ｃｘ４ａ）（ｉ４ｂ）は窒化膜ｆ６る。
なお、各図中同一符号は、同一または相当部分を示す。FIG. 1 fat is a sectional view taken along I-I' of FIG. A top view showing the shapes of the phosphorus glass coat film and the nitride film, FIG. 2 flLl is II-II of FIG.
Fig. 2 is a cross-sectional view showing the part ', (bl is a top view showing the shapes of the floating gate, electrical connection line, phosphorous glass coat film and nitride film in another embodiment, and Fig. M8 is an ultraviolet erasable semiconductor memory. FIG. 4 is a cross-sectional view showing the overall configuration of the device, and FIG. 4 is a cross-sectional view showing a conventional ultraviolet erasable semiconductor element. In the figure, 111 is a semiconductor substrate, and (4) is a plurality of floating gates arranged in a matrix. , (7) is an electrical connection line, (9a) and (9b) are phosphor glass coated films,
(10) is a semiconductor chip, t13fl mold ballast body,
Cx4a) (i4b) is a nitride film f6. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (5)
を有した紫外線消去型メモリセルを複数有したメモリ部
と、このメモリ部の周辺に設けられた周辺回路部と、上
記メモリ部及び周辺回路部上に設けられこれらを電気的
に接続する電気接続線とを有し、上記電気接続線上並び
に上記電気接続線以外の上記メモリ部及び周辺回路部上
にリンガラスコート膜が設けられ、かつ半導体基板上に
おける上記フローティングゲート上部を除いた少なくと
も周辺部に上記リンガラスコート膜を介して窒化膜が形
成された半導体チップ、この半導体チップ全面を被覆、
封止したモールド樹脂体を備えた紫外線消去型半導体記
憶装置。(1) A memory section having a plurality of ultraviolet erasable memory cells with floating gates arranged on a semiconductor substrate, a peripheral circuit section provided around this memory section, and the memory section and peripheral circuit section. an electrical connection line provided on the semiconductor substrate for electrically connecting these, a phosphor glass coating film is provided on the electrical connection line and on the memory section and peripheral circuit section other than the electrical connection line, and a semiconductor substrate; a semiconductor chip on which a nitride film is formed via the phosphorus glass coating film at least in the peripheral area excluding the upper part of the floating gate; the entire surface of the semiconductor chip is covered;
An ultraviolet erasable semiconductor memory device equipped with a sealed molded resin body.
る特許請求の範囲第１項記載の紫外線消去型半導体記憶
装置。(2) The ultraviolet erasable semiconductor memory device according to claim 1, wherein the electrical connection line is made of aluminum.
て設けられているものとし、窒化膜は半導体基板の周端
部に延在して設けられていることを特徴とする特許請求
の範囲第１項または第２項記載の紫外線消去型半導体記
憶装置。(3) A patent claim characterized in that the phosphorus glass coating film is provided on the semiconductor substrate except for the peripheral edge, and the nitride film is provided extending to the peripheral edge of the semiconductor substrate. The ultraviolet erasable semiconductor memory device according to item 1 or 2.
ガラスコート膜上全面に設けられたことを特徴とする特
許請求の範囲第１項ないし第３項の何れかに記載の紫外
線消去型半導体記憶装置。(4) The ultraviolet erasable semiconductor memory device according to any one of claims 1 to 3, wherein the nitride film is provided on the entire surface of the phosphorus glass coat film except for the upper part of the floating gate. .
続線の設けられていない部分を除くリンガラスコート膜
上面に設けられたことを特徴とする特許請求の範囲第１
項ないし第３項の何れかに記載の紫外線消去型半導体記
憶装置。(5) Claim 1, characterized in that the nitride film is provided on the upper surface of the phosphor glass coating film except for the part where the electrical connection line is not provided on the upper part of the floating gate.
3. The ultraviolet erasable semiconductor memory device according to any one of items 1 to 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59235759A JPS61113272A (en) | 1984-11-08 | 1984-11-08 | Ultraviolet ray elimination type semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59235759A JPS61113272A (en) | 1984-11-08 | 1984-11-08 | Ultraviolet ray elimination type semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61113272A true JPS61113272A (en) | 1986-05-31 |
Family
ID=16990813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59235759A Pending JPS61113272A (en) | 1984-11-08 | 1984-11-08 | Ultraviolet ray elimination type semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61113272A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0663695A2 (en) * | 1993-12-27 | 1995-07-19 | Kabushiki Kaisha Toshiba | Electrically erasable programmable non-volatile semiconductor memory device having select gates and small number of contact holes, and method of manufacturing the device |
| JP2008205054A (en) * | 2007-02-17 | 2008-09-04 | Seiko Instruments Inc | Semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5519850A (en) * | 1978-07-31 | 1980-02-12 | Hitachi Ltd | Semiconductor |
| JPS5850771A (en) * | 1981-09-21 | 1983-03-25 | Hitachi Ltd | High integration rom enable of rewriting and manufacture thereof |
| JPS58225649A (en) * | 1982-06-23 | 1983-12-27 | Fujitsu Ltd | Semiconductor device and preparation thereof |
-
1984
- 1984-11-08 JP JP59235759A patent/JPS61113272A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5519850A (en) * | 1978-07-31 | 1980-02-12 | Hitachi Ltd | Semiconductor |
| JPS5850771A (en) * | 1981-09-21 | 1983-03-25 | Hitachi Ltd | High integration rom enable of rewriting and manufacture thereof |
| JPS58225649A (en) * | 1982-06-23 | 1983-12-27 | Fujitsu Ltd | Semiconductor device and preparation thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0663695A2 (en) * | 1993-12-27 | 1995-07-19 | Kabushiki Kaisha Toshiba | Electrically erasable programmable non-volatile semiconductor memory device having select gates and small number of contact holes, and method of manufacturing the device |
| EP0663695A3 (en) * | 1993-12-27 | 1995-12-20 | Toshiba Kk | Electrically erasable programmable non-volatile semiconductor memory device having select gates and small number of contact holes, and method of manufacturing the device. |
| US5589699A (en) * | 1993-12-27 | 1996-12-31 | Kabushiki Kaisha Toshiba | Electrically erasable programmable non-volatile semiconductor memory device having select gates and small number of contact holes |
| JP2008205054A (en) * | 2007-02-17 | 2008-09-04 | Seiko Instruments Inc | Semiconductor device |
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