JPS6110989B2 - - Google Patents
Info
- Publication number
- JPS6110989B2 JPS6110989B2 JP9383976A JP9383976A JPS6110989B2 JP S6110989 B2 JPS6110989 B2 JP S6110989B2 JP 9383976 A JP9383976 A JP 9383976A JP 9383976 A JP9383976 A JP 9383976A JP S6110989 B2 JPS6110989 B2 JP S6110989B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- transistor
- parasitic
- resistance means
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000003071 parasitic effect Effects 0.000 claims description 25
- 239000012535 impurity Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 230000015556 catabolic process Effects 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005686 electrostatic field Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
Description
【発明の詳細な説明】
この発明はMOSデバイスのようなMIS型集積
回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to MIS type integrated circuits such as MOS devices.
MIS型集積回路は外部回路への接続端子からの
静電界の影響で、機能回路部が容易に破壊される
欠点がある。機能回路部が絶縁ゲート構造である
ときには絶縁破壊を起こし、接合領域であるとき
には過電流破壊を引き起す。従来のMIS型集積回
路では機能回路と外部回路との間に拡散抵抗、ト
ランジスタのドレイン接合降服を利用する保護回
路を有する。しかし乍ら従来の保護回路は高電
圧・小容量の静電チヤージに対しての保護を行う
のみであつて高電圧・大容量からの保護作用には
無防備であつた。 MIS type integrated circuits have the disadvantage that their functional circuits are easily destroyed by the influence of electrostatic fields from connection terminals to external circuits. When the functional circuit section has an insulated gate structure, dielectric breakdown occurs, and when it is a junction region, overcurrent breakdown occurs. Conventional MIS type integrated circuits have a protection circuit that uses diffused resistance and transistor drain junction breakdown between functional circuits and external circuits. However, conventional protection circuits only provide protection against electrostatic charges caused by high voltage and small capacity, and are not protected against high voltage and large capacity.
この発明の目的は、高感度大容量放電能力の保
護回路を有するMIS型集積回路を提供することに
ある。 An object of the present invention is to provide an MIS type integrated circuit having a protection circuit with high sensitivity and large capacity discharge capability.
この発明のMIS型集積回路は、外部回路への接
続端子PADと内部の機能回路用素子ＱJ，ＱIと
の接続部に素子破壊を防止する保護回路を有する
集積回路において、前記端子PADと前記素子Ｑ
J，ＱIとの間に細長い不純物領域から成る２個の
抵抗素子R1，R2と該抵抗素子R1，R2をそれぞれ
ドレイン領域とし、接地電位等の基準電位の与え
られた不純物領域をそれぞれソース領域とする２
個の第１層配線ゲート型寄生トランジスタＱSお
よび第１層配線よりも厚い酸化膜上に形成される
第２層配線ゲート型寄生トランジスタＱAとを含
み、端子PADに近い前記抵抗端子R2の第一の端
部に前記第２層配線ゲート型寄生トランジスタＱ
Aのゲート電極を接続し、前記機能回路に近い前
記抵抗素子R1の第二の端部に前記第１層配線ゲ
ート型寄生トランジスタＱSのゲート電極を接続
し、且つ前記第二の端部に機能回路部と同一ゲー
ト構造を一部に有する不純物領域を接続し、前記
トランジスタＱS，ＱAのソース領域と共に前記ゲ
ート構造のゲート電極を接続することを特徴とす
る。 The MIS type integrated circuit of the present invention is an integrated circuit having a protection circuit for preventing element destruction at the connection between a connection terminal PAD to an external circuit and internal functional circuit elements Q J and Q I. The element Q
Two resistance elements R 1 and R 2 are formed of elongated impurity regions between J and Q I , and the impurity regions are provided with a reference potential such as a ground potential, with the resistance elements R 1 and R 2 serving as drain regions, respectively. 2 with each as the source region
The resistance terminal R 2 is close to the terminal PAD . The second layer wiring gate type parasitic transistor Q
A , the gate electrode of the first layer wiring gate type parasitic transistor Q S is connected to the second end of the resistance element R 1 near the functional circuit, and the gate electrode of the first layer wiring gate type parasitic transistor Q S is connected to the second end of the resistance element R An impurity region having a part of the same gate structure as the functional circuit portion is connected to the gate electrode, and a gate electrode of the gate structure is connected to the source regions of the transistors Q S and Q A .
この発明の集積回路は、寄生トランジスタＱ
A，ＱSが順方向で保護回路に結合される、すなわ
ちゲートが接続端子側に接続されているため、高
電圧・大容量の静電チヤージに対して充分に放電
能力を有し確実な保護作用を発揮する。第２層配
線ゲート型寄生トランジスタＱAはゲート絶縁膜
が全ゲート領域で厚いため、端子PADに近い位
置にゲート電極を接続し、立上りの早い放電を行
うとともに保護回路自身の耐高電圧性が良い。
又、第１層配線ゲート型寄生トランジスタＱSは
薄いゲート絶縁膜を有するため閾値電圧は低い
が、ゲート絶縁膜の耐圧は低い。従つて機能回路
側にゲート電極を接続し、ゲート絶縁膜が保護さ
れる一方、機能回路部へのより低い電圧でのクラ
ンプ回路となる。ゲート構造を一部に含む不純物
領域は立上り遅くともさらに低い降服電圧である
アバランシユ降服によるため、機能回路に加わる
電圧が極めて低くなるとともに静電チヤージの放
電能力も高く、回路動作をより安全にすることが
できる。 The integrated circuit of this invention has a parasitic transistor Q
Since A and Q S are coupled to the protection circuit in the forward direction, that is, the gate is connected to the connection terminal side, it has sufficient discharge capacity against high voltage and large capacity electrostatic charge, ensuring reliable protection. exerts its effect. Since the gate insulating film of the second-layer wiring gate type parasitic transistor Q A is thick over the entire gate region, the gate electrode is connected to a position close to the terminal PAD to achieve a quick rising discharge and to improve the high voltage withstand capability of the protection circuit itself. good.
Furthermore, since the first layer wiring gate type parasitic transistor Q S has a thin gate insulating film, its threshold voltage is low, but the breakdown voltage of the gate insulating film is low. Therefore, the gate electrode is connected to the functional circuit side, and while the gate insulating film is protected, it becomes a clamp circuit that applies a lower voltage to the functional circuit section. Since the impurity region that partially includes the gate structure undergoes avalanche breakdown, which has an even lower breakdown voltage at the latest, the voltage applied to the functional circuit becomes extremely low and the ability to discharge electrostatic charges is high, making circuit operation safer. I can do it.
次にこの発明の実施例をより良く理解するため
に、この発明の実施例につき図を用いて説明す
る。 Next, in order to better understand the embodiments of the present invention, the embodiments of the present invention will be explained using figures.
第１図はこの発明の好ましい実施例の回路図で
ある。この実施例は外部回路への接続端子PAD
から機能回路部のトランジスタＱJ，ＱIへの結合
を抵抗素子R1，R2を通して行う。抵抗素子R1，
R2の結合点ｃは両端ａ，ｂの中間点であり、こ
の素子は同時に寄生トランジスタＱA，ＱSのドレ
イン領域である。端子PADに接続する端部Ａに
は第２層配線であるアルミニウムゲート型の寄生
トランジスタＱAのゲート電極を結線する。他端
Ｂには第１層配線であるシリコンゲート型寄生ト
ランジスタＱSのゲート電極が接続し、この端部
に機能回路部の通常のトランジスタのゲート構造
を有するシリコンゲート型トランジスタＱDのド
レイン領域が接続している。このトランジスタＱ
Dのゲート電極は他の寄生トランジスタＱA，ＱS
と共に基準端子GNDに接続する。尚点線で配線
を示した部分は機能回路部である。 FIG. 1 is a circuit diagram of a preferred embodiment of the invention. This example shows the connection terminal PAD to the external circuit.
Coupling from the transistors Q J and Q I of the functional circuit section is performed through resistive elements R 1 and R 2 . Resistance element R 1 ,
The connection point c of R 2 is the midpoint between the ends a and b, and this element is also the drain region of the parasitic transistors Q A and Q S . A gate electrode of an aluminum gate type parasitic transistor Q A , which is a second layer wiring, is connected to the end A connected to the terminal PAD. The other end B is connected to the gate electrode of a silicon gate parasitic transistor Q S , which is the first layer wiring, and this end is the drain region of a silicon gate transistor Q D , which has the gate structure of a normal transistor in the functional circuit section. is connected. This transistor Q
The gate electrode of D is connected to other parasitic transistors Q A , Q S
and the reference terminal GND. Note that the portion where wiring is indicated by dotted lines is a functional circuit portion.
第２図は第１図の実施例の実線で配線を示した
部分の平面図、第３図は第２図の各部の断面図で
ある。この実施例はボロン濃度１×1016cm-3のＰ
型シリコン単結晶基体１の表面にアルミゲート型
寄生トランジスタＱAとシリコンゲート型寄生ト
ランジスタＱSと通常のシリコンゲート型トラン
ジスタＱDとが形成されている。アルミゲート型
寄生トランジスタのゲート電極２はドレイン領域
である抵抗素子３の一端および外部回路への端子
１４への接続用のアルミニウム配線である。この
寄生トランジスタＱAはゲート絶縁膜が不活性領
域を覆う1.0μ程度の厚いSiO2膜４の一部であ
る。シリコンゲート型寄生トランジスタＱSは厚
いゲート絶縁膜４の両側に400Åの薄いSiO2のゲ
ート絶縁膜５，５′を有し、シリコンゲート電極
６が抵抗素子３の端部となるドレイン領域に配線
７により結合されている。シリコンゲート型トラ
ンジスタＱDは400Åの薄いSiO2のゲート絶縁膜
８の上面のゲート電極９が基準端子への配線１０
に結合する。基体１の裏面には基体電極１２があ
り、厚い絶縁膜４の下には寄生チヤンネル防止用
の高濃度領域１１がある。 FIG. 2 is a plan view of a portion of the embodiment shown in FIG. 1 where wiring is indicated by solid lines, and FIG. 3 is a sectional view of each portion of FIG. 2. This example uses P with a boron concentration of 1×10 16 cm -3
An aluminum gate parasitic transistor Q A , a silicon gate parasitic transistor Q S , and a normal silicon gate transistor Q D are formed on the surface of a silicon single crystal substrate 1 . The gate electrode 2 of the aluminum gate type parasitic transistor is an aluminum wiring for connection to one end of the resistance element 3, which is a drain region, and a terminal 14 to an external circuit. This parasitic transistor Q A is a part of a SiO 2 film 4 with a thickness of about 1.0 μm whose gate insulating film covers an inactive region. The silicon gate type parasitic transistor Q S has thin gate insulating films 5 and 5' of SiO 2 of 400 Å on both sides of a thick gate insulating film 4, and a silicon gate electrode 6 is connected to the drain region where the end of the resistor element 3 is connected. 7. In the silicon gate transistor QD, the gate electrode 9 on the top surface of the 400 Å thin SiO 2 gate insulating film 8 is connected to the wiring 10 to the reference terminal.
join to. There is a base electrode 12 on the back surface of the base 1, and under the thick insulating film 4 there is a high concentration region 11 for preventing parasitic channels.
この実施例はMIS型集積回路の保管状態と同様
に基準端子と基体電極が同電位であると、外部回
路への端子の過電圧印加が12Vを超えるときにア
ルミゲート型寄生トランジスタＱAがきわめて急
峻に応答して放電を開始し、若干遅れてシリコン
ゲート型トランジスタＱSが10Vを超える過電圧
入力に対して放電し、さらにトランジスタＱDの
ドレイン接合が20Vを超える過電圧に対してアバ
ランシエ降服する。これらの放電能力は応答速
度・放電能力共に従来に比してきわめて早く、
1nS以内に応答を開始する。２個の抵抗素子の直
列抵抗値は、2KΩ以上であることが好ましく、
機能回路部での10pF程度の入力容量と合せて
20nS程度の時定数で波形が緩和され、保護用の
トランジスタＱS，ＱDでの保護効果の立上りを確
保する。また外部回路への接続端子１４に最も近
く厚いゲート膜を有する寄生トランジスタＱAが
あるので保護回路の破壊も少ない。それに続くト
ランジスタＱS，ＱDは寄生トランジスタＱAの導
通及び抵抗R1，R2により印加電圧が低く抑えら
れるので、これらトランジスタＱS，ＱDも破壊す
ることがない。 In this example, when the reference terminal and the base electrode are at the same potential as in the storage state of the MIS type integrated circuit, when the overvoltage applied to the terminal to the external circuit exceeds 12V, the aluminum gate type parasitic transistor Q A becomes extremely steep. After a slight delay, the silicon gate transistor Q S discharges in response to an overvoltage input exceeding 10V, and furthermore, the drain junction of the transistor Q D undergoes avalanche breakdown in response to an overvoltage input exceeding 20V. Both the response speed and discharge capacity are extremely fast compared to conventional ones.
Starts response within 1nS. The series resistance value of the two resistance elements is preferably 2KΩ or more,
In addition to the input capacitance of about 10 pF in the functional circuit section,
The waveform is relaxed with a time constant of about 20 nS, and the rise of the protection effect in the protection transistors Q S and Q D is ensured. Furthermore, since the parasitic transistor Q A having a thick gate film is located closest to the connection terminal 14 to the external circuit, the protection circuit is less likely to be destroyed. Since the voltage applied to the subsequent transistors Q S and Q D is kept low by the conduction of the parasitic transistor Q A and the resistors R 1 and R 2 , these transistors Q S and Q D will not be destroyed.
上にこの発明の一実施例を説明したが、シリコ
ンゲート型トランジスタＱDは単にドレイン領域
を有するゲート構造を利用するのみであるため、
ゲートコントロール型ダイオードのようにソース
領域を持たないMOSデバイスで代用できる。又
この発明は高電圧・大容量からの静電チヤージの
接色に有効であるため、機能回路部のトランジス
タＱIのゲート構造と共にドレイン領域を入力と
するトランジスタＱJへの保護作用をも有する。 Although one embodiment of the present invention has been described above, since the silicon gate type transistor Q D simply utilizes a gate structure having a drain region,
A MOS device without a source region, such as a gate-controlled diode, can be used instead. Furthermore, since this invention is effective in counteracting electrostatic charge from high voltage and large capacitance, it also has a protective effect on the gate structure of transistor Q I in the functional circuit section as well as on transistor Q J whose drain region is input. .
第１図はこの発明の一実施例の回路図、第２図
は第１図の実施例の保護回路部の平面図、第３図
Ａ，Ｂ，Ｃはそれぞれ第２図のＡ―Ａ，Ｂ―Ｂ，
Ｃ―Ｃに於ける断面図である。図中、ＱAはアル
ミニウムをゲート電極とする寄生トランジスタ、
ＱSはシリコンをゲート電極とする寄生トランジ
スタ、ＱDは通常のシリコンゲート型トランジス
タである。１は半導体基板、２はゲート電極兼配
線層、３，１３は不純物拡散領域、４は厚い酸化
膜、６はシリコンゲート電極、７，１０は配線層
である。
FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a plan view of the protection circuit section of the embodiment of FIG. 1, and FIGS. 3A, B, and C are A-A in FIG. B-B,
It is a sectional view in CC. In the figure, Q A is a parasitic transistor whose gate electrode is aluminum;
Q S is a parasitic transistor with a silicon gate electrode, and Q D is a normal silicon gate type transistor. 1 is a semiconductor substrate, 2 is a gate electrode/wiring layer, 3 and 13 are impurity diffusion regions, 4 is a thick oxide film, 6 is a silicon gate electrode, and 7 and 10 are wiring layers.
Claims (1)
からなる第１の抵抗手段を設け、該第１の抵抗手
段をドレイン領域とする高耐圧の第１の寄生絶縁
ゲート型トランジスタのゲート電極を前記第１の
抵抗手段の前記外部接続端子に近い側に接続した
保護回路を有する集積回路において、第１の抵抗
手段と前記内部機能回路との間に不純物領域から
なる第２の抵抗手段を設け、この第２の抵抗手段
をドレイン領域とする第２の寄生絶縁ゲート型ト
ランジスタのゲート電極を前記第２の抵抗手段の
前記機能回路に近い側に接続し、前記第２の寄生
絶縁ゲート型トランジスタのオン電圧を第１の寄
生絶縁ゲート型トランジスタより低くしたことを
特徴とするMIS型集積回路。1. A first resistance means made of an impurity region is provided between an external connection terminal and an internal functional circuit, and a gate electrode of a first parasitic insulated gate transistor with a high withstand voltage is connected to the first resistance means as a drain region. In an integrated circuit having a protection circuit connected to a side of the first resistance means close to the external connection terminal, a second resistance means made of an impurity region is provided between the first resistance means and the internal functional circuit; A gate electrode of a second parasitic insulated gate transistor having a second resistance means as a drain region is connected to a side of the second resistance means near the functional circuit, and the second parasitic insulated gate transistor is turned on. An MIS type integrated circuit characterized in that the voltage is lower than that of a first parasitic insulated gate transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9383976A JPS5318979A (en) | 1976-08-05 | 1976-08-05 | Mis type integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9383976A JPS5318979A (en) | 1976-08-05 | 1976-08-05 | Mis type integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5318979A JPS5318979A (en) | 1978-02-21 |
| JPS6110989B2 true JPS6110989B2 (en) | 1986-04-01 |
Family
ID=14093550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9383976A Granted JPS5318979A (en) | 1976-08-05 | 1976-08-05 | Mis type integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5318979A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63201209U (en) * | 1987-06-16 | 1988-12-26 |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60257558A (en) * | 1984-06-04 | 1985-12-19 | Nec Corp | Semiconductor integrated circuit device |
| JPH03111426U (en) * | 1990-02-28 | 1991-11-14 |
-
1976
- 1976-08-05 JP JP9383976A patent/JPS5318979A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63201209U (en) * | 1987-06-16 | 1988-12-26 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5318979A (en) | 1978-02-21 |
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