JPS61107027U - - Google Patents
Info
- Publication number
- JPS61107027U JPS61107027U JP19310484U JP19310484U JPS61107027U JP S61107027 U JPS61107027 U JP S61107027U JP 19310484 U JP19310484 U JP 19310484U JP 19310484 U JP19310484 U JP 19310484U JP S61107027 U JPS61107027 U JP S61107027U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- memory
- switching circuit
- model registration
- enhancement type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Stand-By Power Supply Arrangements (AREA)
- Power Sources (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は本考案によるメモリ電源切換回路の構
成図、第２図、第３図は従来のメモリ電源切換回
路の構成図を示している。
２…論理回路用電源、３…メモリ、４…バツク
アツプ電源、７…電圧判定回路、９…Ｐチヤネル
エンハンスメント型ＭＯＳ ＦＥＴ、１０…ＣＭ
ＯＳインバータ。
FIG. 1 is a block diagram of a memory power supply switching circuit according to the present invention, and FIGS. 2 and 3 are block diagrams of conventional memory power supply switching circuits. 2...Power supply for logic circuit, 3...Memory, 4...Backup power supply, 7...Voltage judgment circuit, 9...P channel enhancement type MOS FET, 10...CM
OS inverter.
Claims (1)
の給電路に挿入され、正常時には導通して外部電
源より前記メモリへの給電を行なわせ、外部電源
の電圧降下時には不導通となつて前記バツクアツ
プ電源から前記メモリへの給電が行なわれるよう
に制御されるメモリ電源切換回路であつて、切換
素子としてエンハンスメント型ＭＯＳ ＦＥＴを
用い、給電路に外部電源に対して逆接続で挿入し
たことを特徴とするメモリ電源切換回路。 ２ 実用新案登録請求の範囲第１項に記載のメモ
リ電源切換回路において、エンハンスメント型Ｍ
ＯＳ ＦＥＴの駆動をＣＭＯＳインバータにて行
なうことを特徴とするメモリ電源切換回路。[Claims for Utility Model Registration] 1. A backup power supply is inserted into the power supply path to the memories connected in parallel, and is electrically conductive during normal operation to supply power to the memory from the external power supply, and is non-conductive when the voltage of the external power supply drops. The memory power supply switching circuit is controlled so that power is supplied from the backup power supply to the memory, using an enhancement type MOS FET as a switching element, and inserting it into the power supply path in reverse connection with respect to the external power supply. A memory power supply switching circuit characterized by: 2. In the memory power supply switching circuit set forth in claim 1 of the utility model registration claim, an enhancement type M
A memory power supply switching circuit characterized in that an OS FET is driven by a CMOS inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19310484U JPS61107027U (en) | 1984-12-20 | 1984-12-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19310484U JPS61107027U (en) | 1984-12-20 | 1984-12-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61107027U true JPS61107027U (en) | 1986-07-07 |
Family
ID=30750522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19310484U Pending JPS61107027U (en) | 1984-12-20 | 1984-12-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61107027U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0344721A (en) * | 1989-07-12 | 1991-02-26 | Toshiba Corp | Detecting circuit for memory back-up voltage |
| JPH03218226A (en) * | 1990-01-22 | 1991-09-25 | Hokuyo Automatic Co | Preventing circuit for damage due to reverse power source connection of sensor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5653223B2 (en) * | 1975-02-20 | 1981-12-17 | ||
| JPS5723123A (en) * | 1980-07-16 | 1982-02-06 | Fujitsu Ltd | Semiconductor device having volatile memory |
-
1984
- 1984-12-20 JP JP19310484U patent/JPS61107027U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5653223B2 (en) * | 1975-02-20 | 1981-12-17 | ||
| JPS5723123A (en) * | 1980-07-16 | 1982-02-06 | Fujitsu Ltd | Semiconductor device having volatile memory |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0344721A (en) * | 1989-07-12 | 1991-02-26 | Toshiba Corp | Detecting circuit for memory back-up voltage |
| JPH03218226A (en) * | 1990-01-22 | 1991-09-25 | Hokuyo Automatic Co | Preventing circuit for damage due to reverse power source connection of sensor |
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