JPS6097669A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS6097669A JPS6097669A JP58204663A JP20466383A JPS6097669A JP S6097669 A JPS6097669 A JP S6097669A JP 58204663 A JP58204663 A JP 58204663A JP 20466383 A JP20466383 A JP 20466383A JP S6097669 A JPS6097669 A JP S6097669A
- Authority
- JP
- Japan
- Prior art keywords
- region
- emitter
- silicon layer
- resistance region
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract description 11
- 238000005468 ion implantation Methods 0.000 abstract description 7
- 230000010354 integration Effects 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 229910052785 arsenic Inorganic materials 0.000 abstract description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 3
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体集積回路装置に係り、特にバイポーラト
ランジスタ、ＭＯＳトランジスタ等の能動素子を同一基
板上に形成した半導体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device in which active elements such as bipolar transistors and MOS transistors are formed on the same substrate.
バイポーラトランジスタとＭＯＳトランジスタが混在す
る回路において、バイポーラトランジスタを駆動する回
路として第１図の如き回路がよく知られている。このよ
うな回路を同一基板上に作成しようとするとき、特にベ
ース・エミッタ間のバイアス調整のための抵抗Ｒ８は、
従来第２図、第３図の如く、トランジスタと電気的に分
離された領域に設けた拡散抵抗を用いていた。しかし、
この構造では、拡散抵抗の領域が大きく装置の高集積化
の妨げになっていた。In a circuit in which bipolar transistors and MOS transistors coexist, a circuit as shown in FIG. 1 is well known as a circuit for driving a bipolar transistor. When trying to create such a circuit on the same substrate, the resistor R8 for bias adjustment between the base and emitter is especially important.
Conventionally, as shown in FIGS. 2 and 3, a diffused resistor was used which was provided in a region electrically isolated from the transistor. but,
In this structure, the area of the diffused resistance is large, which hinders high integration of the device.
ここで１はＭＯＳ）ランジスタ、２はＮＰＮ）ランジス
タ、３はバイアス用抵抗、４はベース拡散領域、５はエ
ミッタ拡散領域、６はコレクタ拡散領域、７はＡｔ電極
、８は絶縁分離領域、９はＰ基板、１０はＮ０埋込み層
、１１はＮウェル領域、１４はＮ９コレクタ領域、１５
はＰ＋拡散領域、１７はＬＯＣＯ８酸化膜、１８はＰＳ
Ｇ膜である。Here, 1 is a MOS) transistor, 2 is an NPN) transistor, 3 is a bias resistor, 4 is a base diffusion region, 5 is an emitter diffusion region, 6 is a collector diffusion region, 7 is an At electrode, 8 is an insulation isolation region, 9 is a P substrate, 10 is an N0 buried layer, 11 is an N well region, 14 is an N9 collector region, 15
is P+ diffusion region, 17 is LOCO8 oxide film, 18 is PS
It is a G film.
本発明の目的は、バイポーラトランジスタを同一基板上
に作成する半導体集積回路装置で、前記問題点を解消し
回路の高集積化及び高速化を実現する半導体集積回路装
置を提供するにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device in which bipolar transistors are formed on the same substrate, which solves the above-mentioned problems and achieves higher circuit integration and higher speed.
本発明の半導体集積回路装置の特徴は、バイポーラトラ
ンジスタとＭＯＳ）う／ジスタを同一基板上に形成する
半導体集積回路装置において、基板表面に形成した、高
抵抗領域と低抵抗領域とを有する連続した多結晶及び／
または非晶質シリコン層により、高抵抗領域でバイポー
ラトランジスタのエミッタ・ベース間のバイアス抵抗、
低抵抗領域でバイポーラトランジスタのエミッタ領域を
形成したことを特徴とする半導体集積回路装置にある。A feature of the semiconductor integrated circuit device of the present invention is that, in a semiconductor integrated circuit device in which a bipolar transistor and a MOS transistor are formed on the same substrate, a continuous Polycrystalline and/or
Or, by using an amorphous silicon layer, the bias resistance between the emitter and base of a bipolar transistor in the high resistance region,
A semiconductor integrated circuit device is characterized in that an emitter region of a bipolar transistor is formed in a low resistance region.
以下本発明に係る半導体集積回路装置を一実施例により
説明する。 □
本発明においては、第４図（ａ）に示す如く、先ず例え
ばＰ型基板９上にＮ型高濃度領域１０を形成した上にＮ
型エピタキシャル層を形成し、さらにＮ型埋込層１０上
にはＮウェル１１を形成する。A semiconductor integrated circuit device according to the present invention will be explained below using one embodiment. □ In the present invention, as shown in FIG. 4(a), first, for example, an N-type high concentration region 10 is formed on a P-type substrate 9, and then
A type epitaxial layer is formed, and an N well 11 is further formed on the N type buried layer 10.
その後、ＬＯＣＯ８（ｌｏｃａｌ ｏｘｉｄｉｚａｔｉ
ｏｎ ｏｆｓｉｌｉｃｏｎ）酸化膜１７により、各素子
領域を分離した後ＭＯ８）ランジスタのゲート２２及び
Ｐ型ベース拡散層４、Ｎ０コレクタ拡散層１４、エミツ
タ窓２３を形成する。After that, LOCO8 (local oxidizati
After separating each element region with an on-of-silicon oxide film 17, MO8) the gate 22 of the transistor, the P type base diffusion layer 4, the N0 collector diffusion layer 14, and the emitter window 23 are formed.
次に第４図（ｂ）に示す如く、ポリシリコン層２５を基
板全面に２５００人被着１、その後Ｎ型不純物であるひ
素を８０ＫｅＶのエネルギーで５Ｘ１０”ｃｒｒＩ−”
イオン打込み２４する。Next, as shown in FIG. 4(b), a polysilicon layer 25 is deposited on the entire surface of the substrate for 2,500 times, and then arsenic, which is an N-type impurity, is added at 5X10"crrI-" with an energy of 80KeV.
Perform ion implantation 24.
次に第４図（ｅ）に示す如く、ポリシリコン２５の一部
をフォトレジスト２６でマスクして他の領域にひ素を８
０ＫｅＶのエネルギーで１×１０１６ｃｒｎ−２イオン
打込み２４する。Next, as shown in FIG. 4(e), a part of the polysilicon 25 is masked with a photoresist 26, and arsenic is applied to other areas.
A 1×10 16 crn−2 ion implantation 24 is performed at an energy of 0 KeV.
次に第４図（ｄ）に示す如く、フォトレジスト２６を除
去後、１０００ｔｌｌ’、 ３０分熱処理してエミッタ
拡散領域５を形成し、さらにフォトリソグラフィー技術
とプラズマエツチング技術により第４図（ｄ）の如くエ
ミッタ領域５上と連続する一部のポリシリコン２５を除
いて、ポリシリコンをエッチンク除去する。Next, as shown in FIG. 4(d), after removing the photoresist 26, heat treatment is performed for 1000 tll' for 30 minutes to form the emitter diffusion region 5, and then photolithography and plasma etching techniques are used to form the emitter diffusion region 5 as shown in FIG. 4(d). The polysilicon is etched away except for a portion of the polysilicon 25 that is continuous with the emitter region 5 as shown in FIG.
次に第４図（ｅ）に示す如＜ＭＯＳ）ランジスタのソー
スとドレインとして働らく、Ｐ９拡散領域１５をひ素の
イオン打込みによりセルアラインで形成した後表面にＰ
ＳＧ膜１８（６０００Ａ）を形成する。Next, as shown in FIG. 4(e), P9 diffusion regions 15 are formed in cell alignment by arsenic ion implantation, which serve as the source and drain of the transistor (MOS).
SG film 18 (6000A) is formed.
次に第４図（ｆ）に示す如く、電極のコンタクト用の窓
あけをフォトリソグラフィー技術を用いて行なった後Ａ
ｔ電極を形成する。Next, as shown in FIG. 4(f), after opening a window for the electrode contact using photolithography technology,
Form a t-electrode.
第５図は、前記の工程により形成されたバイポーラトラ
ンジスタと抵抗を含む素子の平面構造を示す図である。FIG. 5 is a diagram showing a planar structure of an element including a bipolar transistor and a resistor formed by the above steps.
エミッタ領域５上から、絶縁分離領域上を通りベースコ
ンタクト領域２１近くまでポリシリコン層１９．２０が
形成されている。さらに、このポリシリコン層１９．２
０は、低抵抗（３０Ω／Ｄ）の領域１９と高抵抗（１０
にΩ／口）の領域２０にわかれていて、ベースコンタク
ト領域２１と低抵抗ポリシリコン１９はＡｔ電極で接続
されている。Polysilicon layers 19 and 20 are formed from above emitter region 5 to near base contact region 21 passing over the insulation isolation region. Furthermore, this polysilicon layer 19.2
0 is a region of low resistance (30Ω/D) and a region of high resistance (10
The base contact region 21 and the low resistance polysilicon 19 are connected by an At electrode.
このような平面構造にすることにより拡散抵抗領域（第
２図４）を用いることなく小さい面積の中に素子を形成
でき、かつ低抵抗ポリシリコン領域１９からエミッタ拡
散することにより浅いエミッタが容易に形成でき第１図
の″ような回路の高集積化、高速化を達成できる。さら
にコンタクト窓の数が大幅に減ることにより、素子歩留
りも良くなる。By adopting such a planar structure, an element can be formed in a small area without using a diffused resistance region (Fig. 2, 4), and a shallow emitter can be easily formed by diffusing the emitter from the low resistance polysilicon region 19. As a result, it is possible to achieve high integration and high speed circuits as shown in FIG.
ポリシリコン膜２５を高抵抗領域１９と低抵抗領域２０
にわける理由は、以下の通り。The polysilicon film 25 is divided into a high resistance region 19 and a low resistance region 20.
The reasons for this are as follows.
まず、本実施例では、ポリシリコン膜２５はバイポーラ
Ｔ、のエミッタ領域の形成と、同じバイポーラＴｒのエ
ミッタ・ベース間のバイアス抵抗の形成に用いられる。First, in this embodiment, the polysilicon film 25 is used to form the emitter region of the bipolar T and to form the bias resistance between the emitter and base of the same bipolar Tr.
ここで、トランジスタのエミッタ注入効率を高くするた
め、エミッタの不純物濃度は、高くする必要がある。そ
のため、エミッタ形成領域上のポリシリコンには、高ド
ーズ量のイオン打込みをし、ポリシリコン自体を低抵抗
化し、シリコン内の不純物濃度を高くする。一方、エミ
ッタ・ベース間のバイアス抵抗は数にΩ〜斂十にΩの比
較的高い抵抗が必要である。したがってエミッタ形成の
ための低抵抗化したポリシリコンでは、層抵抗値で２０
〜３０Ω／口となり、パイアス抵抗として使うためには
、広い面積が必要となり実用的でない。そこで、バイア
ス抵抗として用いる領域のポリシリコン膜へのイオン打
込みを少なくすることにより、高抵抗領域２０を形成す
る。Here, in order to increase the emitter injection efficiency of the transistor, it is necessary to increase the impurity concentration of the emitter. Therefore, a high dose of ions is implanted into the polysilicon on the emitter formation region to lower the resistance of the polysilicon itself and increase the impurity concentration in the silicon. On the other hand, the bias resistance between the emitter and the base requires a relatively high resistance of several ohms to several ohms. Therefore, with low-resistance polysilicon for emitter formation, the layer resistance value is 20
~30Ω/port, which is impractical as it requires a large area to be used as a bias resistor. Therefore, the high resistance region 20 is formed by reducing the amount of ion implantation into the polysilicon film in the region used as the bias resistor.
このようにシリコン表面のポリシリコン膜に高抵抗領域
１９と低抵抗領域２０を作ることにより、バイポーラト
ランジスタのエミッタとエミッタ・ベース間のバイアス
抵抗を同時にかつ小面積テ形成できる。By forming the high resistance region 19 and the low resistance region 20 in the polysilicon film on the silicon surface in this manner, the emitter of the bipolar transistor and the bias resistance between the emitter and base can be formed simultaneously and in a small area.
以上述べた様に本発明によれば高集積化及び高速化を実
現できる半導体集積回路装置を得ることができる。As described above, according to the present invention, it is possible to obtain a semiconductor integrated circuit device that can realize high integration and high speed.
第１図は、本発明を適用する半導体集積回路、第２図は
、従来法による平面構造を示す図、第３図は、従来法に
よる素子の縦断面図、第４図は、本発明の一実施例を示
す図、第５図は、本発明による平面構造図である。
１・・・ＭＯＳ）ランジスタ、２・・・ＮＰＮバイポー
ラトランジスタ、１９・・・低抵抗ポリシリコン、２０
第 ４ 図
第１頁の続き
［相］発 明 者 平 −尾 充 日立市幸町３所内
［相］発 明 者 亀 井 達 弥 日立市幸町３所内FIG. 1 shows a semiconductor integrated circuit to which the present invention is applied, FIG. 2 shows a planar structure according to a conventional method, FIG. 3 is a vertical cross-sectional view of a device according to a conventional method, and FIG. FIG. 5, which shows one embodiment, is a plan view of the structure according to the present invention. 1...MOS) transistor, 2...NPN bipolar transistor, 19...low resistance polysilicon, 20
Figure 4 Continuation of page 1 [Phase] Inventor: Mitsuru Hira-o Inside Saiwai-cho 3, Hitachi City [Phase] Inventor: Tatsuya Kamei Inside Saiwai-cho 3, Hitachi City
Claims (1)
集積回路装置において、基板表面に形成した、高抵抗領
域と低抵抗領域とを有する連続した多結晶及び／または
非晶質シリコン層により、高抵抗領域でバイポーラトラ
ンジスタのエミッタ・ベース間のバイアス抵抗、低抵抗
領域でバイポーラトランジスタのエミッタ領域を形成し
たことを特徴とする半導体集積回路装置。1. In a semiconductor integrated circuit device in which a bipolar transistor is formed on a substrate, a continuous polycrystalline and/or amorphous silicon layer having a high-resistance region and a low-resistance region is formed on the surface of the substrate. A semiconductor integrated circuit device characterized in that the emitter region of the bipolar transistor is formed in a bias resistance between the emitter and base of the bipolar transistor, and a low resistance region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58204663A JPS6097669A (en) | 1983-11-02 | 1983-11-02 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58204663A JPS6097669A (en) | 1983-11-02 | 1983-11-02 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6097669A true JPS6097669A (en) | 1985-05-31 |
Family
ID=16494218
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58204663A Pending JPS6097669A (en) | 1983-11-02 | 1983-11-02 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6097669A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6459856A (en) * | 1987-08-31 | 1989-03-07 | Nec Corp | Manufacture of integrated circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5338992A (en) * | 1976-09-22 | 1978-04-10 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS5519871A (en) * | 1978-07-28 | 1980-02-12 | Mitsubishi Electric Corp | Transistor |
| JPS55156360A (en) * | 1979-05-21 | 1980-12-05 | Exxon Research Engineering Co | Integrated high speed semiconductor power switching device |
-
1983
- 1983-11-02 JP JP58204663A patent/JPS6097669A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5338992A (en) * | 1976-09-22 | 1978-04-10 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS5519871A (en) * | 1978-07-28 | 1980-02-12 | Mitsubishi Electric Corp | Transistor |
| JPS55156360A (en) * | 1979-05-21 | 1980-12-05 | Exxon Research Engineering Co | Integrated high speed semiconductor power switching device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6459856A (en) * | 1987-08-31 | 1989-03-07 | Nec Corp | Manufacture of integrated circuit |
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