JPS6096924A - Frequency division circuit - Google Patents

Abstract

PURPOSE:To realize a high speed counter having a frequency dividing ratio in the unit of 0.5 with simple circuit constitution by adopting relative circuit constitution for two 1/2 frequency division circuits mutually so as to eliminate the need for forming a clock pulse of inverted phase. CONSTITUTION:Since the 1/2 frequency division circuits 1, 2 are formed as mutually relative circuit constitution and a waveform shifted by 1/4 period is obtained at the output. A frequency frequency-dividing an input clock pulse phi into 1/2 is obtained at an output of a 2-input NAND circuit 14 and a frequency frequency-dividing the pulse into 1/4 is obtained at an output of a 1/2 frequency-division circuit 3. To attain the frequency division of 0.5 unit, the phase of the circuits 1, 2 has only to be changed at each output of one pulse from a 1/2 frequency circuit 4 of the final stage. An output of a 1/2 frequency division circuit 5 is used as a selection control signal which of phase of the circuits 1 and 2 and when it is to be changed. When the circuit 3 is driven by an output of the circuit 1, the phase of the circuit 1 is shifted by one period's share of the pulse phi and the circuit 3 is driven by the circuit 2. The similar operation as above is performed also for the circuit 2.

Description

【発明の詳細な説明】 本発明は分周回路、特に高速かつ０．５単位の分周比で
分周可能な分周回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency divider circuit, and particularly to a frequency divider circuit capable of dividing a frequency at high speed and with a frequency division ratio of 0.5 units.

従来よシブαグラムデータに従って任意の分局比を得る
ことの出来るプログラマブルカウンタがＰＬＬ（位相同
期回路）方式周波数シンセサイザー等の高速動作を要求
される用途に使用されている。一般にプログラマブルカ
ウンタは単に固定分周比をもつカウンタに比べ分周比を
カウンタにプリセットする機能とカウンタの内容が所定
値になったことを判定する機能が追加される分だけ回路
が複雑になり最高動作周波数は低下する。一方０．５単
位の分周比をもつプログラマブルカウンタは前述の周波
数シンセサイザー等の用途でＣＮＲ（キャリア　ノイズ
　レシオ）を上げる手段として有効であることが知られ
ており又１／２の固定分周回路の出力に０．５単位の分
周比をもったグログ２マプルカウンタを接続すれば１単
位の分局比をもつ高速なプログラマブルカウンタとして
使用することも出来その応用範囲は広い。Conventionally, programmable counters that can obtain arbitrary division ratios according to sib alpha-gram data have been used in applications that require high-speed operation, such as PLL (phase locked loop) type frequency synthesizers. In general, programmable counters have a more complex circuit than counters with a fixed frequency division ratio due to the addition of a function to preset the frequency division ratio into the counter and a function to determine when the contents of the counter have reached a predetermined value. Operating frequency decreases. On the other hand, a programmable counter with a frequency division ratio of 0.5 units is known to be effective as a means of increasing the CNR (carrier noise ratio) in applications such as the aforementioned frequency synthesizer, and a fixed frequency division circuit of 1/2 is known to be effective as a means of increasing the CNR (carrier noise ratio). If a Glog 2 maple counter with a division ratio of 0.5 units is connected to the output of the counter, it can be used as a high-speed programmable counter with a division ratio of 1 unit, and its range of applications is wide.

これを実現する為にはカウンタはその出力信号が出る度
に入力クロックパルスの位相を反転させなければならな
い。つｔｂ人カクロツクパルスグの位相切り換えをカウ
ンタ段よシ作られるフィードバック信号によシ行なわな
くてはならない為に最高動作周波数は極端に低下してし
まう。To achieve this, the counter must invert the phase of the input clock pulse each time its output signal is output. Since the phase of the clock pulse signal must be switched by the feedback signal generated by the counter stage, the maximum operating frequency is extremely reduced.

本発明の目的は０．５単位の分周比をもつグログラマブ
ルカウンタの高速化を可能にした回路方式を提供するこ
とにおる。An object of the present invention is to provide a circuit system that enables a high-speed programmable counter having a frequency division ratio of 0.5 units.

本発明の分周回路では少なくとも人力クロックパルスに
よシ駆動され互いに９０°位相のずれた出力を得るよう
にした第１．第２の１／２分周回路と前記第１．第２の
１７２分周回路の出力のアンド（オア）信号によ）駆動
されるカウンタと前記カウンタの計数値と外部制御入力
に基づく信号により状態が制御される記憶回路より成シ
前記記憶回路により選択される前記第１．第２の１７２
分周回路の一方の出力と該出力で同期された前記外部制
御入力と前記カウンタの計数値に基づく信号により他方
の１／２分周回路の出力位相ヲ１８０゜ずらすようにし
て構成したことを特徴とする。In the frequency divider circuit of the present invention, the first frequency divider circuit is driven by at least a manual clock pulse and outputs are shifted in phase by 90 degrees from each other. a second 1/2 frequency divider circuit and the first . A counter driven by an AND (OR) signal of the output of a second 172 frequency divider circuit, and a storage circuit whose state is controlled by a signal based on the count value of the counter and an external control input. The first selected item. second 172
The output phase of the other 1/2 frequency divider circuit is shifted by 180 degrees by a signal based on one output of the frequency divider circuit, the external control input synchronized with the output, and the count value of the counter. Features.

以下本発明による分周回路を詳細に説明する。The frequency divider circuit according to the present invention will be explained in detail below.

第１図に本発明の第１の実施例、第２図にその動作を説
明する為のタイムチャートを示す。図中１〜５は１７２
分周回路、　１４〜１８はＮＡＮＤ回路、１９〜２０は
トランスファーゲート、２０〜２１はＮＯＲ回路、２３
〜２５はインノく一夕を表わす。本実施例は０ＭＯ８（
相補型ｙｉｏｓ　Ｆ’ＥＴ）構成である。１／２分周回
路１，２は特に−相のクロックパルスで動作するダイナ
ミック型ヲ使用して高速化をはかっている。本実施例の
大きな特徴は１／２分周回路１と２全互いに相対な回回
路構成としたことであシこの為逆相のクロックパルスを
作る必要がなく高速動作に壱利になっている。１／２分
周回路１と２の位相シフト制御は共に最終段のインバー
タにｎチャンネル型ＭＯ８ＦＥＴを直列に挿入しｐチャ
ンネルｆｆ１Ｍ０８　ＦＥＴを並列にしたＮＡＮＤ回路
構成としでいる。これはｐウェル型の相補ＩＪｌｌＮｉ
Ｏ８ＦＦ；Ｔではｎチャンネル型ＭＯ８ＦＥＴの万がｐ
チャンネル型ＩＶ１０８　ＦＥＴよ勺！１１−ｍが大き
い為であル位相シフト制御回路はＮＯＲ構成、あるいは
片チヤンネル構成としても差し支えない。第１図の実施
例は分局比８と８，５をもつ回路構成であるが説明を簡
単化する為に外部制御入力端子３０４−”ｆＩ”　レベ
ルに固定しであるものとして説明する。本発明による分
周回路は外部制御人力３０をＨ″　レベルにすれば１／
８５分周をし１Ｌ”レベルにすれば１７８分周を行なう
。FIG. 1 shows a first embodiment of the present invention, and FIG. 2 shows a time chart for explaining its operation. 1 to 5 in the diagram are 172
Frequency dividing circuit, 14 to 18 are NAND circuits, 19 to 20 are transfer gates, 20 to 21 are NOR circuits, 23
~25 represents Inno Ku Ichiya. In this example, 0MO8(
This is a complementary yios F'ET) configuration. The 1/2 frequency divider circuits 1 and 2 are of a dynamic type that operates with negative phase clock pulses in order to increase the speed. The major feature of this embodiment is that the 1/2 frequency divider circuits 1 and 2 are constructed in a circuit configuration that is relative to each other.Therefore, there is no need to generate clock pulses of opposite phase, which is advantageous for high-speed operation. . The phase shift control of the 1/2 frequency divider circuits 1 and 2 is performed using a NAND circuit configuration in which an n-channel MO8FET is inserted in series in the final stage inverter and a p-channel ff1M08 FET is connected in parallel. This is a p-well type complementary IJllNi
O8FF; T is n-channel type MO8FET.
Channel type IV108 FET! Since 11-m is large, the phase shift control circuit may have a NOR configuration or a single channel configuration. The embodiment shown in FIG. 1 has a circuit configuration with a division ratio of 8 and 8,5, but for the sake of simplicity, the external control input terminal 304 will be described as being fixed at the "fI" level. The frequency dividing circuit according to the present invention can be set to 1/
If the frequency is divided by 85 and set to 1L'' level, the frequency is divided by 178.

以下第２図のタイムチャートを参照しながら動作を説明
する。The operation will be explained below with reference to the time chart shown in FIG.

１７２分周回路１と２は互いに相対な回路構成になって
いる為にその出力には丁度１／４周期（９０’）ずれた
波形が得られる。２人力ＮＡＮＩ）回路１４の出力には
入力クロックパルスｇを１／２分周した周波数が得られ
１／２分周回路３の出力には１／４分周した周波斂が得
られる。１７２分周且町３は２人力ＮＡＮＤ回路１４の
立ち上がシェッジで状態変化するがこの立ち上がルエッ
ジは１７２分周回路１と２の位相関係によって決ｔ９第
２図に示すタイムチャートの最初の部分では１／２分周
回路１の出力で１／２分周回路３は駆動されている。Since the 172 frequency divider circuits 1 and 2 have relative circuit configurations, their outputs have waveforms shifted by exactly 1/4 period (90'). The output of the 2-man power NANI) circuit 14 obtains a frequency obtained by dividing the input clock pulse g by 1/2, and the output of the 1/2 frequency divider circuit 3 obtains a frequency obtained by dividing the input clock pulse g by 1/4. The state of the 172 frequency dividing circuit 3 changes with the rising edge of the two-man power NAND circuit 14, but this rising edge is determined by the phase relationship between the 172 frequency dividing circuits 1 and 2. In the part shown in FIG. 3, the 1/2 frequency divider circuit 3 is driven by the output of the 1/2 frequency divider circuit 1.

従って０．５単位の分周を行なう為には最終段の１／２
分周回路４から１パルス出る度に１／２分周回路１と２
の位相関係を変えてやれば良いがどちらの１／２分周回
路の位相をいつ変えてやらなくてはならないかという選
択制御とタイミング制御を行なう回路が必要となる。本
発明の分周回路では選択制御信号としては１７２分周回
路５の出力を又タイミング制御信号として１７２分周回
路５の出力で選択された１７２分周回路１．２の一方の
出力を使用している。１／２分周回路５は最終段の１／
２分周回路４から１パルス出る度に状態が反転するがこ
の２つの状態それぞれについて１７２分周回路１と２の
位相が制御される様子を以下に順を追って説明する。Therefore, in order to divide the frequency by 0.5 units, 1/2 of the final stage is used.
Every time one pulse is output from frequency divider circuit 4, 1/2 frequency divider circuits 1 and 2
It is possible to do this by changing the phase relationship between the 1/2 frequency dividers, but a circuit is required to perform selection control and timing control to determine when the phase of the 1/2 frequency divider circuit should be changed. In the frequency divider circuit of the present invention, the output of the 172 frequency divider 5 is used as the selection control signal, and one output of the 172 frequency divider 1.2 selected by the output of the 172 frequency divider 5 is used as the timing control signal. ing. The 1/2 frequency divider circuit 5 is the final stage 1/2 frequency divider circuit 5.
Each time a pulse is output from the divide-by-2 circuit 4, the state is reversed, and the manner in which the phases of the divide-by-172 circuits 1 and 2 are controlled for each of these two states will be explained in order below.

１／２分周回路５の出力が”ｌ（”レベルになると２人
力ＮＡＮＤ回路１４の次のクロックで１／２分周回路３
はｌ″Ｈ″Ｈ″レベル２人力ＮＯＲ回路２２が′Ｈ”レ
ベルとなる。２人力ＮＯＲ回路２２と２１は１７２分周
回路５でどちらか一方が選択されるので２人力ＮＯＲ回
路２１は”Ｌ″しベル状態が維持される。２人力ＮＯＲ
回路２２よシ得られる信号は１７２分周回路１の出力で
変化した信号であシ１／４周期ずれた１／２分周回路２
の出力よシ１パルス取シ出す為の信号としては適当でな
くトランスファーゲート２０はこの為に必要であシ１／
２分周回路２で同期をとり直す役目をしている。２人力
ＮＡＮＤ回路１８よシ１／２分周回路２の１パルスが出
力され１／２分周回路１印加されると１／２分周回路１
は位相が一周期シフトする。When the output of the 1/2 frequency divider circuit 5 reaches the "l(" level), the 1/2 frequency divider circuit 3 is activated at the next clock of the two-man power NAND circuit 14.
The two-manufactured NOR circuit 22 becomes ``H'' level. Since one of the two-man powered NOR circuits 22 and 21 is selected by the 172 frequency divider circuit 5, the two-man powered NOR circuit 21 goes "L" and maintains the bell state. 2 person NOR
The signal obtained from the circuit 22 is a signal changed by the output of the 172 frequency divider circuit 1.
It is not suitable as a signal for extracting one pulse from the output of
It plays the role of resynchronizing with the divide-by-2 circuit 2. When the two-man power NAND circuit 18 outputs one pulse of the 1/2 frequency divider circuit 2 and the 1/2 frequency divider circuit 1 is applied, the 1/2 frequency divider circuit 1
The phase shifts by one cycle.

このように１／２分周回路３が１７２分周回路１の出力
によシ駆動されたのであれば１／２分周回路１の位相は
入カクロックバルスグの一周期分シフトされその後１７
２分周回路３は１／２分周回路２によシ駆動される。こ
れと同様な動作は１／２分周回路２についても行なわれ
る。又初期状態に於いて１／２分周回路３が１７２分周
回路１の出力によ＃）Ｗ！Ａ動されたような位相関係の
ときには２人力ＮＡＮＤ回路１７よル１／２分周回路２
に位相制御信号が印加されても位相のシフトは生じずこ
の結果１／２分周回路１と２がどのような位相関係にあ
っても一度位相制御信号１７、又は１８が発生された後
は第２図に示した位相関係に落ちつくことになる。In this way, if the 1/2 frequency divider circuit 3 is driven by the output of the 172 frequency divider circuit 1, the phase of the 1/2 frequency divider circuit 1 is shifted by one period of the input clock pulse, and then 172
The divide-by-2 circuit 3 is driven by the divide-by-half circuit 2. A similar operation is performed for the 1/2 frequency divider circuit 2 as well. Also, in the initial state, the 1/2 frequency divider circuit 3 uses the output of the 172 frequency divider circuit 1 #) W! When the phase relationship is such that A is shifted, the two-man NAND circuit 17 is connected to the 1/2 frequency divider circuit 2.
Even if a phase control signal is applied to , no phase shift occurs.As a result, no matter what phase relationship the 1/2 frequency divider circuits 1 and 2 have, once the phase control signal 17 or 18 is generated, The phase relationship shown in FIG. 2 will be settled.

以上詳述した様に本発明によれば簡単乃：構成で０．５
単位の分局比をもつ高速なカウンタを実現出来又２モデ
ュラスグリスケージとしても使用することが出来る等真
に有用である。As described in detail above, according to the present invention, the simple configuration is 0.5.
It is truly useful, as it can realize a high-speed counter with a division ratio of one unit, and can also be used as a two-modulus grease cage.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の実施例を示す図％第２図はその動作を
説明する為のタイムチャー１示す図である。図中１〜５
は１７２分周回路、　１４〜１８はＮＡＮＤ回路、１９
〜２０はトランスファーゲート、２０〜２１はＮＯＲ回
路、２３〜２５はインバータを表わす。FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing a time chart 1 for explaining its operation. 1 to 5 in the diagram
is a 172 frequency divider circuit, 14 to 18 are NAND circuits, 19
-20 represent transfer gates, 20-21 NOR circuits, and 23-25 inverters.

Claims (1)

【特許請求の範囲】[Claims] 入力クロックパルスによシ駆動され互いに９０゜位相の
ずれた出力を得るようにした第１．第２の１／２分周回
路と、前記第１．第２のｌ／２分周回路の出力信号によ
シ駆動されるカウンタと、前記カウンタの計数値と外部
制御入力に基づく信号によシ状態が制御される記憶回路
よ構成シ前記記憶回路によ、！７選択されるｆｌＳｊ記
第１．第２の１／２　分周回路の一方の出力と該出力で
同期された前記外部制御入力と前記カウンタの計数値に
基づく信号によ勺他方のｌ／２分周回路の出力位相を１
８００ずらすようにしだ分周回路。The first one is driven by an input clock pulse and has outputs that are 90° out of phase with each other. a second 1/2 frequency divider circuit; A counter driven by the output signal of the second l/2 frequency divider circuit, and a memory circuit whose state is controlled by a signal based on the count value of the counter and an external control input. Yo,! 7 Selected flSj 1st. The output phase of the other 1/2 frequency divider is changed to 1 by a signal based on one output of the second 1/2 frequency divider, the external control input synchronized with the second output, and the count value of the counter.
A frequency divider circuit shifted by 800.