JPS6094780A - Constant-voltage diode - Google Patents

Constant-voltage diode

Info

Publication number
JPS6094780A
JPS6094780A JP58200827A JP20082783A JPS6094780A JP S6094780 A JPS6094780 A JP S6094780A JP 58200827 A JP58200827 A JP 58200827A JP 20082783 A JP20082783 A JP 20082783A JP S6094780 A JPS6094780 A JP S6094780A
Authority
JP
Japan
Prior art keywords
layer
main surface
junction
substrate
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58200827A
Other languages
Japanese (ja)
Inventor
Hirotoshi Toida
裕俊 戸井田
Toshiyuki Hidaka
日高 俊幸
Hisashi Sakamoto
久 坂本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58200827A priority Critical patent/JPS6094780A/en
Publication of JPS6094780A publication Critical patent/JPS6094780A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To eliminate the influence to the constant voltage characteristic even if a semiconductor substrate is damaged or notched by forming the substrate of a constant-voltage diode in a negative bevel structure. CONSTITUTION:An Si substrate 11 has three layers of a p type layer 11a, an n type layer 11b and an n<+> type layer 11c, p type impurity and n type impurity are diffused from the main surface side to the thin n type Si plate to form a p-n-n<+> type layer structure, and the region to which the impurity is not diffused becomes the layer 11b. The area of the main surface of the layer 11a side becomes smaller than that of the main surface of the layer 11b side, and the side periphery of te substrate 11 is inclined to the main surface. A p-n junction J formed of the layers 11a and 11b is parallel to the main surface, the exposed end of the junction J is acute at the layer 11a side in the angle formed with the side periphery, and the layer 11a has higher impurity density than the layer 11b. Accordingly, the Si substrate 11 has negative bevel structure. The portion that damage or notch feasibly occurs during the manufacturing steps of the substrate 11 is the main surface peripheral edge of the layer 11c side, and even if the damage or notch occurs, it is separated from the junction, thereby hardly causing the decrease in the characteristics.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は定電圧ダイオードに係り、特に、pn接合の端
部構造に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a constant voltage diode, and in particular to an end structure of a pn junction.

〔発明の背景〕[Background of the invention]

pn接合の端部構造には正ベベルと負ベベルが(1) ある。正ベベルとは半導体基体をその一対の主表面だわ
たって切断した場合の縦断面でみた時、pn接合の端部
が見出している半導体の表面と該端部のなす角が不純物
濃度の高い半導体層側で鈍角になっているものを云い、
負ベベルとは綾角が不純物濃度の高い半導体層側で鋭角
になっているものを云う。pn接合の端部は主表面が一
対の主表面間の側面に露出される。概略的に云って主表
面に露出したものをプレーナ構造、側面に露出したもの
をメサ構造と呼ぶ。一方、半導体基体はp−n−nゝあ
るいはp+ p nの3層構造とされる。
The end structure of a pn junction has a positive bevel and a negative bevel (1). A normal bevel is a semiconductor substrate with a high impurity concentration, where the angle formed by the edge of the semiconductor and the surface of the semiconductor where the edge of the pn junction is found, when viewed in a longitudinal section when the semiconductor substrate is cut across its pair of main surfaces. It refers to something that has an obtuse angle on the layer side.
Negative bevel means that the winding angle becomes acute on the side of the semiconductor layer where the impurity concentration is high. At the end of the pn junction, the main surface is exposed on the side surface between the pair of main surfaces. Roughly speaking, the structure exposed on the main surface is called a planar structure, and the structure exposed on the side surfaces is called a mesa structure. On the other hand, the semiconductor substrate has a pn-n or p+pn three-layer structure.

従来のメサ構造の定電圧ダイオードはpn接合面積を大
きくして逆方向サージ耐量を高め、またpn接合の両側
にできる障壁の端部での電界を緩和するためにpn接合
が主表面と平行な正ベベルにされていた。
Conventional mesa structure voltage regulator diodes have a large pn junction area to increase reverse surge resistance, and also have a pn junction parallel to the main surface to alleviate the electric field at the ends of the barriers formed on both sides of the pn junction. It was set to a normal bevel.

従って、pn接合は大面積となる主表面に近い位置に存
在しており、大面積となる主表面から側面にかけこの一
部で製造工程中に破損や欠落を生(乃 すると、その定電圧特性に大きな影響を与えていた。
Therefore, the p-n junction is located close to the main surface, which has a large area. had a great influence on.

近年、pn接合端部露出面に設ける表面安定化剤として
、洩れ電流を小さくすることが可能なポリイミド系樹脂
が利用されつつあるが、粘性は低く、厚く付着させられ
ない問題がある。特に正ベベル構造になっていると、そ
のような表面安定化剤は酵〈なり、電気力線が洩れて高
耐圧が得られないだけでなく、耐湿性の点でも問題であ
った。
In recent years, polyimide-based resins that can reduce leakage current have been used as surface stabilizers provided on the exposed surfaces of pn junction ends, but there is a problem in that they have low viscosity and cannot be applied thickly. In particular, in the case of a positive bevel structure, such a surface stabilizer becomes fermented, causing leakage of electric lines of force and not only making it impossible to obtain a high withstand voltage, but also causing problems in terms of moisture resistance.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、半導体基体に破損や欠落を生じても、
定電圧特性の受ける影響のない定電圧ダイオードを提供
するにある。
The purpose of the present invention is to prevent damage or chipping of the semiconductor substrate.
The object of the present invention is to provide a constant voltage diode whose constant voltage characteristics are not affected.

〔発明の概要〕[Summary of the invention]

本発明の特徴とするところは、定電圧ダイオードの半導
体基体を負ベベル構造としたことにある。
A feature of the present invention is that the semiconductor substrate of the constant voltage diode has a negative bevel structure.

〔発明の実施例〕 以下、実施例に基づき本発明を説明する。[Embodiments of the invention] The present invention will be explained below based on Examples.

第1図において、10は本発明になる定電圧ダイオード
である。シリコン基体11はp層11a1n層11b、
n+層11Cの3層からなり、比抵抗が0.01Ωm程
度の大面積n型シリコン薄板にp型不純物、n型不純物
を各主表面(1111から拡散してp−n−n”3層構
造としてから、サンドブラスト等の公知手段によりペレ
タイズしてから、表面に残る加工歪をエツチング除去し
て得たものである。尚、不純物が拡散されなかった領域
が4層11bになっている。ペレタイズ前に薄板の両生
表面にニッケル層を鍍金等の技術により設けておく。1
2a、12bはペレタイズによってシリコン基体11の
両生表面に残ったニッケル層である。
In FIG. 1, 10 is a constant voltage diode according to the present invention. The silicon substrate 11 includes a p layer 11a1n layer 11b,
Consisting of three layers of n+ layer 11C, p-type impurity and n-type impurity are diffused from each main surface (1111) into a large-area n-type silicon thin plate with a specific resistance of about 0.01 Ωm to form a p-n-n" three-layer structure. It was obtained by pelletizing the pellet by a known means such as sandblasting, and then etching away the processing strain remaining on the surface.The region where impurities were not diffused is the 4 layer 11b.Before pelletizing A nickel layer is provided on the ambidextrous surface of the thin plate using techniques such as plating.1
2a and 12b are nickel layers left on the amphiboid surface of the silicon substrate 11 by pelletizing.

ペレタイズ後のシリコン基体11の両生表面は円形であ
る。この時、1層11a側の主表面の面積はn+層11
b側の主表面の面積より小さくなっており、シリコン基
体11の側周面I:j:主表面に対して傾斜している。
The amphibian surface of the silicon substrate 11 after pelletization is circular. At this time, the area of the main surface on the side of the first layer 11a is the n+ layer 11
The area is smaller than the area of the main surface on the b side, and the side peripheral surface I:j of the silicon substrate 11 is inclined with respect to the main surface.

pM’#11aとrlllbが隣接して形成しているp
nn接合は主表面と平行である。従ってpnn接合の露
出端部が側周面となす角は1層11a側で鋭角になって
bる。9層11aは4層11bより高不純物濃度である
から、シリコン基体11は負ベベル構造を持っている。
pM'#11a and rllllb are adjacent to each other.
The nn junction is parallel to the major surface. Therefore, the angle that the exposed end of the pnn junction makes with the side peripheral surface becomes an acute angle b on the first layer 11a side. Since the nine layers 11a have a higher impurity concentration than the four layers 11b, the silicon substrate 11 has a negative bevel structure.

ニッケル層12a、12bに対して半田13a。Solder 13a to nickel layers 12a, 12b.

13bを介してダブルヘッダーリード14a。Double header lead 14a via 13b.

14bが固着されている。シリコン基体11の側周面に
はリード14a、14bのシリコン基体11側の第一ヘ
ッダ部14aa、14ba間に表面安定化剤15が設け
られ、更に第二ヘッダ部14ab、14bb間にモール
ド材16が設けられている。表面安定化剤15としてポ
リイミドシリコーン樹脂、モールド材16としてエポキ
シ樹脂が一例として用いられた。
14b is fixed. A surface stabilizer 15 is provided on the side peripheral surface of the silicon substrate 11 between the first header portions 14aa and 14ba of the leads 14a and 14b on the silicon substrate 11 side, and a molding material 16 is further provided between the second header portions 14ab and 14bb. is provided. As an example, a polyimide silicone resin was used as the surface stabilizer 15, and an epoxy resin was used as the molding material 16.

シリコン基体11の製造工程中に破損や欠落を生じ易い
個所はn+層11C側の主表面周縁部分であり、破損や
欠落を生じたとしても、pnn接合と離れているために
特性低下を起し難い。
During the manufacturing process of the silicon substrate 11, damage or chipping is likely to occur at the main surface periphery on the n+ layer 11C side, and even if damage or chipping occurs, the characteristics will deteriorate because it is far away from the pnn junction. hard.

定電圧ダイオードでは、n層が比抵抗30Ω鋸程度の通
常のダイオードに較べて4層11bが高不純物濃度(低
比抵抗)があるため、逆方向に電圧が印加された場合に
pnn接合の両側の9層11a、n層11b内だできる
障壁はその幅が非常に小さくなる。ツェナー電圧が30
V以下の場合、第2図に示す様に9層11a、n層11
. bの各々の層内にできる障壁の幅は1μm以下であ
る。
In a constant voltage diode, the 4th layer 11b has a higher impurity concentration (lower resistivity) than a normal diode, where the n-layer has a resistivity of about 30Ω, so when a voltage is applied in the opposite direction, both sides of the pnn junction The width of the barrier formed within the nine layers 11a and the n layer 11b becomes extremely small. Zener voltage is 30
In the case of V or less, as shown in FIG.
.. The width of the barrier formed in each layer of b is 1 μm or less.

これを不純物濃度との関係で示すと第3図に示す様に、
ツェナー降伏を起す直前の状態で障壁は不純物傾斜が直
線状となったpn接合の両側の限られた領域に拡がるだ
けで、しかも、9層11a内とn層11b内でほぼ同じ
幅で、不純物濃度もほぼ同じとなっており、障壁内での
電界強度は9層11a、4層11bの両層内でほぼ等し
い。
When this is shown in relation to the impurity concentration, as shown in Figure 3,
Immediately before Zener breakdown occurs, the barrier only spreads to a limited area on both sides of the pn junction where the impurity slope is linear. The concentrations are also approximately the same, and the electric field strength within the barrier is approximately equal within both the 9-layer 11a and the 4-layer 11b.

従って、負ベベル構造になっているとしても、側面部分
での障壁の拡がり具合や電界強度は正ベベル構造とした
場合と大差がない。つまり、負ベベル構造になっている
としても、そのことによって、側面部分での耐圧低下の
恐れはない。このことは側面が主表面となす角度によっ
て変更しないので、ベベル角は正確に制御する必要はな
く、I産性が良い。
Therefore, even if the negative bevel structure is adopted, the spread of the barrier and the electric field strength at the side portions are not much different from those in the case of the positive bevel structure. In other words, even if it has a negative bevel structure, there is no risk of a drop in breakdown voltage at the side portions. Since this does not change depending on the angle that the side surface makes with the main surface, there is no need to accurately control the bevel angle, and productivity is good.

第1図に示す様に第一ヘッダ部14 a a。As shown in FIG. 1, the first header section 14aa.

14haをシリコン基体11と同じかそれ以上の径とし
ておくと、第一ヘッダ部14aa、14baは表面安定
化剤15の流れ止めとして働く。特に、pnn接合部部
分は表面安定化剤15は厚くなるから、粘性の低いもの
を用いた場合は、表面安定化剤15の厚さによる耐圧劣
化や耐湿性低下は生じない。
If the diameter of 14 ha is the same as or larger than that of the silicon substrate 11, the first header portions 14aa and 14ba act as a flow stopper for the surface stabilizer 15. In particular, since the surface stabilizer 15 becomes thick at the pnn junction portion, if a low-viscosity agent is used, pressure resistance deterioration and moisture resistance deterioration due to the thickness of the surface stabilizer 15 will not occur.

pnn接合上接合面積は正ベベルの場合に較べて小さく
なるが、正ベベル角を大きくとれば接合面積の縮小率は
小さく、シリコン基体11そのものを従来よりわずかに
大きくすれば、同じ逆サージ耐量を得るととができるか
ら、この点は、負ベベルであっても、問題にならない。
The junction area on the pnn junction is smaller than that in the case of a positive bevel, but if the positive bevel angle is made large, the reduction rate of the junction area is small, and if the silicon substrate 11 itself is made slightly larger than the conventional one, the same reverse surge resistance can be achieved. Since it is possible to obtain and , there is no problem in this point even if the bevel is negative.

第4図は本発明の応用例になる定電圧ダイオード20を
示している。
FIG. 4 shows a constant voltage diode 20 which is an application example of the present invention.

第4図において、シリコン基体21は1層21a。In FIG. 4, the silicon substrate 21 has one layer 21a.

9層21bX p+層21Cの3層を有している。It has three layers: 9 layers 21bX and a p+ layer 21C.

シリコン基体21はp型シリコン板を出発母材として、
n型不純物、p型不純物を各主表面から各各拡散して1
層21a、p+層21Cを形成したものである。第1図
の実施例と同様大面積シリコン薄板からペレタイズして
得喪もので、0層21a側の主表面がp+層21c側の
主表面より小さくされており、pnn接合上平坦である
ので負ベベル構造になっている。各主表面にはアルミニ
ウムろう23a、23bにより電極リード24a。
The silicon substrate 21 uses a p-type silicon plate as a starting material,
Diffuse n-type impurities and p-type impurities from each main surface.
A layer 21a and a p+ layer 21C are formed. Similar to the embodiment shown in FIG. 1, it is pelletized from a large-area silicon thin plate, and the main surface on the 0 layer 21a side is smaller than the main surface on the p+ layer 21c side, and is flat on the pnn junction, so it has a negative bevel. It has a structure. Electrode leads 24a are provided on each main surface by aluminum solders 23a and 23b.

24bが固着されている。電極リード24a。24b is fixed. Electrode lead 24a.

24bはモリブデン或はタングステンのスラグ電極24
aa、24baとこれにパーカッション溶接された銅リ
ード24ab、24bbがらなっている。シリコン基体
21はその周囲を一方の電極24aaから他方の電極2
4haにかけて設けた表面安定化機能を有するガラス2
5でモールドされている。
24b is a molybdenum or tungsten slag electrode 24
It consists of copper leads 24ab and 24bb percussion welded to aa and 24ba. The silicon substrate 21 has its periphery connected from one electrode 24aa to the other electrode 2.
Glass 2 with surface stabilization function installed over 4 ha
It is molded with 5.

シリコン基体21はn−1)−r)”3層構造であるが
逆バイアスが加えらハた時% r”接合Jの両側に拡が
る障壁は第1図のものと同様、同じ幅で同じ不純物濃度
の位置に拡がるだけであるから、負ベベルによる耐圧劣
化はないし、p” )42 I Cの主表面部に破損や
欠落を生じてもpn接合まで及ぶことはほとんどなく特
性劣下は生じない。
The silicon substrate 21 has a three-layer structure (n-1)-r), but when a reverse bias is applied, the barriers extending on both sides of the junction J have the same width and the same impurity content as in Figure 1. Since it only spreads to the concentration position, there is no breakdown voltage deterioration due to negative bevel, and even if the main surface of the p")42 IC is damaged or missing, it will hardly extend to the pn junction and no characteristic deterioration will occur. .

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば半導体基体に破損
や欠落を生じても定電圧特性に影響を受けることのない
定電圧ダイオードを得ることができる。
As explained above, according to the present invention, it is possible to obtain a constant voltage diode whose constant voltage characteristics are not affected even if the semiconductor substrate is damaged or missing.

【図面の簡単な説明】 第1図は本発明の一実施例を示す定電圧ダイオードの縦
断面図、第2図はツェナー電圧と障壁層幅の関係を示す
図、第3図は定電圧ダイオードのシリコン基体における
不純物濃度プロフィールを示す図、第4図は本発明の応
用例を示す定電圧ダイオードの縦断面図である。 11・・・シリコン基体、11a・・・p層、11b・
・・n層、l l C・・−n”層、12a、12b・
=ツケル層、13 a、13b・・・半田、14a、1
4b・・・半田、15・・・表面安定化剤、16・・・
モールド材。 代理人 弁理士 高橋明夫 第 1 図 ヅエナー電圧CV)
[Brief Description of the Drawings] Fig. 1 is a vertical cross-sectional view of a constant voltage diode showing an embodiment of the present invention, Fig. 2 is a diagram showing the relationship between Zener voltage and barrier layer width, and Fig. 3 is a diagram of a constant voltage diode. FIG. 4 is a longitudinal cross-sectional view of a constant voltage diode showing an application example of the present invention. 11...Silicon base, 11a...p layer, 11b...
・・n layer, l l C・・−n” layer, 12a, 12b・
=Tsukeru layer, 13a, 13b...Solder, 14a, 1
4b...Solder, 15...Surface stabilizer, 16...
mold material. Agent Patent Attorney Akio Takahashi (Figure 1)

Claims (1)

【特許請求の範囲】[Claims] 1、半導体基体は一対の主表面間に順次一方導電型の第
一の半導体層と不純物濃度が第一半導体層より低い他方
導電型の第二の半導体層と他方導電型で第二半導体層よ
り高不純物濃度の第三の半導体層を有し、第一、第二の
両生導体層が作るpn接合は一対の主表面と平行で両主
表面間の側面に端部が露出しており、第一の半導体層側
の主表面は第三の半導体層側の主表面より小さく、ツェ
ナー降伏直前の第一、第二の各半導体層の障壁はほぼ同
じ幅で、同じ不純物濃度の位置に拡がって込ることを特
徴とする定電圧ダイオード。
1. The semiconductor substrate has a first semiconductor layer of one conductivity type between the pair of main surfaces, a second semiconductor layer of the other conductivity type whose impurity concentration is lower than that of the first semiconductor layer, and a second semiconductor layer of the other conductivity type, which is lower in impurity concentration than the first semiconductor layer. The pn junction, which has a third semiconductor layer with a high impurity concentration and is formed by the first and second bidirectional conductor layers, is parallel to the pair of main surfaces and has an end exposed on the side surface between the two main surfaces. The main surface on the first semiconductor layer side is smaller than the main surface on the third semiconductor layer side, and the barriers of the first and second semiconductor layers just before Zener breakdown have approximately the same width and spread to positions with the same impurity concentration. A constant voltage diode characterized by a
JP58200827A 1983-10-28 1983-10-28 Constant-voltage diode Pending JPS6094780A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58200827A JPS6094780A (en) 1983-10-28 1983-10-28 Constant-voltage diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58200827A JPS6094780A (en) 1983-10-28 1983-10-28 Constant-voltage diode

Publications (1)

Publication Number Publication Date
JPS6094780A true JPS6094780A (en) 1985-05-27

Family

ID=16430860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58200827A Pending JPS6094780A (en) 1983-10-28 1983-10-28 Constant-voltage diode

Country Status (1)

Country Link
JP (1) JPS6094780A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008010379A (en) * 2006-06-30 2008-01-17 Mitsumi Electric Co Ltd Plug connector

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5527618A (en) * 1978-08-17 1980-02-27 Mitsubishi Electric Corp Planar diode
JPS57104270A (en) * 1980-12-22 1982-06-29 Hitachi Ltd Manufacture of constant-voltage element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5527618A (en) * 1978-08-17 1980-02-27 Mitsubishi Electric Corp Planar diode
JPS57104270A (en) * 1980-12-22 1982-06-29 Hitachi Ltd Manufacture of constant-voltage element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008010379A (en) * 2006-06-30 2008-01-17 Mitsumi Electric Co Ltd Plug connector

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