JPS6092653A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS6092653A JPS6092653A JP58200214A JP20021483A JPS6092653A JP S6092653 A JPS6092653 A JP S6092653A JP 58200214 A JP58200214 A JP 58200214A JP 20021483 A JP20021483 A JP 20021483A JP S6092653 A JPS6092653 A JP S6092653A
- Authority
- JP
- Japan
- Prior art keywords
- type
- island
- region
- integrated circuit
- silicon layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000009792 diffusion process Methods 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 40
- 229910052710 silicon Inorganic materials 0.000 abstract description 40
- 239000010703 silicon Substances 0.000 abstract description 40
- 229910052594 sapphire Inorganic materials 0.000 abstract description 19
- 239000010980 sapphire Substances 0.000 abstract description 19
- 238000000034 method Methods 0.000 abstract description 6
- 230000006866 deterioration Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- -1 for example Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 241000251468 Actinopterygii Species 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052596 spinel Inorganic materials 0.000 description 1
- 239000011029 spinel Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体集積回路装置に関し、詳しくはマスター
スライス方式によるＰ−ドアレイ型のＭＯ８型大規模集
積回路装置の改良に係る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device, and more particularly to an improvement of a P-dore array type MO8 type large-scale integrated circuit device using a master slice method.
マスタースライス方式とは、予め複数の素子からなる基
本セルを半導体基板に多数作シ、コンタクトホール及び
金属配線（配線ノセタ〜ン）を変更することによ）所望
の回路動作を得るものである。即チ、コンタクトホール
を形成するまでの半導体チップは全ての回路機能に対し
て共通である丸め、開発期間のＩＥｉ縮、製造コストの
低減を図ることが可能とな）、近年注目されている。The master slicing method is a method in which a desired circuit operation is obtained by creating a large number of basic cells each consisting of a plurality of elements on a semiconductor substrate in advance and changing the contact holes and metal wiring (wiring nosetan). In other words, rounding of the semiconductor chip (until contact holes are formed) is common to all circuit functions, which makes it possible to shorten the development period and reduce manufacturing costs) has attracted attention in recent years.
マスメースライス方式のｆ−）アレイでは、半導体チッ
プは基本セルが連なる基本セル領域と、基本セル群を相
互に接続する配線領域（）イールド領域）とから構成さ
れている。基本セルとして要求されることは、種々の機
能をもつ回路を実現できる形態をとると共に、単体のト
ランジスタとしての特性も要求される。In the mass-slice f-) array, the semiconductor chip is composed of a basic cell area in which basic cells are connected, and a wiring area (yield area) that interconnects the basic cells. A basic cell is required to have a form that can realize circuits with various functions, and also to have characteristics as a single transistor.
一方、絶縁基板上の半導体集積回路、代表的な例として
ＳＯＳ（Ｓｉｌｉｃｏｎ ｏｎ ｓａｐｐｈｉｒｅ）で
は、構造に起因する高速性と低消費電力を実現するため
に回路構成をＣＭＯＳ（ｃｏｍｐｌｅｍｅｎｔａｒｙ
ＭＯＳ）にして種々の半導体集積回路装置が実用化され
ている。このため、高速、低消費電力のＣＭＯＳ／ＳＯ
Ｓデバイスをゲートアレイ型集積回路装置として利用す
ることが行なわれている。具体的には、第１図（Ａ）〜
（Ｃ）に示す基本セルを複数配列した基本セル領域から
なるＣＭＯＳ／ＳＯＳのゲートプレイ構造が知られてい
る。即ち、図中１はサファイア基板でちり、この基板１
上にはフィールド酸化膜２で分離されたｐ型の島状シリ
コン層３、ｎ型の島状シリコン層４が夫々設けられてい
る。On the other hand, in semiconductor integrated circuits on insulating substrates, a typical example being SOS (Silicon on Sapphire), the circuit configuration is CMOS (complementary) to achieve high speed and low power consumption due to the structure.
Various semiconductor integrated circuit devices (MOS) have been put into practical use. Therefore, high speed, low power consumption CMOS/SO
S devices are being utilized as gate array type integrated circuit devices. Specifically, Figure 1 (A) ~
A CMOS/SOS gate play structure including a basic cell region in which a plurality of basic cells are arranged as shown in (C) is known. That is, 1 in the figure is a sapphire substrate, and this substrate 1
A p-type island silicon layer 3 and an n-type island silicon layer 4 separated by a field oxide film 2 are provided thereon.
前記ｐ型の島状シリコン層３にはソースもしくはドレイ
ン又はこれらを兼ねるｎ＋型領域５１〜５３が互に電気
的に分離して設けられている。また、ｎ型の島状シリコ
ン層４にも同様な機能をもっｐ＋型領領域６１〜６３が
互に電気的に分離して設けられている。なお、これらｎ
＋型、ｐ−型領域５１〜５８、６１〜６３はサファイア
基板１表面まで達するように形成されている。前記ｎ＋
領域５１、５２及び５２、５３間を含むｐ型のシリコン
層（基部領域）７，７上にはダート酸化膜８，８を介し
て例えばリンドープ多結晶シリコンからなるゲート電極
９１，９２が夫々設けられている。前記ｐ＋型領域６１
、６２及び６２、６３間を含むｎ型のシリコン層（基部
領域）１０．１０にはゲート酸化膜８，８を介して同様
なゲート電極９１′、９２′が設けられている。In the p-type island-like silicon layer 3, n+-type regions 51 to 53, which serve as a source, a drain, or both, are provided so as to be electrically isolated from each other. Furthermore, p+ type regions 61 to 63 having similar functions are provided in the n type island silicon layer 4 so as to be electrically isolated from each other. Furthermore, these n
The + type and p- type regions 51 to 58 and 61 to 63 are formed to reach the surface of the sapphire substrate 1. Said n+
Gate electrodes 91 and 92 made of, for example, phosphorus-doped polycrystalline silicon are provided on p-type silicon layers (base regions) 7 and 7 including between regions 51 and 52 and 52 and 53 via dirt oxide films 8 and 8, respectively. It is being The p+ type region 61
, 62 and 62, 63, similar gate electrodes 91', 92' are provided on the n-type silicon layer (base region) 10.10 with gate oxide films 8, 8 interposed therebetween.
なお、ゲート電極９１，９１′及び９２．９２′は夫々
一直線土に配列され共通電極部１１１、１１２により一
体的に連結されている。こうした構造によって、二列に
並んだｎチャンネルＭＯＳトランゾスタＴｒ１、Ｔｒ２
とこれらの並び方向に直交する方向に隣接した二列のｐ
チャンネルトランノスタＴｒ３、Ｔｒ４とからなる基本
セルが構成される。Note that the gate electrodes 91, 91' and 92, 92' are arranged in a straight line, respectively, and are integrally connected by common electrode portions 111, 112. With this structure, the n-channel MOS transistors Tr1 and Tr2 are arranged in two rows.
and p of two adjacent rows in the direction orthogonal to these alignment directions.
A basic cell is constituted by channel transnosters Tr3 and Tr4.
上述した第１図（Ａ）〜（Ｃ）に示す蒼本セルを用いて
、例えば第２図に示す如く全面に被覆された眉間絶縁膜
のｎ＋型領域５１、５２及びｐ＋増領域６１、６２の一
部に対応する箇所にコンタクトホール１２１〜１２４を
夫々開孔し、更に全面に金属膜（例えばＡｌ膜）を蒸着
し、パターニングしてコンタクトホール１２１を介して
ｎ＋型領域５１と接続するＡｌ配線（ＶＳＳ配線）１３
、同ホール１２４を介してｐ＋増領域６１と接続するＡ
ｌ配線（ＶＤＤ配線）１４、及びコンタクトホール１２
２、１２３を介してｎ＋型領域５２とｐ＋型領域６２と
接続するＡｌ配線（出力配線）１５を形成することによ
り、第３図に示すＣＭＯＳ／ＳＯＳインバータ回路を実
現できる。なお、第３図中のＶＤＤは電源電位、ＶＳＳ
は接地電位、Ｖｉｎは入力端子、Ｖｏｕｔは出力端子で
ある。かかるＣＭＯＳ／ＳＯＳインバータ回路において
、入力端子Ｖｉｎに“Ｈ”レベル信号（通常＋５Ｖ程度
）を入力すると、ｎチャンネルＭＯＳトランジスタＴｒ
１はＯＮ、ｐチャンネルＭＯＳトランゾスタＴｒ３はＯ
ＦＦし、出力端子Ｖｏｕｔは″Ｌ″レベル（０Ｖ付近）
となる。一方、入力端子Ｖｉｎに”Ｌ’レベルの信号（
０Ｖ程度）を入力すると、トランジスタＴｒ１はＯＦＦ
。Using the Aomoto cell shown in FIGS. 1(A) to (C) described above, for example, as shown in FIG. Contact holes 121 to 124 are respectively opened in locations corresponding to a part of Wiring (VSS wiring) 13
, A connected to the p+ increase region 61 via the same hole 124
l wiring (VDD wiring) 14 and contact hole 12
By forming an Al wiring (output wiring) 15 that connects the n+ type region 52 and the p+ type region 62 via 2 and 123, the CMOS/SOS inverter circuit shown in FIG. 3 can be realized. Note that VDD in Figure 3 is the power supply potential, VSS
is a ground potential, Vin is an input terminal, and Vout is an output terminal. In such a CMOS/SOS inverter circuit, when an "H" level signal (usually about +5V) is input to the input terminal Vin, the n-channel MOS transistor Tr
1 is ON, p-channel MOS transistor Tr3 is O
FF, and the output terminal Vout is "L" level (near 0V)
becomes. On the other hand, an “L” level signal (
When input voltage (approximately 0V), transistor Tr1 turns OFF.
.
トランジスタＴｒ３はＯＮして出力端子Ｖｏｕｔは電源
電位ＶＤＤレベル、つまり”Ｈ”レベル（＋５Ｖ付近）
となる。The transistor Tr3 is turned on and the output terminal Vout is at the power supply potential VDD level, that is, the "H" level (near +5V)
becomes.
しかしながら、基本セルを構成する各ＭＯＳトランジス
タＴｒ１〜Ｔｒ４のｎ型、ｐ型の領域５１〜５３．６１
〜６３がサファイア基板１表面まで達していると、フロ
ーティング状態になって基部領域７、７．１０．１０の
面積が少なくなるため、トランジスタの静特性に変化が
起こり、キンク電流と呼ばれる電流が流れる。これを第
４図を参照して説明する。但し、キンク電流はｎチャン
ネル及びｐチャンネルのいずれにも現れるが、特にｎチ
ャンネルにおいて顕著に現れるので第４図ではｎチャン
ネルＭＯＳトランジスタの場合を示した。第４図中の１
６１、１６２はソース配線で通常、接地電位（０Ｖ）に
固定されている。１７はドレイン配線で、これにかかる
電圧をＶＤとする。更に１８１ ＋１８２はダート配線
で、ここにかかる電圧をｖＧとする。However, the n-type and p-type regions 51 to 53, 61 of each MOS transistor Tr1 to Tr4 constituting the basic cell
~ 63 reaches the surface of the sapphire substrate 1, it becomes a floating state and the area of the base regions 7, 7, 10, and 10 decreases, causing a change in the static characteristics of the transistor and a current called kink current flowing. . This will be explained with reference to FIG. However, although kink current appears in both n-channel and p-channel, it appears particularly prominently in n-channel, so FIG. 4 shows the case of an n-channel MOS transistor. 1 in Figure 4
Reference numerals 61 and 162 are source wirings which are normally fixed at a ground potential (0V). 17 is a drain wiring, and the voltage applied thereto is VD. Further, 181 +182 are dirt wiring, and the voltage applied thereto is vG.
第４図図示のｎチャンネルＭＯＳトランジスタＴｒｌに
おいて、ｆ−）配線１８１に加えられるｖＧがしきい値
電圧（ＶＴ）以上になると、チャンネル領域１９が形成
され、ソース領域（ｎ型領域）５１の電子２０はドレイ
ン領域（ｎ型領域）５、に加えられたＶＤの電界に引か
れてチャンネル領域１９、チャンネルに沿うシリコン層
領域２１を移動し、ドレイン領域５雪に達し、これによ
ってドレイン電流として観察される。しかしながら、チ
ャンネル長が短かくなると、移動する電子２０は前記シ
リコン層領域２１で高電界による衝突電離を誘発し易く
なシ、その結果電子−旧札対を生成し易くなる。ここで
発生した電子２２はドレイン配線１７の電界に引かれて
ドレイン領域５２へ流れ込むが、正孔２３はフローティ
ング状態となっているシリコン層（基部領域）７へ流れ
込む。その結果、ｐ型シリコン層７を正にバイアスする
ため、しきい値電圧（ＶＴ ’）を浅くする。更には層
型ソース領域５１とｐ型シリコン層７のｐｎ接合の順方
向電位障壁を越える正孔が蓄積されると、ソース領域５
１とシリコン層７とドレイン領域５２とでｎｐｎ トラ
ンジスタが形成され、より大量の電流２４が流れる。In the n-channel MOS transistor Trl shown in FIG. 20 moves through the channel region 19 and the silicon layer region 21 along the channel due to the VD electric field applied to the drain region (n-type region) 5, and reaches the drain region 5, which is observed as a drain current. be done. However, when the channel length becomes short, the moving electrons 20 are less likely to induce impact ionization due to the high electric field in the silicon layer region 21, and as a result, electron-old banknote pairs are more likely to be generated. The electrons 22 generated here are attracted by the electric field of the drain wiring 17 and flow into the drain region 52, whereas the holes 23 flow into the silicon layer (base region) 7 which is in a floating state. As a result, in order to positively bias the p-type silicon layer 7, the threshold voltage (VT') is made shallow. Furthermore, when holes that exceed the forward potential barrier of the pn junction between the layered source region 51 and the p-type silicon layer 7 are accumulated, the source region 5
1, the silicon layer 7, and the drain region 52 form an npn transistor, through which a larger amount of current 24 flows.
一方、ｐ型、ｎ型の島状半導体層にソース、ドレイン領
域となる拡散領域をその底面がサファイア基板と所望距
離あけて設けた構造のｒ−トアレイ型集積回路装置も知
られている。しかしながら、こうした構造の集積回路装
置においても不都合が生じる。これを第５図のｎチャン
ネルＭＯＳ トランジスタを参照して説明する。トラン
ジスタ魚がＯＮ状態、トランジスタエｙノがＯＦＦ’状
態にあるとする。トランジスタηす、では第４図で既に
説明したのと同様、通常状態ではドレイン電流２５が流
れるにすぎないが、電界が強くなると、電子２２−正孔
２３対も生成され、正孔２３は基部領域７に流れ出す。On the other hand, an r-array type integrated circuit device is also known, which has a structure in which diffusion regions serving as source and drain regions are provided in p-type and n-type island-shaped semiconductor layers, the bottom surfaces of which are spaced a desired distance from the sapphire substrate. However, even in an integrated circuit device having such a structure, disadvantages occur. This will be explained with reference to the n-channel MOS transistor shown in FIG. Assume that the transistor fish is in the ON state and the transistor eno is in the OFF' state. In the transistor η, as already explained in FIG. 4, only the drain current 25 flows in the normal state, but when the electric field becomes strong, electron 22-hole 23 pairs are also generated, and the hole 23 is It flows into area 7.
こうした正孔２３の基部領域７への流出によシ、各ｎ＋
型領領域１′〜５３′はサファイア基板１表面まで達し
ておらず、浮いた状態でトランジスタＴｒＩ、 ）ラン
ノスタＴｒｌの基部領域７がつながった状態になってい
るため、トランジスタＴｒ１の基部領域のみならず、ト
ランジスタＴｒｙの電位をも変化する。その結果、極端
な場合はＯＦＦ状態にあるトランジスタ）もバックｙ＝
トパイアス効果忙よりＯＮ状態になってしまうという不
都合さを生じる。Due to the outflow of holes 23 to the base region 7, each n+
The mold regions 1' to 53' do not reach the surface of the sapphire substrate 1, and are connected to the base region 7 of the transistor TrI and ) rannostar Trl in a floating state. First, the potential of the transistor Try is also changed. As a result, in the extreme case the transistor which is in the OFF state) also backs up y=
This causes the inconvenience of being turned on due to the Topias effect.
〔発明の目的〕
本発明は短チャンネル化に伴なうキンク電流による素子
特性の劣化の抑制と、同一島状半導体層のＭＯＳトラン
ジスタの反転を抑制し、大規模集積回路として正常に動
作できうるｆ−）アレイ構造の半導体集積回路装置を提
供しようとするものである。[Object of the Invention] The present invention suppresses deterioration of device characteristics due to kink current accompanying shortened channels, suppresses inversion of MOS transistors in the same island-shaped semiconductor layer, and enables normal operation as a large-scale integrated circuit. f-) It is an object of the present invention to provide a semiconductor integrated circuit device having an array structure.
本発明は絶縁基板上の素子分離領域で分離された＠シ合
うｐ型、ｎ型の島状半導体層に例えば２つの？−）電極
をそれら半導体層を横切るように設け、Ｐ−）電極と素
子分離領域の間の島状半導体層に底面が絶縁基板表面ま
で達しない拡散領域を、？−）電極間の島状半導体層に
絶縁基板表面まで達する拡散領域を設けることによって
、短チャンネル化に伴なうキンク電流による素子特性の
劣化を抑制すると共に１同一島状半導体層内の２つのＭ
ＯＳ ）ランジスタを独立して動作させるようにしたこ
とを骨子とする。In the present invention, for example, two ? -) An electrode is provided across these semiconductor layers, and P-) A diffusion region whose bottom surface does not reach the surface of the insulating substrate is provided in the island-shaped semiconductor layer between the electrode and the isolation region. -) By providing a diffusion region that reaches the surface of the insulating substrate in the island-shaped semiconductor layer between the electrodes, it is possible to suppress the deterioration of device characteristics due to the kink current that accompanies the shortening of the channel, and to M
OS) The main point is that the transistors are operated independently.
次に１本発明の実施例を製造方法を併記して説明する。 Next, an embodiment of the present invention will be described along with a manufacturing method.
なお、製造工程ではｎチャンネルＭＯＳ ）ランゾスタ
のみを説明する。Note that in the manufacturing process, only the n-channel MOS (Lanzostar) will be explained.
（１） まず、厚さ５２５μｍのサファイア基板３１上
にシランがス（ＳＩＨ４ｆｆス）の熱分解によシ厚さ０
．６μｍの単結晶シリコン層を形成した後、選択酸化法
等によ多素子分離領域としてのフィールド酸化膜３２を
形成すると共にフィールド酸化膜３２で分離された複数
の島状シリコン層を形成した。つづいて、所定の島状シ
リコン層にビロンをイオン注入してｐ型島状シリコン層
３３とし、これに隣シ合う島状シリコン層に砒素をイオ
ン注入してｎ型島状シリコン層（図示せず）とした。ひ
きつづき、熱酸化処理を施してｐ型島状シリコン層３３
表面等忙厚さ４５０Ｘの熱酸化膜を成長させ、更に全面
に厚さ４５００にの多結晶シリコン膜を堆積し、これを
７４ターニングしてｐ型島状シリコン層３３、ｎ型島状
シリコン層を横切る互に平行な２つのＰ−ト電極３４１
゜３４２を形成した後、これらＰ−）電極３４１゜３４
３をマスクとして熱酸化膜をエツチングしてｆ−）酸化
膜３５・・・を形成した（第６図（ａ１図示）。(1) First, silane (SIH4ff) was thermally decomposed on a sapphire substrate 31 with a thickness of 525 μm.
．． After forming a 6 μm single crystal silicon layer, a field oxide film 32 as a multi-element isolation region was formed by selective oxidation or the like, and a plurality of island-shaped silicon layers separated by the field oxide film 32 were formed. Next, Viron is ion-implanted into a predetermined island-like silicon layer to form a p-type island-like silicon layer 33, and arsenic is ion-implanted into an adjacent island-like silicon layer to form an n-type island-like silicon layer (not shown). ). Subsequently, thermal oxidation treatment is performed to form the p-type island silicon layer 33.
A thermal oxide film with a thickness of 450× is grown on the surface, and a polycrystalline silicon film with a thickness of 4,500× is deposited on the entire surface, which is turned 74 times to form a p-type island silicon layer 33 and an n-type island silicon layer. Two P-to electrodes 341 parallel to each other across the
342, these P-) electrodes 341°34
The thermal oxide film was etched using No. 3 as a mask to form f-) oxide films 35 (FIG. 6 (a1)).
（ｉｉｌ 次いで、写真蝕刻法によｊＤｆ−）電極３４
１゜３４哀間のｐ型島状シリコン層３３部分が開口され
たレジストノーターン３６を形成した後、ｒ−ト電極”
ｌ ＋３４雪及びレジストパターン３６をマスクとして
ｎ型不純物、例えばリンを加速電圧５０ｋｅＶ、ドーズ
量４Ｘ１０１５３−２の条件でイオン注入してｐ型島状
シリコン層３３の深い箇所にリンイオン注入層３７を形
成した（第６図（ｂ）図示）。(iii then jDf-) electrode 34 by photolithography
After forming a resist no-turn 36 in which a portion of the p-type island-like silicon layer 33 between 1° and 34 mm is opened, an r-to electrode is formed.
A phosphorus ion implantation layer 37 is formed in a deep part of the p-type island-like silicon layer 33 by ion-implanting an n-type impurity, for example, phosphorus, using the +34 snow and resist pattern 36 as a mask under conditions of an acceleration voltage of 50 keV and a dose of 4×10153-2. (as shown in FIG. 6(b)).
（ｉｉｌｌ 次いで、レゾストノやターン３６を除去し
、再度、写真蝕刻法によＦ）？’−）電極３４Ｋ 。(iill Next, remove the resistance and turn 36 and use the photo-etching method again)? '-) Electrode 34K.
３４鵞とフィールド酸化膜３２間のｐ型島状シリコン層
３３部分が開口されたレジストノーターン３８を形成し
た。つづいて、Ｐ−）電極３４１゜３４１、フィールド
酸化膜３２及びレジストパターン３８をマスクとしてリ
ンを加速電圧４０ｋｓＶ ｓ Ｐ −！量２Ｘ１０１５
３−’＋７）条件でイオン注入してｐ型島状シリコン層
３３の浅い箇所Ｋ ＩＪンイオン注入層３９１，３９．
を形成した（第６図（ｃ）図示）。A resist no-turn 38 was formed in which a portion of the p-type island silicon layer 33 between the oxide film 34 and the field oxide film 32 was opened. Next, using the P-) electrode 341, the field oxide film 32, and the resist pattern 38 as a mask, phosphorus was accelerated at a voltage of 40 ksV s P-! Amount 2X1015
3-'+7) ion implantation layers 391, 39.
was formed (as shown in FIG. 6(c)).
Ｑψ 次いで、レジストパターン３８を除去した後、１
ｏｏｏ℃、２０分間の熱処理を施して、リンイオン注入
層３７＊３９１ ．３９１を活性化、拡散を行なった。Qψ Next, after removing the resist pattern 38, 1
Heat treatment was performed at ooo°C for 20 minutes to form a phosphorus ion-implanted layer 37*391. 391 was activated and spread.
これ釦より、ｒ−ト電極３４１゜３４１とフィールド酸
化膜３２０間のｐ型島状シリコン層Ｓ３に底部がサファ
イア基板３１表面から所定距離へだてたｎ＋型領領域１
ｒ４０１が形成されると共にＰ−）電極”１＋３４２間
のｐ型シリコン層３３に底部がサファイア基板３１表面
にまで達するｎ＋型領領域４１形成された（第６図Ｃ（
至）図示）。この後、ｎ型島状シリコン層についてもボ
ロンのイオン注入を前記（ｉｉ） 。When this button is pressed, an n+ type region 1 whose bottom part protrudes at a predetermined distance from the surface of the sapphire substrate 31 is formed in the p type island-like silicon layer S3 between the r-toe electrode 341 and the field oxide film 320.
At the same time as r401 is formed, an n+ type region 41 whose bottom reaches the surface of the sapphire substrate 31 is formed in the p type silicon layer 33 between the P- electrode "1+342" (FIG. 6C).
to) (as shown). Thereafter, boron ions are implanted into the n-type island-like silicon layer as described in (ii) above.
ｒｉｉｌｌと同様、レゾストパターンをマスクとしてイ
オン注入し、ｐ＋型領領域形成（但し熱処理はｎ＋型領
領域同一工程で行なう）し、基本セル４２１を備えたｆ
−）アレイ型集積回路装置を製造した（第７図、第８図
図示）。なお、第８図は第７図の■−■線に沿う断面で
あシ、４３はｎ型島状シリコン層である。４４１ ・４
４：はＣ−ト電極３４．，３４．とフィールド酸化膜３
２間の島状ｎ型シリコ７層４３表面に設けられ、底部が
サファイア基板３１表面から所定距離へだてられたｐ＋
型領領域４５はｆ−）電極３４哀。Similar to riill, ions are implanted using the resist pattern as a mask to form a p+ type region (however, the heat treatment is performed in the same step as the n+ type region), and an f with basic cell 421 is formed.
-) An array type integrated circuit device was manufactured (as shown in FIGS. 7 and 8). Incidentally, FIG. 8 is a cross section taken along the line ■-■ in FIG. 7, and 43 is an n-type island-shaped silicon layer. 441 ・4
4: C-to electrode 34. , 34. and field oxide film 3
The p +
The mold area 45 is f-) the electrode 34.
３４意間のｎ型島状シリコ７層４３ＪｆＣ設けられ、底
部がサファイア基板３１表面と接触したｐ増領域である
。Thirty-four layers of n-type island silicon 7 layers 43JfC are provided, and the bottom is a p-enhanced region in contact with the surface of the sapphire substrate 31.
本発明のｆ−）アレイ型集積回路装置は第６図Ｉ、第７
図及び第８図に示す如くサファイア基板３１上にフィー
ルド酸化膜３２にょシ分離されて設けられた互に隣接す
るｐ型、ｎ型の島状シリコン層３３．４３と、これら島
状シリコン層３３．４３をｆ−）酸化膜３５を介して横
切る互に平行な２つのＰ−）電極３４１．３４ｇと、こ
れらＰ−）電極３４％、３４意とフィールド酸化膜３２
の間のｐ型、ｎ型の島状シリコン層３３．３４に底部が
サファイア基板３１表面と所定距離へだてるように設け
られたｎ＋型領領域４０１＊ ４’＊ ％ ｐ＋型領領
域４４１．４４９ と、前記Ｐ−）電極３４１．３４意
間のｐ型、ｎ型の島状シリコン層３３．４３に底部がサ
ファイア基板３１表面まで達するように夫々設けられた
？属領域４１、ｐ＋型領領域４５から構成されたｎチャ
ンネルＭＯ８）ランジスタＴｒｌ ｒ Ｔｒ！とこれに
隣接したｐチャンネルＭＯ８）ランゾスタＴｒｙ ｅＴ
ｒ４からなる基本セル４２を複数配列した構造になって
いる。The f-) array type integrated circuit device of the present invention is shown in FIGS. 6I and 7.
As shown in FIG. 8 and FIG. 8, adjacent p-type and n-type island-shaped silicon layers 33 and 43 are separated from each other by a field oxide film 32 on a sapphire substrate 31, and these island-shaped silicon layers 33 .43 to f-) Two mutually parallel P-) electrodes 341.34g crossing through the oxide film 35, and these P-) electrodes 34%, 34 and the field oxide film 32.
An n+ type region 401*4'*% p+ type region 441. is provided in the p-type and n-type island-like silicon layers 33 and 34 between the p-type and n-type island-like silicon layers 33 and 34 so that the bottom part is oriented at a predetermined distance from the surface of the sapphire substrate 31. 449 and the p-type and n-type island-shaped silicon layers 33 and 43 between the P-) electrodes 341 and 34 were respectively provided so that their bottoms reached the surface of the sapphire substrate 31. An n-channel MO8) transistor Trl r Tr! composed of a primary region 41 and a p+ type region 45. and the adjacent p-channel MO8) Lanzosta Try eT
It has a structure in which a plurality of basic cells 42 consisting of r4 are arranged.
しかして本発明によれば、例えばｎチャンネルＭＯ８）
ランジスタＴｒ１．Ｔｒ意において、トランジスタＴｒ
ｌを構成するｎ＋型領領域ソース領域）４０１の底面が
サファイア基板３１表面に達しておらず、一方トランゾ
スタＴｒ４を構成するｎ型領域（ソース領域）４０１の
底面もサファイア基板３１表面に達していないため、そ
れらのｐ型基部領域４６．４６の面積を第４図図示の従
来構造に比べて大きくできる。その結果、短チャンネル
化に伴なうキンク電流の発生を抑制できる。また、トラ
ンジスタＴｒｌ ｒ Ｔｒ２の基部領域４６．４６は？
−ト電極３４１，３４．間のサファイア基板３１表面ま
で達した討型領域４７によシ分離され、それら基部領域
４６．４６の電位はトランジスタＴｒ１ ＊ Ｔｒ２に
依存して独立した状態となる。その結果、トランジスタ
ＴｒＩ側の基部領域４６への正孔の蓄積、電位変化がト
ランジスタＴｒ２の基部領域４６に影響を与えないため
、夫々のトランジスタＴｒｓ＋Ｔｒｌを独立して動作さ
せることができる。なお、ｎ型島状シリコ７層４３に形
成されたトランジスタ’ｒｒ３＋ ’ｒｒ４におりても
、そのｉ型基部領域４７．４７の面積増大、基部領域４
７．４７のｐ＋型領領域４５よる分離によって、同様な
効果が達成される。According to the invention, for example n-channel MO8)
Transistor Tr1. In Tr, the transistor Tr
The bottom surface of the n+ type region (source region) 401 constituting the transistor L does not reach the surface of the sapphire substrate 31, and on the other hand, the bottom surface of the n type region (source region) 401 constituting the transistor Tr4 also does not reach the surface of the sapphire substrate 31. Therefore, the areas of the p-type base regions 46, 46 can be made larger than in the conventional structure shown in FIG. As a result, the generation of kink current that accompanies shortened channels can be suppressed. Also, what about the base region 46.46 of the transistor Trl r Tr2?
- electrodes 341, 34. They are separated by a depressed region 47 that reaches the surface of the sapphire substrate 31 between them, and the potentials of these base regions 46 and 46 are independent depending on the transistors Tr1*Tr2. As a result, accumulation of holes and potential changes in the base region 46 on the transistor TrI side do not affect the base region 46 of the transistor Tr2, so each transistor Trs+Trl can be operated independently. Note that even in the transistor 'rr3+'rr4 formed in the n-type island-shaped silicon 7 layer 43, the area of the i-type base region 47.47 increases, and the base region 4
A similar effect is achieved by isolation by 7.47 p+ type regions 45.
なお、上記実施例では絶縁基板としてサファイア基板を
用いたが、この代シにスピネル基板を用いてもよく、或
いはＳＯＩ （Ｓｉｌｉｃｏｎ ｏｎｉｎｓｕｌａｔｏ
ｒ）構造にも同様に適用できる。In the above embodiments, a sapphire substrate was used as the insulating substrate, but a spinel substrate may be used instead, or an SOI (Silicon on Insulator) substrate may be used instead.
r) It can be similarly applied to structures.
以上詳述した如く、本発明によればキンク電流による素
子特性の劣化を抑制できると共に同一島状半導体層の複
数のＭＯＳ ）ランゾスタを独立して動作でき、ひいて
は大規模集積回路として正常に動作できうるｒ−）プレ
イ構造の半導体集積回路装置を提供できる。As detailed above, according to the present invention, it is possible to suppress the deterioration of device characteristics due to kink current, and also it is possible to operate multiple MOS transistors of the same island-shaped semiconductor layer independently, which in turn allows normal operation as a large-scale integrated circuit. It is possible to provide a semiconductor integrated circuit device having an urr-)play structure.
第１図（２）は従来のＰ−）アレイ型集積回路装置の基
本セルを示す平面図、同図［Ｂｌは同図ＩＡＪのＢ−Ｂ
線忙沿う断面図、同図（Ｃ１は同図ＩＡ）のｃ−ｃ線に
沿う断面図、第２図は従来の基本セルに、１配線を施す
ことによ多形成されたＣＭＯ８／ＳＯＳインバータ回路
の平面図、第３図は第２図のインパーク回路の回路図、
第４図は従来の集積回路装置の問題点を説明するための
断面図、第５図は従来の他の集積回路装置の問題点を説
明するだめの断面図、第６図（ａ）〜Ｃωは本発明の実
施例におけるｒ−ドアレイ型集積回路装置のｎチャンネ
ルトランジスタ側の製造工程を示す断面図、第７図は本
実施例方法で製造された集積回路装置の基本セルを示す
平面図、第８図は第７図の■−■線に沿う断面図である
。
、９１・・・サファイア基板、３２・・・フィールド酸
化膜、３３・・・ｐ型島状シリコン層、３４１゜３４？
・・・Ｐ−）電極、３５・・・Ｐ−）酸化膜、４０１１
４０！ １４１・・・ｎ＋型領領域４ ｊ ・・・基本
セル、４３・・・ｎ Ｍ １％ 状シリコンＩ、”ｔ＋
４４意 、４５・・・ｐ型領域、４６．４６・・・ｐ型
基部領域、４７．４７・・・ｎ型基部領域。
第１図
第２図
■２
第３図Figure 1 (2) is a plan view showing the basic cell of a conventional P-) array type integrated circuit device;
A cross-sectional view taken along line C--C in the same figure (C1 is IA in the same figure), and Figure 2 shows a CMO8/SOS inverter in which multiple wirings are formed by applying one wiring to a conventional basic cell. A plan view of the circuit, Figure 3 is a circuit diagram of the impark circuit in Figure 2,
FIG. 4 is a cross-sectional view for explaining the problems of a conventional integrated circuit device, FIG. 5 is a cross-sectional view for explaining the problems of another conventional integrated circuit device, and FIG. 6(a) to Cω 7 is a cross-sectional view showing the manufacturing process of the n-channel transistor side of the r-dore array integrated circuit device according to the embodiment of the present invention, and FIG. 7 is a plan view showing the basic cell of the integrated circuit device manufactured by the method of this embodiment. FIG. 8 is a sectional view taken along the line ■-■ in FIG. 7. , 91... Sapphire substrate, 32... Field oxide film, 33... P-type island silicon layer, 341°34?
...P-) electrode, 35...P-) oxide film, 4011
40! 141...n+ type region 4j...basic cell, 43...nM 1% silicon I, "t+"
44 meaning, 45... p type region, 46.46... p type base region, 47.47... n type base region. Figure 1 Figure 2 ■2 Figure 3
Claims (1)
ャンネルのＭＯＳ ）ランジスメからなる基本セルを複
数個配列して集積し、配線、４ターンによシ所望の動作
を実現する半導体集積回路装置において、前記各基本セ
ルを、絶縁基板上に素子分離領域によシ分離されて設け
られた基本セルの配列方向と直交する方向に互に隣接す
るｐ型、ｎ型の島状半導体層と、これら島状半導体層を
ｆ−）酸化膜を介して横切る互に平行な複数のＰ−）電
極と、これらｆ−）電極と前記素子分離領域の間のｐ型
、ｎ型の島状半導体層に底部が前記絶縁基板と所望距離
へだてるように夫々設けられた半導体層に対して反対導
電型の拡散領域と、前記各電極間のｐ型、ｎ型の島状半
導体層に＠部が前記絶縁基板表面忙達するように夫々設
けられた半導体層に対して反対導電型の拡散領域とによ
シ構成したことを特徴とする半導体集積回路装置。In a semiconductor integrated circuit device in which a plurality of basic cells consisting of a plurality of n-channel and p-channel MOS transistors are arranged and integrated on a semiconductor layer on an insulating substrate, and a desired operation is realized by wiring and four turns. , p-type and n-type island-shaped semiconductor layers adjacent to each other in a direction perpendicular to the arrangement direction of the basic cells provided on an insulating substrate and separated by element isolation regions; A plurality of mutually parallel P-) electrodes that cross the island-shaped semiconductor layer via an oxide film, and p-type and n-type island-shaped semiconductor layers between these f-) electrodes and the element isolation region. diffusion regions of opposite conductivity type to the semiconductor layers provided so that their bottoms extend to a desired distance from the insulating substrate; and p-type and n-type island-shaped semiconductor layers between the respective electrodes; 1. A semiconductor integrated circuit device comprising diffusion regions of opposite conductivity type to each semiconductor layer provided so as to cover the surface of an insulating substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58200214A JPS6092653A (en) | 1983-10-26 | 1983-10-26 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58200214A JPS6092653A (en) | 1983-10-26 | 1983-10-26 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6092653A true JPS6092653A (en) | 1985-05-24 |
| JPH0517711B2 JPH0517711B2 (en) | 1993-03-09 |
Family
ID=16420708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58200214A Granted JPS6092653A (en) | 1983-10-26 | 1983-10-26 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6092653A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6370439A (en) * | 1986-09-11 | 1988-03-30 | Seiko Epson Corp | Semiconductor integrated circuit device |
| US5264720A (en) * | 1989-09-22 | 1993-11-23 | Nippondenso Co., Ltd. | High withstanding voltage transistor |
| US6140161A (en) * | 1997-06-06 | 2000-10-31 | Nec Corporation | Semiconductor integrated circuit device and method for making the same |
| US6414357B1 (en) | 1998-06-05 | 2002-07-02 | Nec Corporation | Master-slice type semiconductor IC device with different kinds of basic cells |
| JP2003069027A (en) * | 2001-08-24 | 2003-03-07 | Semiconductor Energy Lab Co Ltd | Element group for evaluation and manufacturing method thereof, semiconductor device and method for evaluating the same |
-
1983
- 1983-10-26 JP JP58200214A patent/JPS6092653A/en active Granted
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6370439A (en) * | 1986-09-11 | 1988-03-30 | Seiko Epson Corp | Semiconductor integrated circuit device |
| US5264720A (en) * | 1989-09-22 | 1993-11-23 | Nippondenso Co., Ltd. | High withstanding voltage transistor |
| US6140161A (en) * | 1997-06-06 | 2000-10-31 | Nec Corporation | Semiconductor integrated circuit device and method for making the same |
| US6414357B1 (en) | 1998-06-05 | 2002-07-02 | Nec Corporation | Master-slice type semiconductor IC device with different kinds of basic cells |
| JP2003069027A (en) * | 2001-08-24 | 2003-03-07 | Semiconductor Energy Lab Co Ltd | Element group for evaluation and manufacturing method thereof, semiconductor device and method for evaluating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0517711B2 (en) | 1993-03-09 |
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