JPS6083292A - Address line driving circuit - Google Patents
Address line driving circuitInfo
- Publication number
- JPS6083292A JPS6083292A JP58191477A JP19147783A JPS6083292A JP S6083292 A JPS6083292 A JP S6083292A JP 58191477 A JP58191477 A JP 58191477A JP 19147783 A JP19147783 A JP 19147783A JP S6083292 A JPS6083292 A JP S6083292A
- Authority
- JP
- Japan
- Prior art keywords
- node
- potential
- address line
- power supply
- jsfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、ＢＰ几ＵＭ（ｅｌｅｃｔｒｉｃａｌｌｙ ｐ
ｒｏｇｒａｍｒｒ＋ａｂＩｃｒｅａｄ −ｏｎｌｙ ｍ
ｅｍｏｒｙ ）笠のＣＭｕＳ不揮発性メモリのアドレス
線駆動回路に関するっ
従来のこの種の不揮発性メモリのアドレス線駆動回路は
、第１図に回路図で示すように、節点１１と節点１２の
間に接続されたＭ（ＪＳＦＥＴ Ｑｌｌと１節点１３と
基準電源との間に接続されたＭ（ＪＳＦＥＴ Ｑｌ２と
１節点１３と節点１４０間に接続されたＭ（ＪＳＦＥＴ
Ｑｌ３と５節点Ｉ４と節点１２との間に接続されたＭ
（Ｊ８ＦＥＴＱ１４と、第２の１１Ｖｆｉ端子７と節点
１４の間に接線されたＭ（ＪＳＦ’Ｅ’ｌ’ Ｑｌ ５
と５節点１１に接続したアドレス線選択回路２２とか
ら成る。そして、Ｑｌｌ のゲーＬＨ節点１９に接続さ
れ、Ｑｌ２及びＱｌ３のゲートは節点１２に接続されｂ
Ｑ１４ のゲートは節点１３に接続され、Ｑｌ５ のゲ
ートは節点１５に接続されている。このアドレス線駆動
回路では符号２３で示す回路が電圧印加回路である。こ
こで、ＱｌｌはＮチャンネルティプレッション型トラン
ジスターｔ’ｌり、 ’Ｑ１２１１Ｎチヤンネルエンハ
ンスメント型トランジスタであシ、Ｑ１３，１４．１５
はＰチャンネルエンハンスメンＩ−ｍ トランジスタ
Ｔある。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a BP UM (electrically pUM).
rogramrr+abIcread -only m
Regarding the address line drive circuit of Kasa's CMuS nonvolatile memory, the conventional address line drive circuit of this type of nonvolatile memory is connected between nodes 11 and 12, as shown in the circuit diagram in FIG. M (JSFET Qll connected between 1 node 13 and the reference power supply)
Ql3 and 5 M connected between node I4 and node 12
(J8FET Q14 and M(JSF'E'l' Ql 5
and an address line selection circuit 22 connected to the five nodes 11. The gate of Qll is connected to the LH node 19, and the gates of Ql2 and Ql3 are connected to the node 12.
The gate of Q14 is connected to node 13, and the gate of Ql5 is connected to node 15. In this address line drive circuit, a circuit indicated by reference numeral 23 is a voltage application circuit. Here, Qll is an N-channel depression type transistor t'l, 'Q1211N-channel enhancement type transistor, Q13, 14.15
is a P-channel enhancement I-m transistor T.
なお、第１図の回路全般に電力葡供給する電位ＶＤＩ）
の第１の電源端子は本図では省略しである。Note that the potential VDI that supplies power to the entire circuit in Figure 1)
The first power supply terminal of is omitted in this figure.
読み出しの際１節点１５は第２の電源端子７と同電位に
するから、Ｑｌ５はｏｆｆ シ、節点１９’ｋｖＤＤに
することによりＱ１１は完全にｏｎ 状態になり、出力
端となる節点１２の電位はＱｌｌ’に通して、アドレス
線選択回路の出力節点１１に引かれて変化するウ
プログラムモードでは、第２の電源端子７の電位は、書
込み用の１０７以上の高電位になっているから、節点１
５はｌ、ｏｗにされることにより、節点１４の電位は第
２の電源端子７と同電（Ｓｌｊ（Ｖｒりになる。アドレ
スＲ’に選択する場合には、節点１１の電位がＨｉｇｂ
になり、Ｑｌｌ’に通して節点１２の電位も上がシ、
Ｑｌ２はｏｎｌ、、導通時におけるＱｌ３とＱｌ２の抵
抗比により節点１３の電位はＬｏｗに落ち、Ｑｌ４はｏ
ｎ状態になり、Ｑ１４葡通して節点１２の電位が上げら
れる。プログラムモードの時には節点１９はＬｏｗにさ
れるので、節点１２の電位が高くなっていくとＱｌｌは
ｏｆｆ シｓ節点１２の電位はＶＤＤ以上まで上がるこ
とができ、最終的にはＶＰＰまで上がる。アドレス線？
選択しない場合は、節点１１の電位ヶしＯＷにすること
によシ、Ｑｌｌ’に通して節点１２の電位は下げられる
為、Ｑｌ２はｏｆｆＬ−節点１３の電位はＶＦＰまで上
げられ＋ Ｑ １４ ｋ ｏｆｆさせる為。During reading, the first node 15 is set to the same potential as the second power supply terminal 7, so Ql5 is turned off, and by setting the node 19'kvDD, Q11 is completely turned on, and the potential of node 12, which is the output terminal, is turned off. is passed through Qll' and changes by being pulled to the output node 11 of the address line selection circuit.In the program mode, the potential of the second power supply terminal 7 is a high potential of 107 or more for writing, so Node 1
5 is set to l and ow, the potential of the node 14 becomes the same voltage as the second power supply terminal 7 (Slj (Vr). When selecting the address R', the potential of the node 11 becomes Highb
, and the potential at node 12 also increases through Qll'.
Ql2 is onl, the potential of node 13 falls to low due to the resistance ratio of Ql3 and Ql2 during conduction, and Ql4 is o
It becomes n state and the potential of node 12 is raised through Q14. In the program mode, the node 19 is set to Low, so as the potential of the node 12 increases, Qll turns off.The potential of the node 12 can rise to VDD or higher, and eventually rises to VPP. Address line?
If not selected, by setting the potential of node 11 to OW, the potential of node 12 is lowered through Qll', so Ql2 is offL - the potential of node 13 is raised to VFP + Q 14 k To turn it off.
節点１２の電位は基準電源電位まで下がる。The potential at node 12 drops to the reference power supply potential.
このｊうに作動する従来のアドレス線駆動回路は、エン
ハンスメント型又はティプレッション型のいずれか一方
のみのトランジスタからなる通常のＣＭ（ＪＳ回路では
なく、両方の型のトランジスタケ要するから、集積回路
化における製造工程が複雑となり、ひいては製造費が高
いという欠点があった。Conventional address line drive circuits that operate in this manner are conventional CM circuits (not JS circuits, which require transistors of both types, but are made up of transistors of either an enhancement type or a depression type), so they are difficult to integrate into integrated circuits. The disadvantage is that the manufacturing process is complicated and the manufacturing cost is high.
本発明の目的は、少ない工程で製造ｔきるＣＭ（Ｊ８不
揮発性メモリのアドレス線駆動回路の提供にある。An object of the present invention is to provide an address line drive circuit for a CM (J8 nonvolatile memory) that can be manufactured with fewer steps.
本発明によれば、節点ｌと節点２との間に接続されたＭ
Ｏ８ＦＢ’ｌ’１と５節点３と基準電源端子との間に接
続されたＭｕＳＦＥＴ２と５節点４と節点３との間に接
続されたＭ（ＪＳＩ”ＥＴ３と１節点４と節点２との間
に接続されたＭ（ＪＳＦＥＴ４と、第１の電位の電源端
子と基準電源端子と節点ｌとの間に接続されたアドレス
線選択回路とｔ有し、 Ｍ（Ｊ８ＦＥＴｔのゲートが電
源端子に接続され、Ｍ（ＪＳＦＥＴ２及びＭＩＪＳＦＥ
Ｔ３のゲートが共に節点ｌに接続され、Ｍ（ＪＳＦＥＴ
４のゲートが節点３に接続され、節点４には第１の電位
又は第１１７）電位より高い第２のＩＩ位のいずれかが
与えられるＣＭ（Ｊ８不揮発メモリのアドレス線駆動回
路が得られる。According to the present invention, M connected between node l and node 2
O8FB'l' MuSFET2 connected between 1 and 5 node 3 and the reference power supply terminal and 5 M M(JSFET4) connected to the power supply terminal, and an address line selection circuit connected between the first potential power supply terminal, the reference power supply terminal and the node l, and the gate of M(J8FETt) connected to the power supply terminal. , M (JSFET2 and MIJSFE
The gates of T3 are both connected to node l, and M(JSFET
An address line drive circuit for a CM (J8 nonvolatile memory) is obtained in which the gate of No. 4 is connected to node 3, and node 4 is given either the first potential or the second II level higher than the 117th) potential.
次に図面ケ参照して本発明の詳細な説明するっ第２図は
本発明の一実施例の回路図である。この実施例は、節点
１と節点２０間に接続されたＮチャンネルＭ（ＪＳＦＥ
Ｔ Ｑｌと、節点３と基準′ｉＩＮ、＃との間に接続さ
れたペチャンネルＭ（ＪＳＦＥＴ Ｑ２と５節点３と節
点４との間に接続されたＰチャンネルＭ（ＪＳＦＥＴＱ
３と５節点４と節点２との間に接続されたＰチャンネル
Ｍ（ＪＳＦＥＴＱ４と、第２の電源（ｖｐｐ）の電源端
子７と節点４との間に接続妊れたＰチャンネルＭ（Ｊ８
ＦＥＴＱ５と、第１の電源（ＶＤｎ ）の電源端子８と
節点４との間に接続されたＮチャンネルＭ（ＪＳＦＥＴ
Ｑ６と、節点１と基準電源との間に接続されたＮチャン
ネルＭ（ＪＳＦＥＴＱ７と、 ＶＤＤと節点ｌとの間に
接続されたＰチャンネルＭ（ＪＳＦＥＴ Ｑ８から成る
。これらのＭ（ＪＳＦＥＴ Ｑｌ〜Ｑ８はい−Ｊ’ｔＬ
モエンハンスメント型である。そしてｓＱｌのゲートは
ＶＤＤに接続され、Ｑ２及びＱ３のゲートは節点ｌに接
続され、Ｑ４のゲートは節点３に接続されているう読み
出しモードの際には、ｖｒｒ＝Ｖ＋巾であり、節点５０
屯位ｋ Ｌｏｗにすることにより、節点４０屯位はＶＤ
Ｉ）になる。このＶＤＩ）は前述の第１の電位であり、
一定である。プログラムモードｔてなるとＶＰＰ ＞Ｖ
ＤＤ （このときの”Ｊｒｐが前述の第２の電位である
）であり、節点５１節点６のｉｌｔ ６Ｚ ｋ共にＬｏ
ｗにすることにより、Ｑ５はｏｎｊ、、Ｑ６けｏｆｆす
る為、節点４の電位はＶｐｒまで上がる。プログラムベ
リファイモードではＶｐｐ ）） ＶＤＤであり。The present invention will now be described in detail with reference to the drawings. FIG. 2 is a circuit diagram of an embodiment of the present invention. This example uses an N-channel M (JSFE) connected between node 1 and node 20.
P-channel M (JSFET Q2 and 5) connected between node 3 and node 4;
3 and 5 P-channel M (JSFETQ4) connected between nodes 4 and 2, and P-channel M (J8
FETQ5 and an N-channel M (JSFET) connected between power supply terminal 8 of the first power supply (VDn) and node 4.
Q6, an N-channel M (JSFET Q7) connected between node 1 and the reference supply, and a P-channel M (JSFET Q8) connected between VDD and node l. Yes-J'tL
It is a mo-enhancement type. The gate of sQl is connected to VDD, the gates of Q2 and Q3 are connected to node l, and the gate of Q4 is connected to node 3. In read mode, vrr=V+width, and node 50
By setting the level k to Low, the node 40 level becomes VD.
become I). This VDI) is the above-mentioned first potential,
constant. When program mode is reached, VPP>V
DD (Jrp at this time is the above-mentioned second potential), and both ilt 6Z k of node 51 and node 6 are Lo.
By setting the voltage to w, Q5 is turned on, . . . Q6 is turned off, so that the potential of the node 4 rises to Vpr. In program verify mode, Vpp)) is VDD.
節点５１節点６の電位ケ共にＶＰＦまで上げることによ
ジＱ５はｏｆｆｌ、、Ｑ６はｏｎ状態となるから、節点
４の電位はＶＤＤになる
アドレス線が選択される場合には、ＱＢがｏｎしＱｌが
ｏｆｆすることによシ節点１の電位０弗餞はＶＤＤまで
上げられ、節点２の電位はＱｌ−通しテＶＤＤ −ＶＴ
ＮまＴ上げられる（ＶＴＮはＱｌのスレッシホールドｔ
ＴＪ、ｕＥ）。プログラムモードでアドレス線が選択さ
れた場合には、節点４の電位はＶｒｒ、！： ｆｌ Ｆ
） ＶＰＰ＞ ＶＤＩ）ゆえ、Ｑ２及びＱＢは共にｏｎ
状態となるが、Ｑ２及びＱＢのトランジスタサイズ奮考
應することにより、節点３の電位奮ＬＯ３き、節点３が
ｂｏｗになるとＱ４が０１１状態となハ節点２に電流が
流れ倦む。ＱｌのゲートはＶＤＤに接続されており、節
点ｌと節点２の電位が共にＶＤＤ−ＶＴＮ以上であれば
Ｑｌｉｊ：ｏｆｆ状態となるので、節点２０屯位は■ｒ
ｐｉで上けられる。プログラムモード以外においてアド
レス線が選択された場合には、節点４の電位はＶＤＤと
なり、Ｑ２及びＱＢは単なるインバータとして動作する
ので、節点３はＬｏｗになり＆Ｑ４はｏｎ状態になり、
節点２の電位はＶＤＤまで上げられる。By raising both the potentials of node 51 and node 6 to VPF, Q5 is turned off and Q6 is turned on, so the potential of node 4 becomes VDD.When an address line is selected, QB is turned on. By turning off Ql, the potential of node 1 is raised to VDD, and the potential of node 2 becomes Ql - VDD - VT.
It can be raised by N to T (VTN is the threshold of Ql
TJ, uE). When the address line is selected in program mode, the potential of node 4 is Vrr, ! : fl F
) VPP > VDI) Therefore, Q2 and QB are both on
However, by increasing the transistor size of Q2 and QB, the potential of node 3 is increased, and when node 3 becomes bow, Q4 becomes 011 state, and current flows to node 2 and stagnates. The gate of Ql is connected to VDD, and if the potentials of node l and node 2 are both VDD-VTN or higher, Qlij: off state occurs, so node 20 is
You can upload it with pi. When the address line is selected in a mode other than the program mode, the potential of node 4 becomes VDD, and Q2 and QB operate as mere inverters, so node 3 becomes Low & Q4 becomes on state,
The potential at node 2 is raised to VDD.
アドレス線が選択されない場合には、ＱＢがｏｆｆｌ、
、Ｑｌがｏｎ状態となり、節点ｌの電位葡Ｌｏｓｖに落
とし、Ｑ２’１ｏｆｆさせ、Ｑ ３ ’＜ ｏ ｎ状態
とするから、節点３の電位は節点４と同電位になυ、Ｑ
４はｏ ｆ ｆ Ｌ／ ｂ節点２０屯位はＱｌ及び９７
４通して基準１１詮電位まで下げられるっ本発明のアド
レス線駆動回路は、μ上説明したような構成でありディ
プレッショントランジスタ紮必要としないから、果債回
路として製造する際の工程数金紙らすことができ、した
がって安価に製造−ひきる。If the address line is not selected, QB offl,
, Ql turns on, drops to the potential Losv of node l, turns Q2'1 off, and sets Q3'< o n, so the potential of node 3 becomes the same potential as node 4, υ, Q
4 is of f f L/b node 20th position is Ql and 97
The address line drive circuit of the present invention is configured as described above and does not require a depletion transistor. It can be manufactured and ground at low cost.
第１図は従来のＣＭＩＪＳ不揮発メモリのアドレス線駆
動回路の回路図であり、第２図ｔま本発明の一実施例の
回路図であろう
Ｑｌ、 Ｑ２． Ｑ６． Ｑｌ、 Ｑｌ ２・・・・・
・Ｎチャンネルエン大７ｘメント型Ｍｕ８ＦＥＴ、Ｑｔ
ｔ ０．−１−Ｎ−ｙ−ヤンネルディプレッション型
Ｍ（ＪＳＦＥＴ、ＱＢ、Ｑ４． Ｑ５． ＱＢ、Ｑｌ
３． Ｑｌ ４． Ｑｌ ５・・・・・・Ｐ−ｙ−ヤン
ネルエンハンスメントｆｆｉＭ（ＪＳＦ’ＥＴ２．１２
−−−−−・出方端子、５，６，９，１０，１５゜１９
・・・・・・大刀端子、７・・・・・・第２の電源端子
（Ｖｐｐ）、８・・・・・・第１の電源端子（ＶＤＤハ
２０． ２２・・用アドレスＨ選択回路、２１．２３
・・・・・・電圧印加回路ウFIG. 1 is a circuit diagram of an address line driving circuit of a conventional CMIJS nonvolatile memory, and FIG. 2 is a circuit diagram of an embodiment of the present invention. Q6. Ql, Ql 2...
・N-channel large 7xment type Mu8FET, Qt
t 0. -1-Ny-Yannel depression type M (JSFET, QB, Q4. Q5. QB, Ql
3. Ql 4. Ql 5...P-y-Yannel Enhancement ffiM (JSF'ET2.12
------Output terminal, 5, 6, 9, 10, 15° 19
......Taito terminal, 7...2nd power supply terminal (Vpp), 8...1st power supply terminal (VDD) 20. Address H selection circuit for 22... , 21.23
・・・・・・Voltage application circuit c
Claims (1)
ＪＳＦＥＴと、第３の節点と基準電源端子との間に接続
された第２のＭ（ＪＳＦＥＴと、第４の節点と前記第３
の節点との間に接続された第３０Ｍ（ＪＳＦＥＴと、前
記第４の節点と前記第２の節点との間に接続された第４
のＭ（ＪＳＦＥＴと、第１の電位の電瞭端子と前記基準
電原端子と前記第１の節点との間に接続されたアドレス
線選択回路と勿有し、前記第１０Ｍ（ＪＳＦＥＴのゲー
ト電極が前記電源端子に接続され、前記第２及び第３の
Ｍ（Ｊ Ｓ Ｆ ＥＴのゲート電極が共に前記第１の節
点に接続され、前記第４（７）Ｍ（ＪＳＦＥＴのゲート
電極が前記第３の節点に接続され、前記第４の節点には
前記第１の電位又はこの第１の？［１位より高い第２の
電位のいずれかが与えられるアドレス線駆動回路。The first M(
JSFET, a second M connected between the third node and the reference power supply terminal (JSFET, the fourth node and the third
a 30M (JSFET) connected between the fourth node and the second node;
M (JSFET), an address line selection circuit connected between a voltage terminal at a first potential, the reference voltage terminal and the first node; is connected to the power supply terminal, the gate electrodes of the second and third M(JSFETs are both connected to the first node, and the gate electrodes of the fourth (7)M(JSFET) are connected to the first node. 3, and the fourth node is supplied with either the first potential or a second potential higher than the first node.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58191477A JPS6083292A (en) | 1983-10-13 | 1983-10-13 | Address line driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58191477A JPS6083292A (en) | 1983-10-13 | 1983-10-13 | Address line driving circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6083292A true JPS6083292A (en) | 1985-05-11 |
Family
ID=16275300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58191477A Pending JPS6083292A (en) | 1983-10-13 | 1983-10-13 | Address line driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6083292A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5264985A (en) * | 1990-11-28 | 1993-11-23 | Mitsubishi Denki Kabushiki Kaisha | Apparatus for increasing effective insulation between terminal plates |
-
1983
- 1983-10-13 JP JP58191477A patent/JPS6083292A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5264985A (en) * | 1990-11-28 | 1993-11-23 | Mitsubishi Denki Kabushiki Kaisha | Apparatus for increasing effective insulation between terminal plates |
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