JPS6077434A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6077434A
JPS6077434A JP58188092A JP18809283A JPS6077434A JP S6077434 A JPS6077434 A JP S6077434A JP 58188092 A JP58188092 A JP 58188092A JP 18809283 A JP18809283 A JP 18809283A JP S6077434 A JPS6077434 A JP S6077434A
Authority
JP
Japan
Prior art keywords
semiconductor chip
chip
insulating substrate
semiconductor
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58188092A
Other languages
English (en)
Inventor
Takayoshi Kawakami
川上　隆由
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58188092A priority Critical patent/JPS6077434A/ja
Publication of JPS6077434A publication Critical patent/JPS6077434A/ja
Pending legal-status Critical Current

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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、最近の半導体装置の高密度実装化傾向に適
合するように、回路構成後洗発見さねた不良半導体チッ
プの交換が容易になるよう医、半導体チップとその取付
はパット部との構成時における相互の寸法関係にあらか
じめ引剥しのための〔従来技術〕 第１図は従来の半導体装置を示すものである。
この図において、１はセラミック等からなる絶縁基板、
２は導電パターンを形成する電極、３は半導体チップ、
４はこの半導体チップ３ケ絶縁基板１上のその取付はバ
ット部Ａ上に機械的、電気的に接続するための接着剤、
５は前記半導体チップ３と電極２とを接続する金線であ
る。
一般に、混成集積回路装置とかマルチチップＩＣ等の半
導体装置の製造工程においては、目視検査または中間電
気試験により半導体チップ３の傷、電気的接続不良ある
いに接着不良が発見された場合は、こｈ４．不良品とし
て廃却するか、または当該半導体チップ３’／交換する
方法があるが、集積回路装置の種類の規模が拡太さねた
高密度実装の現状では、コストとの兼ね合いから後者の
半導体チップ交換作業が必要となってきている。
ところで、このような半導体装ｆｉにおいて、不良半導
体チップ乞交換するには、絶縁基板１ケ全接着剤４の接
着強度ン低下させ、半導体装ツブ３と接着剤４との接着
部をその側方より機械的に押すことにエリ、不良半導体
チップを取り除いていた。
このように取り除き作業は、半導体チップ３の接着部を
側方より押すことになるために、具体的にはＬＳＩチッ
プのようなものを取り除こうとすると、１０ｋ１７以上
の力を要し、こねかため専用治具な用いてもその取り除
き作業が非常に困難であった。
これは半導体チップ３の厚みが２５０ミクロン〜５００
ミクロンと薄いこと、半導体チップ側面（切断面）がそ
れ自体の結晶面により斜めになっていたりして、加えら
第１た力により斜めに割れてしまうということからであ
る。
なお、現在では、接着強度がより強いものが採用され、
例えば３５０℃で３０分間加熱した場合においても接着
強度の劣化が少ない接着剤を用いる傾向から、取り除き
作業をより困難にしているという欠点があった。
〔発明の概要〕 この発明は、上記のような従来のものの欠点ｌ除去する
ためＫなさねたもので、取＋ｊ１ナパット部として絶縁
基板に突出部を形成し半導体チップと取付はバット部と
の相互の寸法関係？生成不良半導体チップが容易に交換
できるようにしたものである。
〔発明の実施例〕
以下、この発明の一実施例について説明する。
第２図はこの発明の一実施例を示す側断面図で、第１図
と同一個所は同一符号で示している。絶縁基板１１の中
央には、半導体チップ３の直下に位置するように突出部
１１ｍを形成させ、かつ、この突出ｍ１ｌａを含めた半
導体装ツブ３の取付け／くント部への縦横寸法は、その
上に接着剤４で固着した半導体チップ３０ａｍ寸法より
小さくシ。
当該半導体チップ３の四辺の外周縁部を取付はバット部
Ａ外に突出させている点に特徴ケ有するものである。
このようにして、回路構成後に不具合が発見された、い
わゆる不良半導体チップを交換する場合には、従来の方
法と同様に絶縁基板を全体的若しくは局部的に加熱し、
半導体チップ３の突出外周縁部を引剥し治具の当て代と
して核部を下面から押し上げることが可能になるように
し、半導体チップ３の割ねを生することな（容易に取り
除くことができるようにしたものである。
なお、取付はバット部Ａ外に突出させる半導体チップ３
の外周縁部は必すしも四辺でなくとも前後あるいは左右
の二辺であつあもｊ、（・。
〔発明の効果〕
以上説明したよ５ＶＣ１この発明は、半導体チップより
その取利ロパット部を突出部とし、そσ〕面積を半導体
チップより小さくして、半導体クーツブの外周縁部を取
付はノくント部外に突出させて（・るりで、不良半導体
チップが発見された場合その引剥しが容易にでき、その
部分の交換グ）みですむので、特に作業ミスの多（なる
高密度のマルチチップ型理＃：集積回路装置にこの発明
を採用すること利点がある。
【図面の簡単な説明】
第１図は従来の半導体装置における半導体チップの取付
はバット部を示１−側断面図、第２図し工この発明の一
実施例を示す側断面−である。 図中、１は絶縁基板、３は半導体チップ、４番１接着剤
、１１＆は突出部、Ａは取付はパント部である。 なお、図中の同一符号はβ１−または相当部分ケ示す。 代理人　大岩増雄　Ｃ外２名） 手続補正書（自発） 昭和オ？年タ月／７日 特許庁長官殿　間色 １、事件の表示　特願昭５８−１８８０９２号２、発明
の名称　半導体装置 ３、補正をする者 ５、補正の対象 明細書の発明の詳細な説明の欄 ６、補正の内容 明細書第２頁１５行の１種類」を、「回路」と補正する
。 以上

Claims (1)

    【特許請求の範囲】
  1. 半導体チップ！固着する取付はパット部として絶縁基板
    に突出部ケ形成し、この突出部の前記半導体チップを固
    着する部分の面′ｆＲを前記半導体チップの面積より小
    さく形成して、この半導体チップの外周縁部を前記取付
    はパット部外に突出させ、この突出させた部分で不良半
    導体チップヶ引剥し治具の当て代を形成させたことを％
    徴とする半導体装置。
JP58188092A 1983-10-04 1983-10-04 半導体装置 Pending JPS6077434A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58188092A JPS6077434A (ja) 1983-10-04 1983-10-04 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58188092A JPS6077434A (ja) 1983-10-04 1983-10-04 半導体装置

Publications (1)

Publication Number Publication Date
JPS6077434A true JPS6077434A (ja) 1985-05-02

Family

ID=16217558

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58188092A Pending JPS6077434A (ja) 1983-10-04 1983-10-04 半導体装置

Country Status (1)

Country Link
JP (1) JPS6077434A (ja)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6137170A (en) * 1996-08-20 2000-10-24 Nec Corporation Mount for semiconductor device
WO2004074168A3 (en) * 2003-02-20 2005-04-14 Analog Devices Inc Packaged microchip with thermal stress relief
US6946742B2 (en) 2002-12-19 2005-09-20 Analog Devices, Inc. Packaged microchip with isolator having selected modulus of elasticity
US7166911B2 (en) 2002-09-04 2007-01-23 Analog Devices, Inc. Packaged microchip with premolded-type package
US8344487B2 (en) 2006-06-29 2013-01-01 Analog Devices, Inc. Stress mitigation in packaged microchips
US9676614B2 (en) 2013-02-01 2017-06-13 Analog Devices, Inc. MEMS device with stress relief structures
US10131538B2 (en) 2015-09-14 2018-11-20 Analog Devices, Inc. Mechanically isolated MEMS device
US10167189B2 (en) 2014-09-30 2019-01-01 Analog Devices, Inc. Stress isolation platform for MEMS devices
US11417611B2 (en) 2020-02-25 2022-08-16 Analog Devices International Unlimited Company Devices and methods for reducing stress on circuit components
US11981560B2 (en) 2020-06-09 2024-05-14 Analog Devices, Inc. Stress-isolated MEMS device comprising substrate having cavity and method of manufacture

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6137170A (en) * 1996-08-20 2000-10-24 Nec Corporation Mount for semiconductor device
KR100270828B1 (ko) * 1996-08-20 2000-11-01 가네꼬 히사시 반도체장치
US7166911B2 (en) 2002-09-04 2007-01-23 Analog Devices, Inc. Packaged microchip with premolded-type package
US6946742B2 (en) 2002-12-19 2005-09-20 Analog Devices, Inc. Packaged microchip with isolator having selected modulus of elasticity
WO2004074168A3 (en) * 2003-02-20 2005-04-14 Analog Devices Inc Packaged microchip with thermal stress relief
US8344487B2 (en) 2006-06-29 2013-01-01 Analog Devices, Inc. Stress mitigation in packaged microchips
US9676614B2 (en) 2013-02-01 2017-06-13 Analog Devices, Inc. MEMS device with stress relief structures
US10167189B2 (en) 2014-09-30 2019-01-01 Analog Devices, Inc. Stress isolation platform for MEMS devices
US10759659B2 (en) 2014-09-30 2020-09-01 Analog Devices, Inc. Stress isolation platform for MEMS devices
US10131538B2 (en) 2015-09-14 2018-11-20 Analog Devices, Inc. Mechanically isolated MEMS device
US11417611B2 (en) 2020-02-25 2022-08-16 Analog Devices International Unlimited Company Devices and methods for reducing stress on circuit components
US11981560B2 (en) 2020-06-09 2024-05-14 Analog Devices, Inc. Stress-isolated MEMS device comprising substrate having cavity and method of manufacture

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