JPS6074654A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6074654A
JPS6074654A JP58182851A JP18285183A JPS6074654A JP S6074654 A JPS6074654 A JP S6074654A JP 58182851 A JP58182851 A JP 58182851A JP 18285183 A JP18285183 A JP 18285183A JP S6074654 A JPS6074654 A JP S6074654A
Authority
JP
Japan
Prior art keywords
resin
mark
resin body
lead
ultraviolet ray
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58182851A
Other languages
Japanese (ja)
Inventor
Atsushi Tanaka
篤 田中
Takashi Matsuzaki
隆 松崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Components Co Ltd
Original Assignee
Toshiba Corp
Toshiba Components Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Components Co Ltd filed Critical Toshiba Corp
Priority to JP58182851A priority Critical patent/JPS6074654A/en
Publication of JPS6074654A publication Critical patent/JPS6074654A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To contrive to improve the reliability and to simplify the manufacturing process by increase of the moisture resistance and the mark strength by a method wherein an ultraviolet ray hardened type resin film is provided on the surface of a resin body so as to cover the upper surface of the mark of the resin body and the boundary on the surface of the resin body between the resin body and a metallic member. CONSTITUTION:A semiconductor element 11 is resin-sealed with a molding metal mold together with a lead 14 and an element arrangement base floor 12, resulting in the formation of the resin body 17. Marks for the product number and the like are printed on the upper surface of the body 17 with mark ink 18. Then, the transparent ultraviolet ray hardened type resin is applied on the surface of the body and then irradiated with ultraviolet rays, and accordingly the ultraviolet ray hardened type resin film 20 is formed so as to cover the part of lead-out of the upper surface of the mark and the lead 14 from the body and the boundary on the surface of the body between the base floor and the body. For example, an acrylic resin of mark ink, etc. from which pigment has been removed can be used as this ultraviolet ray hardened type resin. Thereafter, the unnecessary frames of the lead frame are cut down suitably.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、樹脂封止型の半導体装置に関し、特に半導体
素子の配設された素子配設台床がヒートシンクを兼ねる
ような半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a resin-sealed semiconductor device, and particularly to a semiconductor device in which an element mounting base on which semiconductor elements are arranged also serves as a heat sink.

〔発明の技術的背景〕[Technical background of the invention]

第１図は従来の半導体装置の構造の１例な示す図で、ヒ
ートシンクを兼ねる素子配設台床１２上に半導体素子１
１が例えば半田１３等によりマウントされ、金属板を打
ち抜き形成したり−ド１４のインナーリード部と半導体
素子１１の所定の部位とが、がンディングワイヤ１５に
より電気的接続されている。さらに、耐湿性向上の目的
でシリコン系エンキャップ剤１６により、上記半導体素
子１１が一次封止（エンキャップ）され、さらにシリコ
ン系エンキャップ剤１６を覆うように例えばエポキシ樹
脂等により二次封止が施されて所定形状の樹脂体１７が
構成され【いる。FIG. 1 is a diagram showing an example of the structure of a conventional semiconductor device, in which a semiconductor element 1 is mounted on an element mounting base 12 which also serves as a heat sink.
1 is mounted by, for example, solder 13 or the like, and the inner lead portion of the lead 14 formed by punching out a metal plate is electrically connected to a predetermined portion of the semiconductor element 11 by a bonding wire 15. Further, the semiconductor element 11 is firstly encapsulated (encapped) with a silicone-based encapsulant 16 for the purpose of improving moisture resistance, and is further secondarily encapsulated with, for example, an epoxy resin so as to cover the silicone-based encapsulant 16. is applied to form a resin body 17 having a predetermined shape.

そして、この樹脂体１７上の上面には、例えば製品番号
等のマークがマークインク１８により印刷されたものと
なっている。On the upper surface of this resin body 17, a mark such as a product number is printed with mark ink 18, for example.

〔背景技術の問題点〕[Problems with background technology]

ところで一般に樹脂封止型半導体装置では樹脂体１７と
金属部材よりなる素子配設台床１２およびリード１４と
の熱膨張係数の違いによって樹脂体１７に間隙が生じ、
この間隙より水分が樹脂体１７内に浸入する。従来の装
置では樹脂体１７内に浸入した水分が半導体素子１ノに
達するのを防止するためシリコン系エンキャップ剤１６
を用いて半導体素子１１を被覆している。By the way, in general, in a resin-sealed semiconductor device, a gap is created in the resin body 17 due to a difference in thermal expansion coefficient between the resin body 17 and the element mounting base 12 and the leads 14 made of metal members.
Moisture penetrates into the resin body 17 through this gap. In conventional devices, a silicone-based encapsulant 16 is used to prevent moisture that has entered the resin body 17 from reaching the semiconductor element 1.
The semiconductor element 11 is coated using the same.

しかしながら、エンキャップ剤１６よりデンディングワ
イヤ１５が露出しているため、エンキャップ剤１６によ
り覆れていない部分のアルミニウム線よりなるデンディ
ングワイヤ１５に水分が達することは防止できず、ボン
ディングワイヤ１５の腐食、断線、電流のリーク等がし
ばしば問題となる。その上、上記エンキャップ剤１６の
硬化のために約１０時間の多大な時間を要し、しかも樹
脂体１７用の樹脂材料としてはがンディングワイヤ１５
の腐食を生じに（くするため純度の高い高価なものを使
用しなげればならない。However, since the dending wire 15 is exposed from the encapsulant 16, moisture cannot be prevented from reaching the part of the dending wire 15 made of aluminum wire that is not covered by the encapsulant 16, and the bonding wire 15 Corrosion, wire breaks, current leaks, etc. often become problems. Moreover, it takes a long time of about 10 hours to harden the encapsulant 16, and the soldering wire 15 is used as the resin material for the resin body 17.
To avoid corrosion, high-purity and expensive materials must be used.

さらに、従来の装置では樹脂体１７の上面にマークイン
ク１８により印刷を行っているが、この印刷されたマー
クの鮮明度を保つためにマークインクによる印刷工程（
マーキング工程）の前に、組立工程中に付着した樹脂体
１７表面の汚染物を除去する必要があり、例えばトリク
レンによる樹脂体１７表面の拭取り或いはいわゆるバー
ニング等の前処理を行ねばならない。Furthermore, in the conventional apparatus, the mark ink 18 is printed on the upper surface of the resin body 17, but in order to maintain the clarity of the printed mark, the printing process using the mark ink (
Before the marking process), it is necessary to remove contaminants on the surface of the resin body 17 that have adhered during the assembly process, and it is necessary to perform a pretreatment such as wiping the surface of the resin body 17 with triclean or so-called burning.

また、マークインク１８の材質ても適当な強度が必要で
あり、高価、なものを使用しなければならない。Further, the material of the mark ink 18 must have appropriate strength and must be expensive.

〔発明の目的〕[Purpose of the invention]

本発明は上記のような点に鑑みてなされたもので、耐湿
性およびマーク強度に優れた半導体装置を提供し、信頼
性の向上、製造工程の簡素化および製品の低コスト化を
図ろうとするものである。The present invention has been made in view of the above points, and aims to provide a semiconductor device with excellent moisture resistance and mark strength, and to improve reliability, simplify the manufacturing process, and reduce the cost of the product. It is something.

〔発明の概要〕[Summary of the invention]

すなわちこの発明に係る半導体装置は、内部に半導体素
子が収納され上面に製品番号等のマークがマークインク
により印された樹脂封止型の樹脂体と、例えばリードや
ヒートシンク等、上記半導体素子に電気的接続され上記
樹脂体から露出した部分を有する金属部材とを有し、さ
らに上記樹脂体のマーク上面と、上記樹脂体表面におけ
る上記樹脂体と金属部材との境界上とを覆うように樹脂
体表面に密着性の良い紫外線硬化型樹脂膜がさらに設け
られているものである。In other words, the semiconductor device according to the present invention includes a resin-sealed resin body in which a semiconductor element is housed and a mark such as a product number is stamped on the upper surface with mark ink, and an electric conductor, such as a lead or a heat sink, for the semiconductor element. a metal member that is connected to the metal member and has a portion exposed from the resin body; A UV-curable resin film with good adhesion is further provided on the surface.

〔発明の実施例〕[Embodiments of the invention]

以下図面を参照して本発明の一実施例につき説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第２図の断面図において、例えばリード１４と一体とな
った素子配設台床１２上に例えば半田１３を用いて半導
体素子１１をマウントする。In the cross-sectional view of FIG. 2, a semiconductor element 11 is mounted using, for example, solder 13 on an element mounting base 12 that is integrated with leads 14, for example.

さらにリード１４のインナーリード部と上記半導体素子
１１の所定の部位とをアルミニウム線等からなるデンデ
ィングワイヤ１５を用いて接続する。Further, the inner lead portion of the lead 14 and a predetermined portion of the semiconductor element 11 are connected using a ending wire 15 made of an aluminum wire or the like.

次にこのような半導体素子１１をリード１４と素子配設
台床１２と共にモールド金型を用いて樹脂封止し、樹脂
体１７を形成する。Next, such a semiconductor element 11 is sealed with a resin together with the leads 14 and the element mounting base 12 using a molding die to form a resin body 17.

その後、樹脂体１７の上面にマークインク１８５− を用いて製品番号等のマークを印刷する。After that, mark ink 185- is applied to the upper surface of the resin body 17. Use to print marks such as product numbers.

続いて、樹脂体１７表面に透明の紫外線硬化型樹脂を塗
布し紫外線の照射を行って、上記マーク上面とリード１
４が樹脂体１７より引き出された部分と、樹脂体１７表
面における素子配設台床１２と樹脂体１７との境界上と
を覆うように紫外線硬化型樹脂膜２０を形成する。この
紫外線硬化型樹脂膜２０の硬化（キユアリング）は塗布
時間を含めて約６０秒で行うことができる。尚、この紫
外線硬化型樹脂としては、例えば顔料を抜いたマークイ
ンク等のアクリル系樹脂が使用できる。Next, a transparent ultraviolet curable resin is applied to the surface of the resin body 17, and ultraviolet rays are irradiated to form the upper surface of the mark and the lead 1.
An ultraviolet curable resin film 20 is formed so as to cover the portion where 4 is pulled out from the resin body 17 and the boundary between the element mounting base 12 and the resin body 17 on the surface of the resin body 17. Curing (curing) of this ultraviolet curable resin film 20 can be performed in about 60 seconds including the coating time. As this ultraviolet curable resin, for example, an acrylic resin such as mark ink without pigment can be used.

この後、適宜リードフレームの図示しない不要な枠部を
切り落とし、仕上げを行って製品が完成する。Thereafter, unnecessary frame portions (not shown) of the lead frame are appropriately cut off and finishing is performed to complete the product.

尚、上記実施例ではリードフレームの枠部の除去をマー
クインク１８によるマーキング工程および紫外線硬化型
樹脂膜２０の形成工程の後に行う場合を示したが、これ
は適宜マーキング工程の前或いは紫外線硬化型樹脂膜２
０の形成６一 工程前等に変更してよい。In the above embodiment, the frame portion of the lead frame is removed after the marking step with the mark ink 18 and the step of forming the ultraviolet curable resin film 20. Resin film 2
It may be changed one step before the 0 formation step 6, etc.

以上のようにして形成した半導体装置ではマークインク
１８と、リード１４および樹脂体１７の引き出された部
分２ノと、樹脂体１７と素子配設台床１２との接合部分
２２上とが紫外線硬化型樹脂膜２０により覆れたものと
なっている。In the semiconductor device formed as described above, the mark ink 18, the lead 14 and the pulled out portion 2 of the resin body 17, and the joint portion 22 between the resin body 17 and the element mounting base 12 are cured by ultraviolet light. It is covered with a mold resin film 20.

この紫外線硬化型樹脂膜２０は強度的にも優れ且つ樹脂
体１７の樹脂よりも金属との密着性が高く、樹脂体１７
への密着性も高いものである。This ultraviolet curable resin film 20 has excellent strength and has higher adhesion to metal than the resin of the resin body 17.
It also has high adhesion to the surface.

第３図に、従来の第１図に示す構造の装置と、紫外線硬
化型樹脂膜２０の膜厚が約１０μｍの第２図に示す構造
の装置とを対象に、耐湿性試験としてプレッシャー・ク
ツカー・テストを行い、半導体装置表面或いはボンディ
ングワイヤ間のリーク電流を測定した結果を示す。この
第３図のグラフで明らかなように、破線で示す従来の装
置では、プレッシャー・クツカー・テストの時間が増加
する程、リーク電流の平均値が増加する傾向てあり、そ
のばらつきも大きくなるが、実線で示す本実節゛□例゛
め装置では、１５０時間の試験を行ってもリーク電流の
増加は殆んど見られなかった。FIG. 3 shows a pressure tester as a moisture resistance test for the conventional device having the structure shown in FIG. 1 and the device having the structure shown in FIG.・The results of testing and measuring leakage current on the surface of the semiconductor device or between bonding wires are shown. As is clear from the graph in Figure 3, in the conventional device shown by the broken line, the average value of leakage current tends to increase as the time of the pressure puller test increases, and the variation also increases. In the present practical example device shown by the solid line, almost no increase in leakage current was observed even after 150 hours of testing.

また、従来の装置および本実施例装置の樹脂体の上面に
対しダイフロン（有機溶剤の１つ）による拭取り試験を
施した結果、従来の装置では１０回程度でマークインク
によるマークの一部が不鮮明になるのに対して、第２図
の本実施例装置では３０回の試験によっても樹脂体１７
表面の変化はみられなかった。In addition, as a result of performing a wiping test using Diflon (an organic solvent) on the upper surface of the resin body of the conventional device and the device of this embodiment, it was found that some of the marks made by the mark ink were removed in the conventional device after about 10 times. In contrast, in the apparatus of this embodiment shown in FIG. 2, the resin body 17 becomes unclear even after 30 tests.
No surface changes were observed.

〔発明の効果〕〔Effect of the invention〕

以上、実施例の項で説明したように、本発明による装置
では、耐湿性およびマーク強度に優れた半導体装置を得
られる。さらに従来の装置では約１０時間のエンキャッ
プ剤のキユアリング（硬化）工程が必要であったが本発
明装置では耐湿性が高いためエンキャップを省略しても
よい。これにより製造時間の大幅な短縮を図ることがで
きる。As described above in the embodiment section, the apparatus according to the present invention can provide a semiconductor device with excellent moisture resistance and mark strength. Further, while the conventional apparatus required a curing step of the encapsulant for about 10 hours, the apparatus of the present invention has high moisture resistance, so the encapping step may be omitted. This makes it possible to significantly shorten manufacturing time.

加えて、特にアルミニウムの腐食を避けるために従来使
用されていた高純度のモールド樹脂も、安価な樹脂に変
更でき、同様にマークインクも従来のような強度が必要
ないため安価なものに切り換えること力でできる。In addition, the high-purity molding resin that was previously used to avoid corrosion, especially of aluminum, can be replaced with a cheaper resin, and the mark ink can also be replaced with a cheaper one, as it does not need the strength of conventional marking inks. It can be done with force.

尚、紫外線硬化型樹脂の粘度により多少の違いはあるが
、樹脂の膜厚管理及び作業性の易さにより、紫外線硬化
型樹脂の膜厚は１．０μｍ〜３０．０μｍ程度が好まし
いものである。Although there are some differences depending on the viscosity of the ultraviolet curable resin, the film thickness of the ultraviolet curable resin is preferably about 1.0 μm to 30.0 μm due to ease of resin film thickness control and workability. .

また、半導体装置の形状は第２図に示すようなものに限
らず、例えばＤＩＰ　（Ｄｕａｌ　−Ｉｎ　−１１ｎｏ
　）型の装置等ヒートシンクを兼ねるような素子基台床
を有さない装置にも本発明は適用可能である。Furthermore, the shape of the semiconductor device is not limited to that shown in FIG.
) type of device, etc., which do not have an element base floor that also serves as a heat sink, are also applicable to the present invention.

以上のように本発明によれば耐湿性およびマーク強度に
優れた半導体装置を提供でき、装置の信頼性の向上、製
造工程の簡素化および製品コストの低廉化を実現できる
。As described above, according to the present invention, a semiconductor device with excellent moisture resistance and mark strength can be provided, and it is possible to improve the reliability of the device, simplify the manufacturing process, and reduce the product cost.

【図面の簡単な説明】 第１図は従来の半導体装置の構造を示す断面図、第２図
は本発明の一実施例に係る半導体装置の構造を示す断面
図、第３図は本発明の装置９− および従来の装置に対して施した耐湿性試験の結果を示
すグラフである。 １１・・・半導体素子、１２・・・素子配設台床、１４
・・・リード、１５・・・デンディングワイヤ、１８１
．。 マークインク、２０・・・紫外線硬化型樹脂膜。 出願人代理人　弁理士　鈴　江　武　彦１０−[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a sectional view showing the structure of a conventional semiconductor device, FIG. 2 is a sectional view showing the structure of a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a sectional view showing the structure of a semiconductor device according to an embodiment of the present invention. It is a graph showing the results of a moisture resistance test performed on Device 9- and a conventional device. 11... Semiconductor element, 12... Element placement platform, 14
... Lead, 15 ... Dending wire, 181
．． . Mark ink, 20...UV curable resin film. Applicant's agent Patent attorney Takehiko Suzue 10-

Claims (1)

【特許請求の範囲】[Claims] 内部に半導体素子が収納され表面にマークインクにより
マークの印された樹脂体と、上記半導体素子に電気的接
続され上記樹脂体と一体となっていると共に上記樹脂体
より露出した部分を有する金属部材と、上記マーク上と
上記樹脂体表面における樹脂体と金属部材との境界上と
を覆うように樹脂体表面を被覆する紫外線硬化型樹脂膜
とを具備していることを特徴とする半導体装置。a resin body with a semiconductor element housed therein and a mark marked with mark ink on its surface; and a metal member that is electrically connected to the semiconductor element, is integrated with the resin body, and has a portion exposed from the resin body. and an ultraviolet curable resin film that covers the surface of the resin body so as to cover the mark and the boundary between the resin body and the metal member on the surface of the resin body.
JP58182851A 1983-09-30 1983-09-30 Semiconductor device Pending JPS6074654A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58182851A JPS6074654A (en) 1983-09-30 1983-09-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58182851A JPS6074654A (en) 1983-09-30 1983-09-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6074654A true JPS6074654A (en) 1985-04-26

Family

ID=16125564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58182851A Pending JPS6074654A (en) 1983-09-30 1983-09-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6074654A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2577727B1 (en) * 2011-09-02 2016-03-16 SanDisk Semiconductor (Shanghai) Co., Ltd. Method for forming color images on memory devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2577727B1 (en) * 2011-09-02 2016-03-16 SanDisk Semiconductor (Shanghai) Co., Ltd. Method for forming color images on memory devices

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