JPS6070752A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6070752A
JPS6070752A JP58178611A JP17861183A JPS6070752A JP S6070752 A JPS6070752 A JP S6070752A JP 58178611 A JP58178611 A JP 58178611A JP 17861183 A JP17861183 A JP 17861183A JP S6070752 A JPS6070752 A JP S6070752A
Authority
JP
Japan
Prior art keywords
stage
chips
semiconductor device
lead
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58178611A
Other languages
Japanese (ja)
Inventor
Toshiyuki Yoda
敏幸 誉田
Junichi Kasai
純一 河西
Tsuyoshi Aoki
強 青木
Katsushi Yoshitoshi
吉利　勝志
Koichi Kobayashi
幸一 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58178611A priority Critical patent/JPS6070752A/en
Publication of JPS6070752A publication Critical patent/JPS6070752A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve mounting density, and to combine various chips by constituting a semiconductor device by superposing a plurality of chips in a multistage manner. CONSTITUTION:When manufacturing a semiconductor device 50, a chip 8 is loaded on a stage 2 in a lead frame 1 while a chip 9 is loaded on a stage 6 in a lead frame 5, and the chips 8, 9 are superposed through the stage 6 and bonded and unified by a tape 10. When stage bars 11, 12 for each lead frame are spot- welded on the unification, the chips are unified positively. Each lead 3 and the terminal sections of each chip 8, 9 are connected by wires 13, several chip 8, 9 and the base sections of several lead 3 are molded with an insulator 14, and lastly connecting sections 15 are cut and removed, thus completing the semiconductor device 50.

Description

【発明の詳細な説明】 発明の技術分野 本発明は実装密度の優れた半導体装置の製造方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device with excellent packaging density.

従来技術と問題点 従来の電子機器において多数の半導体素子を用いる場合
、回路基板上にこれらの半導体装置を配設して実装する
方式が従来一般に採用されている。Prior Art and Problems When a large number of semiconductor devices are used in a conventional electronic device, a method of disposing and mounting these semiconductor devices on a circuit board has been generally adopted.

このような場合に、回路基板面有効利用の観点から、よ
シ一層実装密度の優れた半導体装置が強く要望されてい
る。In such cases, from the viewpoint of effective use of the circuit board surface, there is a strong demand for semiconductor devices with even better packaging density.

発明の目的 本発明は上述の要望を満足させるためのもので、実装密
度の優れた半導体装置の製造方法を提供することを目的
としている。OBJECTS OF THE INVENTION The present invention is intended to satisfy the above-mentioned needs, and it is an object of the present invention to provide a method for manufacturing a semiconductor device with excellent packaging density.

発明の構成 ムの各ステージにそれぞれチップを搭載して該各チップ
を一方のチップを搭載するステージを介し重ね合せて一
体化し、次に前記各リードと前記各チップとをワイヤに
より接続した後、前記各リードの基部及び前記各チップ
を絶縁物にょシモールドし、最後に前記各リードフレー
ムの不要部分を除去することによシ上記目的の達成を図
っている。A chip is mounted on each stage of the component of the invention, and the chips are stacked and integrated via a stage on which one of the chips is mounted, and then each lead and each chip are connected with a wire, and then The above object is achieved by molding the base of each lead and each chip with an insulator, and finally removing unnecessary portions of each lead frame.

発明の実施例 以下、図面に関連して本発明の実、施例を説明する。Examples of the invention Hereinafter, embodiments of the present invention will be described with reference to the drawings.

第１図乃至第４図に第１の実施例を示す。A first embodiment is shown in FIGS. 1 to 4.

第１図及び第２図は半導体装置の製造に用いられるリー
ドフレームをそれぞれ示している。第１図のリードフレ
ーム１は、ステージ２と複数のリード６とを備えておシ
、ステージ２及び各リード３は２本の外枠４に一体に接
続されている。また第２図のリードフレーム５は、ステ
ージ６を備えておシ、該ステージ６は２本の外枠７に一
体に接続されている。1 and 2 each show a lead frame used in manufacturing a semiconductor device. A lead frame 1 shown in FIG. 1 includes a stage 2 and a plurality of leads 6. The stage 2 and each lead 3 are integrally connected to two outer frames 4. Further, the lead frame 5 in FIG. 2 includes a stage 6, and the stage 6 is integrally connected to two outer frames 7.

第６図及び第４図はこれらのリードフレームを用いて構
成された半導体装置５０の正面図及び側面図である。6 and 4 are a front view and a side view of a semiconductor device 50 constructed using these lead frames.

半導体装置５０の製造に際しては、まずリードフレーム
１のステージ２にチップ８を搭載するとともにリードフ
レーム５のステージ乙にチップ９を搭載し、次にチップ
８，９をステージ６を介し重ね合せテープ１０により接
着して一体化する。テープ１０は、例えばＡｔはく、ポ
リエステルフィルムの上下面に接着剤を塗布したものを
使用するが、Ａｔはくを使ったものは効熱性が優れてい
る。When manufacturing the semiconductor device 50, first the chip 8 is mounted on the stage 2 of the lead frame 1, and the chip 9 is mounted on the stage B of the lead frame 5, and then the chips 8 and 9 are placed on the stage 6 via the overlapping tape 10. to bond and integrate. The tape 10 is made of, for example, an At foil or a polyester film coated with an adhesive on the upper and lower surfaces, and tapes using At foil have excellent heat efficiency.

なお、この一体化時に、第４図に示したように各リード
フレームのステージバー１１．１２をスポット溶接する
と、一体化が確実に行われる。１６はスポット溶接部で
ある。Incidentally, at the time of this integration, if the stage bars 11 and 12 of each lead frame are spot welded as shown in FIG. 4, the integration will be reliably performed. 16 is a spot weld.

次に各リード３と各チップ８，９の端子部をワイヤ１６
によυ接続した後、各チップ８，９及び各リード３の基
部を絶縁物１４によりモールドし、最後に不要部分であ
る各リードフレームの外枠４，７及び各リード６間の接
続部１５を切断、除去して半導体装置５０が完成する。Next, connect the terminals of each lead 3 and each chip 8, 9 to the wire 16.
After making the connections, the bases of each chip 8, 9 and each lead 3 are molded with an insulator 14, and finally, the unnecessary portions of the outer frame 4, 7 of each lead frame and the connection part 15 between each lead 6 are molded. is cut and removed to complete the semiconductor device 50.

このような構成の半導体装置５０は、２つのチップ８，
９が重なっているため、実装密度が大幅に向上する。The semiconductor device 50 having such a configuration includes two chips 8,
9 overlap, the packaging density is greatly improved.

第５図乃至第８図に第２の実施例を示す。A second embodiment is shown in FIGS. 5 to 8.

本例の場合も、第５図に示すリードフレーム２１及び第
６図に示すリードフレーム２２を用いて第７．８図に示
す半導体装置６０を製造する。第７図は半導体装置６０
の正面図、第８図は同側面図である。リードフレーム２
１は比較的大きなステージ２６を備え、リードフレーム
２２は比較的小さなステージ２４と複数のリード２５と
を備えている。２６．２７は外枠、２８　、２９はステ
ージバー、３ｏはリードの接続部である。In this example as well, the semiconductor device 60 shown in FIG. 7.8 is manufactured using the lead frame 21 shown in FIG. 5 and the lead frame 22 shown in FIG. 6. FIG. 7 shows a semiconductor device 60
8 is a front view of the same, and FIG. 8 is a side view of the same. Lead frame 2
1 is equipped with a relatively large stage 26, and the lead frame 22 is equipped with a relatively small stage 24 and a plurality of leads 25. 26 and 27 are outer frames, 28 and 29 are stage bars, and 3o is a lead connection portion.

半導体装置６０の製造工程は前例と同様で、ステージ２
６に搭載されたチップ６１　とステージ２４に搭載され
たチップ５２はステージ２４を介しテープ６６により重
ね合せて一体化され、各チップ３１．３２はリード２５
とワイヤ６４にょシ接続され、各チップ５１．３２とリ
ード２５の基部は絶縁物６５によシモールドされ、不碩
部分である外枠２６．２７及び各リード２５間の接続部
６０を除去する。The manufacturing process of the semiconductor device 60 is the same as the previous example, and stage 2
The chip 61 mounted on the lead 25 and the chip 52 mounted on the stage 24 are overlaid and integrated by a tape 66 via the stage 24, and each chip 31, 32 is attached to the lead 25.
The bases of each chip 51, 32 and the leads 25 are molded with an insulator 65, and the blank parts of the outer frame 26, 27 and the connection part 60 between each lead 25 are removed.

本例の場合は前例よシ大きなチップを重ね合せることが
でき、よシ一層実装密度が向上する。In the case of this example, larger chips can be stacked on top of each other than in the previous example, and the packaging density is further improved.

上述の各実施例ではチップを２段重ねとする例について
述べたが、３段以上重ねることも勿論可能である。In each of the above-described embodiments, an example in which the chips are stacked in two stages has been described, but it is of course possible to stack the chips in three or more stages.

発明の効果 以上述べたように、本発明によれば、複数のチップを多
段状に重ねて半導体装置を構成するようになっているた
め、実装密度を向上させることができしかも色々なチッ
プの組み合せが可能である。Effects of the Invention As described above, according to the present invention, since a semiconductor device is constructed by stacking a plurality of chips in a multi-tiered manner, it is possible to improve the packaging density and also to combine various chips. is possible.

【図面の簡単な説明】[Brief explanation of drawings]

図面は本発明に係る半導体装置の製造方法を示すもので
、第１図及び第２図は第１の実施例の各リードフレーム
の平面図、第３図及び第４図は同半導体装置の正面図及
び側面図、第５図及び第６図は第２の実施例の各リード
フレームの平面図、第７図及び第８図は同半導体装置の
正面図及び側面図である。 図中、１，５．２１．２２はリードフレーム、２，６．
２３．２４はステージ、６，２５はリード、４１７．２
６．２７は外枠、８．９，３１．３２はチップ、１０．
３＋はテープ、１１　、１２，２８゜２９　はステージ
バー、’＋５．５４はワイヤ、１４．３５はモールド用
絶縁物、１５．３０はリード間接続部である。The drawings show a method for manufacturing a semiconductor device according to the present invention, and FIGS. 1 and 2 are plan views of each lead frame of the first embodiment, and FIGS. 3 and 4 are front views of the same semiconductor device. Figures 5 and 6 are plan views of each lead frame of the second embodiment, and Figures 7 and 8 are front and side views of the same semiconductor device. In the figure, 1, 5, 21, 22 are lead frames, 2, 6.
23.24 is stage, 6, 25 is lead, 417.2
6.27 is the outer frame, 8.9, 31.32 are chips, 10.
3+ is a tape, 11, 12, 28°29 is a stage bar, '+5.54 is a wire, 14.35 is an insulator for molding, and 15.30 is an inter-lead connection part.

Claims (1)

【特許請求の範囲】[Claims] ステージ及び複数のリードを備えたリードフレームとス
テージを備えたリードフレームの該各ステージにそれぞ
れチップを搭載して該各チップを一方のチップを搭載す
るステージを介し重ね合せて一体化し、次に前記各リー
ドと前記各チップとをワイヤにより接続した後、前記各
チップ及び前記リードの基部を絶縁物によシモールドし
、最後に前記各リードフレームの外枠及び前記各リード
間の接続部を除去することを特徴とする半導体装置の製
造方法。A lead frame is provided with a stage and a plurality of leads, and a chip is mounted on each stage of the lead frame provided with the stage, and the chips are stacked and integrated via a stage on which one of the chips is mounted, and then the above-mentioned steps are performed. After connecting each lead to each of the chips using wires, the bases of each of the chips and the leads are molded with an insulating material, and finally, the outer frame of each of the lead frames and the connecting portion between each of the leads are removed. A method for manufacturing a semiconductor device, characterized in that:
JP58178611A 1983-09-26 1983-09-26 Manufacture of semiconductor device Pending JPS6070752A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58178611A JPS6070752A (en) 1983-09-26 1983-09-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58178611A JPS6070752A (en) 1983-09-26 1983-09-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6070752A true JPS6070752A (en) 1985-04-22

Family

ID=16051472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58178611A Pending JPS6070752A (en) 1983-09-26 1983-09-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6070752A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0262530A1 (en) * 1986-09-23 1988-04-06 Siemens Aktiengesellschaft Semiconductor components having a power MOSFET and control circuit
KR100223125B1 (en) * 1996-12-31 1999-10-15 윤종용 Stacked chip package having chip on chip structure
EP0972307A1 (en) * 1995-12-19 2000-01-19 Micron Technology, Inc. Multi-chip device and method of fabrication employing leads over and under processes
US6049971A (en) * 1995-03-31 2000-04-18 Sgs-Thomson Microelectronics S.A. Casing for integrated circuit chips and method of fabrication

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0262530A1 (en) * 1986-09-23 1988-04-06 Siemens Aktiengesellschaft Semiconductor components having a power MOSFET and control circuit
US4947234A (en) * 1986-09-23 1990-08-07 Siemens Aktiengesellschaft Semiconductor component with power MOSFET and control circuit
US6049971A (en) * 1995-03-31 2000-04-18 Sgs-Thomson Microelectronics S.A. Casing for integrated circuit chips and method of fabrication
EP0972307A1 (en) * 1995-12-19 2000-01-19 Micron Technology, Inc. Multi-chip device and method of fabrication employing leads over and under processes
EP0972307A4 (en) * 1995-12-19 2000-01-19 Micron Technology Inc Multi-chip device and method of fabrication employing leads over and under processes
KR100223125B1 (en) * 1996-12-31 1999-10-15 윤종용 Stacked chip package having chip on chip structure

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