JPS6066672A - Phase controlling method of thyristor type 3-phase full- wave rectifier - Google Patents
Phase controlling method of thyristor type 3-phase full- wave rectifierInfo
- Publication number
- JPS6066672A JPS6066672A JP17317383A JP17317383A JPS6066672A JP S6066672 A JPS6066672 A JP S6066672A JP 17317383 A JP17317383 A JP 17317383A JP 17317383 A JP17317383 A JP 17317383A JP S6066672 A JPS6066672 A JP S6066672A
- Authority
- JP
- Japan
- Prior art keywords
- phase
- voltage
- output
- signal
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/145—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
- H02M7/155—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Rectifiers (AREA)
- Power Conversion In General (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、サイリスク式３相全波整流器の位相制御方法
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for controlling the phase of a thyrisk type three-phase full-wave rectifier.
この種の整流器の主回路は、６１１１ｉ１のサイリスク
をブリッジ接続して構成されるが、各サイリスクの通電
制御可能な期間は電源電圧率サイクル中の順電圧を受け
る期間即ち電気角で１２０度の位相範囲（３０〜１５０
．２１０〜３３０）となる為、該期間内に位相制御パル
スをサイリスクに供給しなければ欠相運転となる。この
位相制御パルスは、従来、チューロン回路等を用い、こ
れに入力される位相制御信号の大きさに対応した位相で
発生させるようにしているが、その発生位相を電源電圧
の０〜１８０度の範囲に亘って制御できる為、上記位相
制御信号が所定レベル以下、またはあるレベル以上にな
ると、位相制御パルスの発生位相が上記通電制御可能な
期間から外れ、そのままでは、欠相運転が起こると云う
問題があった。The main circuit of this type of rectifier is constructed by connecting 6111i1 cyrisks in a bridge, but the period during which the energization of each cyrisk can be controlled is the period during which the forward voltage is received during the power supply voltage ratio cycle, that is, the phase of 120 degrees in electrical angle. Range (30-150
．． 210 to 330), therefore, if the phase control pulse is not supplied to the cyrisk within this period, an open phase operation will occur. Conventionally, this phase control pulse is generated using a Turon circuit or the like with a phase corresponding to the magnitude of the phase control signal input to the circuit. Since it can be controlled over a range, if the phase control signal goes below a predetermined level or above a certain level, the generation phase of the phase control pulse will deviate from the period in which energization can be controlled, and if left as is, open-phase operation will occur. There was a problem.
この為、従来は、上下限リミッタを設りて位相制御信号
のレベル範囲を制限することにより上記欠相運転を防い
でいるが、整流器の機能調整を現場で行う場合に上記上
下限リミッタの調整ミスにより過電流が発生して遮断器
が働いてしまうなどの面倒を惹起していた。For this reason, conventionally, upper and lower limiters are installed to limit the level range of the phase control signal to prevent the above-mentioned phase loss operation, but when adjusting the rectifier function on site, the upper and lower limiters are adjusted Mistakes caused problems such as overcurrents causing circuit breakers to trip.
本発明は、この問題点に鑑みてなされたもので、位相制
御されるサイリスク式３相全波整流器の交流電源の相間
電圧と同相の電圧をΔ結線検出トランスで取り出し、こ
れら電圧とその９０度進み位相の電圧のＡＮＤ信号及び
Ｎ ＯＲ信号、該ＡＮＤ信号とＮＯＲ信号にそれぞれ基
づく鋸歯状波信号、及び位相制御信号を用いてゲートパ
ルスの発生タイミングを決定する構成とすることにより
、節用な構成であるが、位相制御信号のレベルが過大も
しくは過小になっても、欠相を起こすことなく確実にサ
イリスクを点弧することができるサイリスク式３相全波
整流器の位相制御方法を提供することを目的とする。The present invention has been made in view of this problem, and uses a delta connection detection transformer to extract voltages in phase with the phase-to-phase voltage of the AC power source of a phase-controlled thyrisk-type three-phase full-wave rectifier, and extracts these voltages and their 90 degrees. The configuration is such that the gate pulse generation timing is determined using an AND signal and a NOR signal of leading phase voltages, a sawtooth wave signal based on the AND signal and the NOR signal, and a phase control signal. However, it is an object of the present invention to provide a phase control method for a thyrisk-type three-phase full-wave rectifier that can reliably ignite the thyrisk without causing phase loss even if the level of the phase control signal becomes too high or too low. purpose.
以下、本発明の一実施例を図面を参照して説明する。Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図において、１０は出力側がＹ結線された電源トラ
ンスあって、＋ａｌ、（ｂｌ及び（Ｃ１はそれぞれＡ相
、Ｂ相及びＣ相の出力端子、＋０１は中性点を示してい
る。２０は位相制御される３相全波整流器であって、６
（１＆ｌのサイリスク２１〜２６をブリッジ接続して構
成され、その直流出力端子ｄ−ｅ間にはフライボイルダ
イオード２７が挿入されている。各サイリスク２１〜２
６には位相制御装置３０から所定の順序で位相制御パル
スＧ１〜Ｇ６が供給される。In FIG. 1, 10 is a power transformer whose output side is Y-connected; +al, (bl and (C1) are the output terminals of the A phase, B phase and C phase, respectively, and +01 is the neutral point. 20 is a phase-controlled three-phase full-wave rectifier, and 6
(It is constructed by connecting the cyrisks 21 to 26 of 1&l in a bridge manner, and a flyboil diode 27 is inserted between the DC output terminals d.Each of the cyrisks 21 to 2
6 are supplied with phase control pulses G1 to G6 in a predetermined order from the phase control device 30.
次に、上記位相制御装置３０を第１図及び第２図につい
て説明する。該位相制御装置１ｔ３０は、その入力部に
位相変換用の検出Ｉ・ランス３１を有している。該検出
トランス３１の入力巻線はΔ結線されて？Ｔｉｉ＋７ｉ
ｉトランス１０の出力側に接続されている。Ｘ、、Ｙ、
Ｚは検出Ｉ・ランス３１の出力巻線であって、出力巻線
Ｘば電源のΔ相電圧Ｖａに対して位相が３０度遅れた遅
れ電圧Ｖｃａ、出力巻線Ｙは電源のＢ相電圧ｖｂに対し
て位相が３０度遅れた遅れ電圧Ｖａｂ、出力巻線Ｚは電
源のＣ相電圧Ｖ ｃ、に対して位相が３０度遅れた遅れ
電圧ｖｂＣをそれぞれ出力する。３２Ａは位相変換回路
であって、出力巻線Ｘが送出する遅れ電圧Ｖｃａが供給
され、該遅れ電圧Ｖｃａより９０度進み位相の進め電圧
■τ１を出力する。３３Ａ及び３４Δは波形成形回路で
あって、前者は遅れ電圧Ｖｃａを矩形波に波形成形して
出力し、後者は進み電圧■ττを矩形波に波形成形して
出力する。３５ＡはＡ Ｎ Ｉ）素子、３６ＡはＮＯＲ
素子であって、共に波形成形された進み電圧Ｖττと波
形成形された遅れ電圧Ｖｃａとが導かれ、ＡＮＤ素子３
５Ａは■τ１とＶｃａが共に正である場合にＡＮｌ）信
号Ｐｃａ（Ｈレベル）を発生し、ＮＯＲ素子３６Ａは■
ττとＶｃａが共に負である場合にＮ ＯＲ信号ｔμａ
（Ｈレベル）を発生ずる。３２Ｉ３は位相変換回路であ
って、出力巻線Ｙが送出する遅れ電圧Ｖａｂが供給され
、該遅れ電圧Ｖａｂより９０度進み位相の進め電圧Ｖａ
丁を出力する。３３Ｂ及び３４Ｂは波形成形回路であっ
て、前者は遅れ電圧Ｖａｂを矩形波に波形成形して出力
し、後者は進み電圧Ｖａｂを矩形波に波形成形して出力
する。３５ＢはＡＮＤ素子、３６ＢはＮＯＩン素子であ
って、共に波形成形された進め電圧ｖｂτと波形成形さ
れた遅れ電圧Ｖｂｃとが導かれ、ＡＮＤ−素子３５Ｂは
Ｖａｂと■ａＩ）が共ニ正テアル場合にＡＮＤ信号Ｐａ
ｂ（Ｈレベル）を発生し、Ｎ ＯＲ素子３６ＢはＷｉｌ
とＶａｂが共に負である場合にＮ ＯＲ信号り１立（１
−Ｉレベル）を発生ずる。３２Ｃは位相変換回路であっ
て、出力巻線Ｚが送出する遅れ電圧Ｖｂｃが供給され、
該遅れ電圧Ｖｂｃより９０度進み位相の進み電圧Ｖｂｃ
を出力する。３３Ｇ及び３４Ｃは波形成形回路であって
、前者は遅れ電圧Ｖ ｂ ｃを矩形波に波形成形して出
力し、後者は進み電圧ｖｂ■を矩形波に波形成形して出
力する。３５ＣはＡＮＤ素子、３６ＣはＮ ＯＲ素子で
あって、共に波形成形された進み電ＩＬ’Ｖ ｂ ｃと
波形成形された遅れ電圧Ｖｂｃとが導かれ、ＡＮＤ素子
３５ＣはＶｂｃとＶｂｃが共に正である場合にＡＮＤ信
ｑｌ）ｂ ｃ （ＩＩレレベ）を発生し、Ｎｏ）ン素子
３６Ｇは７ｂｃとＶｂｃが共に負である場合にＮＯＲ信
号ヱ亙ｃ（１−ルベル）を発生ずる。Next, the phase control device 30 will be explained with reference to FIGS. 1 and 2. The phase control device 1t30 has a detection lance 31 for phase conversion at its input portion. Is the input winding of the detection transformer 31 connected in Δ? Tii+7i
It is connected to the output side of the i-transformer 10. X,,Y,
Z is the output winding of the detection I/lance 31, the output winding X is the delayed voltage Vca whose phase is delayed by 30 degrees with respect to the Δ phase voltage Va of the power supply, and the output winding Y is the B phase voltage Vb of the power supply. The output winding Z outputs a delayed voltage Vab whose phase is delayed by 30 degrees with respect to the C-phase voltage Vc of the power supply, and a delayed voltage VbC whose phase is delayed by 30 degrees with respect to the C-phase voltage Vc of the power supply. 32A is a phase conversion circuit, which is supplied with the delayed voltage Vca sent out by the output winding X, and outputs an advanced voltage ■τ1 which is 90 degrees ahead of the delayed voltage Vca in phase. 33A and 34Δ are waveform shaping circuits, the former shaping the delayed voltage Vca into a rectangular wave and outputting it, and the latter shaping the leading voltage ■ττ into a rectangular wave and outputting it. 35A is AN I) element, 36A is NOR
An AND element 3 in which both a waveform-shaped lead voltage Vττ and a waveform-shaped lag voltage Vca are guided.
5A generates ■AN1) signal Pca (H level) when both τ1 and Vca are positive, and NOR element 36A generates ■
When ττ and Vca are both negative, the NOR signal tμa
(H level) is generated. 32I3 is a phase conversion circuit, to which the delayed voltage Vab sent out by the output winding Y is supplied, and the phase-advanced voltage Va is 90 degrees ahead of the delayed voltage Vab.
Outputs ding. 33B and 34B are waveform shaping circuits, the former shaping the delayed voltage Vab into a rectangular wave and outputting it, and the latter shaping the leading voltage Vab into a rectangular wave and outputting it. 35B is an AND element, and 36B is an NOI-in element, from which both the waveform-shaped leading voltage vbτ and the waveform-shaped lag voltage Vbc are guided, and the AND-element 35B is such that Vab and ■aI) are both positive. AND signal Pa if
b (H level), and the NOR element 36B
and Vab are both negative, the NOR signal is 1 (1
-I level). 32C is a phase conversion circuit to which the delayed voltage Vbc sent out by the output winding Z is supplied;
A leading voltage Vbc that is 90 degrees ahead of the delayed voltage Vbc and has a phase lead of 90 degrees
Output. 33G and 34C are waveform shaping circuits, the former shaping the delayed voltage Vbc into a rectangular wave and outputting it, and the latter shaping the leading voltage Vb■ into a rectangular wave and outputting it. 35C is an AND element, and 36C is an NOR element, from which both the waveform-shaped leading voltage IL'Vbc and the waveform-shaped lag voltage Vbc are guided, and the AND element 35C has both Vbc and Vbc positive. In a certain case, the AND signal ql)bc (II level) is generated, and when both 7bc and Vbc are negative, the NOR signal ql)bc (1-level) is generated.
ＡＮＤ素子３５Ａ、３５Ｂ及び３５ＣのＡＮＤイｉｉ
’ｒ’７ ｐ （’、 ；］ 、、 Ｐ ａ ｌ）及び
ｐｂｃはＯＲ，４Ｓ子３７−１を介して鋸歯状波発生回
路３８−１に供給される。また、Ｎ ＯＲ素子３６Ａ、
３６１３及び３ｃｃの出力■且ａ、ｐａｂ及びＬ立上は
ＯＲ１子３７−２を介して鋸歯状波発生回路３８−２に
（ｌ給される。鋸歯状波発生回路３８−１はＡＮｕ）信
号Ｉ）ｃａ、Ｐａｂ及びｐｂｃの立上りに同＋１ＪＩ
して負の所定ルベルから零レベルに立上り該零レベルか
ら所定勾配で増大し、ＡＮＤ信号Ｐｃａ＝Ｐａｂ及びＰ
ｂ ｃの立下りに同期して上記負の所定ルベルまで立
下る波形の出力Ｑｌを発生する。鋸歯状波発生回路３８
−２はＮ ＯＲ信号ヱ匹且、Ｐ ａ丸及びｐ 亙ｃの立
上りに同期して負の所定ルベルから零レベルに立上り該
零レベルから所定勾配で増大し、Ｎ ＯＲ信号ヱ互主、
旦支上及び工」しくの立下りに同期して上記負の所定ル
ベルまで立下る波形の出力Ｑ２を発生する。鋸歯状波発
生回路３８−１の出力Ｑ１は比較回路３９−１で位相制
御信号Ｘと比較され、また、鋸歯状波発生回路３８−２
の出力Ｑ２は比較回路３９−２で位相制御信号ｘと比較
される。比較回路３９−１は、Ｑｌ ＞ｘである場合に
信号Ｍｌ（Ｈレベル）を発生し、比較回路３９−２は、
Ｑ２＞Ｘである場合に信号Ｍ２（Ｈルベル）を発生ずる
。４０−１はＮＡＮＤＡＮＤ素子て、比較回路３９−１
の出力Ｍｌの反転信号とＯＲ素子３７−１の出力とが導
かれ、信号Ｍ１に同期する出力に１を発生ずる。この出
力に１はワンショットマルチ４１−１に供給され、該ワ
ンショットマルチ４１−１は信号Ｍｌの立上りもしくは
ＯＲ素子３７−１の出力の立−１・りに同期して所定の
小時間１１Ｊのパルスｐ１を発生ずる。AND iii of AND elements 35A, 35B and 35C
'r'7 p (', ;] , , P a l) and pbc are supplied to the sawtooth wave generation circuit 38-1 via the OR, 4S element 37-1. In addition, NOR element 36A,
The outputs of 3613 and 3cc, and the rising edges of a, pab, and L are fed to the sawtooth wave generation circuit 38-2 via the OR1 child 37-2.The sawtooth wave generation circuit 38-1 is an ANu signal. I) +1JI at the rise of ca, Pab and pbc
and rises to zero level from a negative predetermined level, increases from the zero level at a predetermined slope, and AND signal Pca=Pab and P
An output Ql having a waveform falling to the negative predetermined level is generated in synchronization with the falling of bc. Sawtooth wave generation circuit 38
-2 rises from a predetermined negative level to zero level in synchronization with the rise of P a and p c, and increases from the zero level at a predetermined slope, and the N OR signal is mutually independent.
A waveform output Q2 is generated that falls to the above-mentioned negative predetermined level in synchronization with the fall of the mechanical and mechanical signals. The output Q1 of the sawtooth wave generation circuit 38-1 is compared with the phase control signal X in the comparison circuit 39-1, and the output Q1 of the sawtooth wave generation circuit 38-2
The output Q2 of is compared with the phase control signal x in the comparison circuit 39-2. Comparison circuit 39-1 generates signal Ml (H level) when Ql > x, and comparison circuit 39-2 generates signal Ml (H level).
When Q2>X, a signal M2 (H level) is generated. 40-1 is a NAND AND element, and a comparison circuit 39-1
The inverted signal of the output M1 of the circuit and the output of the OR element 37-1 are guided, and 1 is generated at the output synchronized with the signal M1. 1 is supplied to this output to a one-shot multi 41-1, and the one-shot multi 41-1 receives a predetermined short period of 11J in synchronization with the rising edge of the signal Ml or the rising edge of the output of the OR element 37-1. A pulse p1 is generated.
４０−２はＮＡＮＤＡＮＤ素子て、比較回路３９−２の
出力Ｍ２の反転信号とＯＲ素子３７−２の出力とが導か
れ、信号Ｍ２に同期する出力に２を発生ずる。この出力
に２はワンショットマルチ・４１−２に供給され、該ワ
ンショットマルチ４Ｉ−２は１３号Ｍ２の立」ニリもし
くはＯＲ素子３７−２の出力の立下りに同期して所定の
小時間中のパルスｐ２を発生する。４２Ａ、４２Ｂ、４
２ＣはＡＮｕ）素子であって、それぞれにはＡＮＤ素子
３５Ａ、３５Ｂ、３５Ｇの出力Ｐ ｃ ａ ％ Ｐ ａ
ｂ 、、ＰｂＣが遅延素子４３八、４３Ｂ、４３Ｃを
それぞれ介し゛（供給されると共にパルスｐ１が供給さ
れる。１１人、土１且、土叢旦はＡＮＤ素子であって、
それぞれにはＮ ＯＲ素子３６Ａ、３６１３．３６Ｃの
出力ｔμ主、丑土上、上±土が遅延素子４３八、土主旦
、↓１旦をそれぞれ介して供給されると共にパルスｐ２
が供給される。４４はリングカウンクであって、ＡＮＤ
素子４２Ａ〜土１旦の出力Ｎａ−凡且にそれぞれ間１９
１する位相制御パルスＧ１〜Ｇ ６をダブルパルス化し
て発生ずる。Reference numeral 40-2 denotes a NAND AND element, to which the inverted signal of the output M2 of the comparator circuit 39-2 and the output of the OR element 37-2 are guided, and generates 2 at the output synchronized with the signal M2. This output 2 is supplied to the one-shot multi 41-2, and the one-shot multi 4I-2 waits for a predetermined short period of time in synchronization with the rise of No. 13 M2 or the fall of the output of the OR element 37-2. The middle pulse p2 is generated. 42A, 42B, 4
2C is an ANu) element, and each of them has an output P c a % P a of AND elements 35A, 35B, and 35G.
b, , PbC are supplied through the delay elements 438, 43B, and 43C, and the pulse p1 is also supplied.
The outputs tμ main, Ushido top, and top±Sat of NOR elements 36A and 3613.36C are supplied to each of them through delay elements 438, Tatsudo, and ↓1, respectively, and the pulse p2
is supplied. 44 is a ring counter, AND
Output Na of element 42A to Saturday 1-approximately 19 respectively
The phase control pulses G1 to G6, which are equal to 1, are generated as double pulses.
次に、この装置の動作について、第３図の波形タイムヂ
ャ−１・を参照して説明する。Next, the operation of this device will be explained with reference to waveform timer 1 in FIG.
電源トランスｌＯが出力する３相交流の電源電圧（相電
圧）Ｖａ、ｖｂ、Ｖｃは検出トランス３１を介して位相
制御装置３０に取り込まれるが、該検出トランスばΔ結
線である為、その出力電圧は前記した通り上記電源電圧
より３０度位相遅れの電圧となる。出力巻線Ｘの電圧に
ついて説明すれば、該出力巻線Ｘは電源電圧のＡ相電圧
Ｖａより３０度だけ位相が遅れた電圧Ｖｃａを出力する
。位相変換された遅れ電圧Ｖｃａは、位相変換回路３２
Ａで９０度進み位相の電圧■τ］に変換される。この遅
れ電圧Ｖｃａと進み電圧■τ１はＡＮＤ素子３５Δに供
給され、該Ａ Ｎ Ｉ）素子３５Ａは遅れ電圧Ｖｃａの
零位相、即ち電源電圧Ｖａの３０度位相に立上り、進み
電圧の１８０度位相、即ら電源電圧Ｖａの１２０度位相
に立下るＡＮＤ信号Ｐｃａを送出する。同様にし−Ｃ，
ＡＮ＋）素子３５Ｂからは、電源電圧ｖｂの３０度位相
に立上り１２０度位相で立下るＡＮＤ信号Ｐ；１ｂが送
出され、ＡＮＤ素子３５Ｇからは、電源電圧Ｖｃの３０
度位相に立上り１２０度位相で立下る出力Ｐ ｂ ｃが
送出される。鋸歯状波発生回路３８−１はＡＮＤ信号Ｐ
ｃａ、Ｐａｂ、Ｐｂｃを受けてそれぞれの立上り時点か
ら所定の勾配でレベル上昇し立−トリ時点に同期して立
下る３０度間隔の鋸歯状波の信号Ｑ１を発生ずる。Three-phase AC power supply voltages (phase voltages) Va, vb, and Vc output by the power transformer IO are taken into the phase control device 30 via the detection transformer 31, but since the detection transformer is Δ-connected, its output voltage As described above, is a voltage with a phase delay of 30 degrees from the above power supply voltage. To explain the voltage of the output winding X, the output winding X outputs a voltage Vca whose phase is delayed by 30 degrees from the A-phase voltage Va of the power supply voltage. The phase-converted delayed voltage Vca is transferred to the phase conversion circuit 32.
It is converted into a voltage ■τ] with a phase lead of 90 degrees at A. The lagging voltage Vca and the leading voltage ■τ1 are supplied to the AND element 35Δ, and the AN I) element 35A rises at the zero phase of the lagging voltage Vca, that is, at the 30-degree phase of the power supply voltage Va, and at the 180-degree phase of the leading voltage. That is, an AND signal Pca falling at a 120 degree phase of the power supply voltage Va is sent out. Similarly -C,
AN+) element 35B sends out an AND signal P;1b that rises at a 30-degree phase of power supply voltage vb and falls at a 120-degree phase, and AND element 35G sends an AND signal P;
An output P b c that rises and falls at a 120 degree phase is sent out. The sawtooth wave generating circuit 38-1 receives the AND signal P.
In response to ca, Pab, and Pbc, a sawtooth wave signal Q1 is generated at 30 degree intervals whose level rises at a predetermined slope from the respective rising points and falls in synchronization with the rising and falling points.
この信号Ｑ１は比６２回路３９−１で位相制御信号Ｘと
比較されるが、位相制御信号Ｘのレベルが信号Ｑｌの最
大値Ｑ１ｍａｘと零レベルの間にある場合は両レベルは
交差するので、比較回路３９−１の出力Ｍ１は、信号Ｑ
１が位相制御信号Ｘのレベルまで上昇した時点で立上り
、信４ｊＱ１の立下り時点で立下る断続信号となり、こ
の立」ニリに同期して発生ずるＮＡＮＤ素子４０−１の
出力Ｋｌによりワンショットマルチ４１−１が駆動され
てパルスｐ１を発生ずる。この時ＡＮＤ素子４２Ａには
遅延素子４３Ａを介してＡＮＤ素子３５Ａの出力Ｐｃａ
が入力されているので、該ＡＮｌ）素子４２Ａばパルス
ｐ１を受Ｌ３ると同時に（Ｑ １ ＝ ｘの時点）パル
スＮａを発生ずる。Ａ Ｎ Ｉ）素子４２Ｂ、４２Ｃか
らは、同様に、それぞれＡＮＤ信号Ｐｂｃ、Ｐｃａの発
生中にパルスｐｉに同期するパルスＮｂ、Ｎｃを発生ず
る。逆に、位相制御信号Ｘが上昇して信号Ｑ ’ｌの最
大値ＱＬｍａｘを超えた時には、上記反転信号は１４レ
ベルのままであるが、ＯＲ素子３７−１の出力の立下り
時点にＮＡＮＤ素子４０−１の出力が立上るのでパルス
ｐｉ、＃ｌ＜発生し、この時、進み電圧■τ］が零レベ
ルになってＡ Ｎ Ｉ）信号１） ｃａは消滅するが、
遅延素子４３Ａがある為、ＡＮＤ素子４２八はＡＮＤ信
号Ｐｃａの消滅時点にパルスＮａを発生ずる。このよう
に、位相制御信号Ｘのレベルが信号Ｑ１の最大値Ｑ１ｍ
ａｘを超えた場合には、進み電圧■τ１の零点降下時に
同期してＡＮＤ素子４２ＡがパルスＮａを発生ずる。Ａ
ＮＤ素子４２Ｂ、４２Ｃの出力Ｎｂ、Ｎｃについても同
様である。This signal Q1 is compared with the phase control signal X in the ratio 62 circuit 39-1, but if the level of the phase control signal X is between the maximum value Q1max of the signal Q1 and the zero level, the two levels cross. The output M1 of the comparison circuit 39-1 is the signal Q
It becomes an intermittent signal that rises when signal 1 rises to the level of phase control signal 41-1 is driven to generate a pulse p1. At this time, the AND element 42A is connected to the output Pca of the AND element 35A via the delay element 43A.
is input, the AN1) element 42A receives the pulse p1 and simultaneously generates the pulse Na (at the time of Q 1 =x). A N I) Elements 42B and 42C similarly generate pulses Nb and Nc that are synchronized with pulse pi while generating AND signals Pbc and Pca, respectively. Conversely, when the phase control signal Since the output of 40-1 rises, a pulse pi, #l is generated, and at this time, the leading voltage ■τ] becomes zero level and the ANI) signal 1) ca disappears, but
Since the delay element 43A is provided, the AND element 428 generates the pulse Na at the time when the AND signal Pca disappears. In this way, the level of the phase control signal X reaches the maximum value Q1m of the signal Q1.
When the voltage exceeds ax, the AND element 42A generates a pulse Na in synchronization with the zero point drop of the lead voltage ■τ1. A
The same applies to the outputs Nb and Nc of the ND elements 42B and 42C.
このように、パルスＮａ、Ｎｂ、Ｎｃの発生時点は位相
制御信号Ｘのレベル上昇に伴ってＡＮＤ信’信置３１〕
ｃ ％ Ｐ ａ ｂ ％ Ｐ ｂ ｃの立上り時点から
立下り時点に向かって移動するが、信号Ｑｌの最大値Ｑ
ｌ ｒｎ ａ ｘを超えた後は該立下り時点に固定さ
れてしまうので、位相制御パルスＧ１、Ｇ２、Ｇ３ば電
源電圧Ｖａ、Ｖｂ、Ｖｃの３０度位相から１２０度位相
の間に必ず１回発生ずる。In this way, the generation points of the pulses Na, Nb, and Nc are determined by the AND signal 31 as the level of the phase control signal X increases.
c % P a b % P b Moves from the rising point of c to the falling point, but the maximum value Q of the signal Ql
After exceeding lrn a x, it is fixed at the falling point, so the phase control pulses G1, G2, and G3 are always applied once between the 30-degree phase and the 120-degree phase of the power supply voltages Va, Vb, and Vc. Occurs.
上記遅れ電圧Ｖｃａと進み電圧■τｉは、また、ＮＯＲ
素子３６Ａに供給され、該ＮＯＩ？素子３６Ａからは遅
れ電圧Ｖｃａの１８０度位相、即ち電源電圧Ｖｃの２１
０度位相に立上り、進み電圧の３６０度位相、即ち電源
電圧Ｖａの３００度位相に立下るＮＯＲ信号Ｐｃａが送
出される。同様にして、ＮＯＲ素子３６Ｂからは、電源
電圧ｖｂの２１０度位相に立上り３００度位相で立下る
ＮＯＲ信号Ｐａｂが送出され、ＮＯＲ素子３６Ｃからは
、電源電圧Ｖｃの２１０度位相に立上り３００度位相で
立下るＮＯＲ信号ヱｂｃが送出される。鋸歯状波発生回
路３８−２はＮＯＲＯＲ信号上土工ユコ＋、Ｐｂｃを受
けてそれぞれの立上り時点から所定の勾配でレベル上昇
し立下り時点に同期して立下る３０度間隔の鋸歯状波の
信号Ｑ２を発生する。The above lagging voltage Vca and leading voltage ■τi are also NOR
is supplied to element 36A, and the NOI? From the element 36A, there is a 180 degree phase of the delayed voltage Vca, that is, 21 degrees of the power supply voltage Vc.
A NOR signal Pca that rises at a 0 degree phase and falls at a 360 degree phase of the leading voltage, that is, a 300 degree phase of the power supply voltage Va, is sent out. Similarly, the NOR element 36B sends out a NOR signal Pab that rises at a 210-degree phase and falls at a 300-degree phase of the power supply voltage vb, and the NOR signal Pab rises at a 210-degree phase and falls at a 300-degree phase of the power supply voltage Vc. A NOR signal ebc that falls at this point is sent out. The sawtooth wave generation circuit 38-2 receives the NOROR signals UDOKU YUKO+ and Pbc, and generates a sawtooth wave signal at 30 degree intervals, which rises in level at a predetermined slope from the respective rising points and falls in synchronization with the falling points. Generates Q2.
この信号Ｑ２は比較回路３９−２で位相制御信号Ｘと比
較されるが、位相制御信号Ｘのレベルが信号Ｑ２の最大
値Ｑ ２ ｍ ａ ｘと零レベルの間にある場合は両し
ベルは交差するので、比較回路３９−２の出力Ｍ２は、
信号Ｑ２が位相制御信号Ｘのレベルまで上昇した時点で
立上り信号Ｑ２の立下り時点で立下る断続信号となり、
この立上りに同期して発生ずるＮＡＮＤ素子４０−２の
出力に２によりワンショットマルチ４１−２が駆動され
てパルスｐ２を発生する。この時ＡＮＤ素子↓１人には
遅延素子土主人を介してＮ Ｏｌ’？素子３６への出力
Ｐｅａが入力されているので、該ＡＮＤ素子４２Ａはパ
ルスｐ２を受けると１１１１時に（Ｑ２＝ｘの時点）パ
ルスＮａを発生する。ＡＮＤ素子土叢旦、土１旦からは
、同様に、それぞれＮ ＯＲ信号ヱａｂ、Ｐｂｃの発生
中にパルスｐ２に同期するパルス−Ｎｂ−１Ｎｃを発生
ずる。逆に、位相制御信号Ｘが上昇して信号Ｑ２の最大
値Ｑ２ｍａ ｘを超えた時には、上記反転信号はＨレベ
ルのままであるが、ＯＲ素子３７−２の出力が立下り時
点にＮへＮｌ）素子４０−２の出力が立上るのでパルス
ｐ２が発生し、この時、遅れ電圧■Ｃａが零しベルにあ
ってＮＯＲ信号ｐｃａは消滅するが遅延素子４３Ａがあ
る為、ＡＮＤ素子１１人はＮ ＯＲ信号上−［」２の消
滅時点にパルスｐＪａを発生ずる。This signal Q2 is compared with the phase control signal X in the comparison circuit 39-2, but if the level of the phase control signal Since they intersect, the output M2 of the comparator circuit 39-2 is
When the signal Q2 rises to the level of the phase control signal X, it becomes an intermittent signal that falls when the rising signal Q2 falls,
The one-shot multi 41-2 is driven by the output 2 of the NAND element 40-2 which is generated in synchronization with this rising edge, and generates a pulse p2. At this time, the AND element↓1 person is N Ol'? through the delay element. Since the output Pea to the element 36 is input, when the AND element 42A receives the pulse p2, it generates the pulse Na at 1111 (at the time of Q2=x). Similarly, the AND elements 1 and 1 generate a pulse -Nb-1Nc synchronized with the pulse p2 while the NOR signals ab and Pbc are being generated, respectively. Conversely, when the phase control signal ) Since the output of the element 40-2 rises, a pulse p2 is generated, and at this time, the delay voltage ■Ca drops and reaches the bell, and the NOR signal pca disappears, but because of the delay element 43A, the 11 AND elements A pulse pJa is generated at the time of disappearance of NOR signal -[''2.
Ａ Ｎ ｌ）素子（ユニし土り旦の出力凡を、凡旦につ
いても同様である。The same is true for the output of the A N l) element (uniform and uncircumcised).
このように、パルスＮａ、Ｎｂ、Σ工の発生時点は位相
制御信号Ｘのレベル上昇に伴ってＮ ＯＲ信号旦旦土、
且土工、ｌ瓦旦の立上り時点から立下り時点に向かって
移動するが、信号Ｑ２の最大値Ｑ２ｍａｘを超えた後は
該立下り肋点に固定されてしまうので、位相制御パルス
Ｇ４、Ｇ５、Ｇ６は電源電圧Ｖａ、Ｖｂ、Ｖｃの２１０
度位相から３００度位相の間に必ず１回発生ずる。In this way, the time points at which pulses Na, Nb, and Σ are generated are determined by the NOR signal
In addition, the earthwork moves from the rising point to the falling point of the signal Q2, but after exceeding the maximum value Q2max of the signal Q2, it is fixed at the falling point, so the phase control pulses G4, G5, G6 is 210 of the power supply voltages Va, Vb, and Vc.
It always occurs once between the degree phase and the 300 degree phase.
従って、電源電圧Ｖａ、ｖｂ、Ｖｃの３０〜１２０度、
２１０度〜３００度の間に発生ずる位相制御パルスＧｌ
、Ｇ２、Ｇ３及びＧ４、Ｇ５、Ｇ６は対応するサイリス
タ２１．２２．２３及び２４．２５．２６に供給される
と共にサイリスタ２５．２６．２４．２２．２３．２１
に供給される。Therefore, 30 to 120 degrees of power supply voltage Va, vb, Vc,
Phase control pulse Gl generated between 210 degrees and 300 degrees
, G2, G3 and G4, G5, G6 are supplied to the corresponding thyristors 21.22.23 and 24.25.26 as well as thyristor 25.26.24.22.23.21
supplied to
以上の如く、本発明によれば、電源電圧をΔ結線トラン
スを用いて取出した」二記電源電圧に対する遅れ電圧の
零点位相を基準とし、該零点位相とこの遅れ電圧を９０
度進ませた進み電圧の零点位相との間で１つの位相制御
パルスが発生ずる構成点したことにより、節用な回路構
成であるが、位相制御信号が過大レベルになっても、過
小レベルになっても、サイリスクが順電圧を受りている
間に確実に位相制御パルスが発生ずるので、整流器の欠
相運転を確実に防止し′ζ該整流器の位相１１−制御を
行うことができ、前記した」二］・限リミッタが不要で
あるので、現場据付聞整作業時の操作員の負１１１を軽
減することができる利点がある。As described above, according to the present invention, the zero point phase of the delayed voltage with respect to the power source voltage obtained by using the Δ connection transformer is taken as the reference, and the zero point phase and this delayed voltage are
Since one phase control pulse is generated between the zero point phase of the advanced voltage and the phase of the advanced voltage, the circuit configuration is economical, but even if the phase control signal reaches an excessive level, it will not become an However, since the phase control pulse is reliably generated while the SIRIS is receiving the forward voltage, it is possible to reliably prevent open phase operation of the rectifier and perform phase 11-control of the rectifier. Since a limiter is not required, there is an advantage that the burden on the operator during on-site installation work can be reduced.
第１図は本発明によるサイリスク式３相全波整流器の位
相制御方法の実施例の回路図、第２図は第１図における
位相制御装置の詳細ブロック図、第３図は上記実施例に
おける波形タイムチャーＩ・である。
ｌ〇−電源トランス、２０−・３相全波整流器、２１〜
２６−サイリスク、３〇−位相制御装置、３１−検出ト
ランス、３２Ａ〜３２ Ｃ−位相変換回路、３３Ａ〜３
３Ｃ，３４Ａ〜３４ Ｃ−波形成形回路、３５Ａ〜３５
Ｃ・・・ＡＮＤ素子、３６Ａ〜３（ｉＣ−ＮＯＲ素子、
３７−１．３７−２−・ＯＲ素子、３８−１．３Ｂ−２
−鋸歯状波発生回路、３９−Ｌ３９−２−−・比較回路
、４０−１．４０−２−Ｎ Ａ Ｎ Ｄ素子、４１−１
．４１−２−ワンショットマルチ、４２Ａ−↓１旦−・
ＡＮＤ素子、４３Ａ〜土主旦−遅延素子、４４− リン
グカウンタ。
特許出願人
高周波熱錬株式会社
代理人
弁理士 小林 傅Fig. 1 is a circuit diagram of an embodiment of the phase control method for a thyrisk type three-phase full-wave rectifier according to the present invention, Fig. 2 is a detailed block diagram of the phase control device in Fig. 1, and Fig. 3 is a waveform in the above embodiment. Time chart I. l〇-Power transformer, 20-・3-phase full-wave rectifier, 21-
26-Sirisk, 30-Phase control device, 31-Detection transformer, 32A-32 C-Phase conversion circuit, 33A-3
3C, 34A~34 C-Waveform shaping circuit, 35A~35
C...AND element, 36A-3 (iC-NOR element,
37-1.37-2-OR element, 38-1.3B-2
- Sawtooth wave generation circuit, 39-L39-2-- Comparison circuit, 40-1.40-2-NAND element, 41-1
．． 41-2-One shot multi, 42A-↓1dan-・
AND element, 43A~Doshudan-delay element, 44- Ring counter. Patent applicant Koshuha Netsuren Co., Ltd. Representative patent attorney Fu Kobayashi
Claims (1)
電源トランス出力端子にΔ結線検出トランスを接続して
各相の相間電圧を取り出し、各電圧について、位相変換
回路に導いて９０度進み電圧を生ぜしめ、該９０度進み
電圧と上記相聞電圧をＡＮＤ素子に入力すると共にＮ
ＯＲ素子に供給し、上記ＡＮＤ素子の出力を第１の鋸歯
状波発生回路に、上記ＮＯＲ素子の出力を第２の鋸歯状
波発生回路にそれぞれ入力し、第１の鋸歯状波発生回路
の出力を第１の比較回路で位相制御信号と比較して該位
相制御信号より大である場合に該比較回路から出力を生
ぜしめ、該出力の立上り時点もしくは上記ＡＮＤ素子の
出力の立下り時点に同期するパルスを発生せしめ、該パ
ルスに同期して位相制御パルスを発生させ、また、上記
第２の鋸歯状波発生回路の出力を第２の比較回路で上記
位相制御信号と比較して位相制御信号より大である場合
に該比較回路から出力を生ぜしめ、該出力の立上り時点
及び上記ＮＯＲ素子の出力の立下り時点にそれぞれ同期
するパルスを発生せしめ、該パルスに同期して位相制御
パルスを発生させることを特徴とするサイリスク式３相
全波整流器の位相制御方法。+11 A delta connection detection transformer is connected to the power transformer output terminal of a phase-controlled thyrisk type three-phase full-wave rectifier to extract the phase-to-phase voltage of each phase, and each voltage is led to a phase conversion circuit to generate a 90 degree lead voltage. Then input the 90 degree lead voltage and the phase voltage to the AND element, and
The output of the AND element is inputted to the first sawtooth wave generation circuit, and the output of the NOR element is inputted to the second sawtooth wave generation circuit. The output is compared with a phase control signal in a first comparator circuit, and if the output is larger than the phase control signal, an output is generated from the comparator circuit, and at the time of the rising edge of the output or the falling edge of the output of the AND element. A synchronized pulse is generated, a phase control pulse is generated in synchronization with the pulse, and the output of the second sawtooth wave generation circuit is compared with the phase control signal in a second comparison circuit to control the phase. generates an output from the comparison circuit when the signal is larger than the signal, generates a pulse that is synchronized with the rising edge of the output and the falling edge of the output of the NOR element, and generates a phase control pulse in synchronization with the pulse; A phase control method for a thyrisk type three-phase full-wave rectifier, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17317383A JPS6066672A (en) | 1983-09-21 | 1983-09-21 | Phase controlling method of thyristor type 3-phase full- wave rectifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17317383A JPS6066672A (en) | 1983-09-21 | 1983-09-21 | Phase controlling method of thyristor type 3-phase full- wave rectifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6066672A true JPS6066672A (en) | 1985-04-16 |
| JPH0435992B2 JPH0435992B2 (en) | 1992-06-12 |
Family
ID=15955441
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17317383A Granted JPS6066672A (en) | 1983-09-21 | 1983-09-21 | Phase controlling method of thyristor type 3-phase full- wave rectifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6066672A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4797802A (en) * | 1987-12-03 | 1989-01-10 | Sundstrand Corp. | Multiple phase rectifier with active filter for removing noise in triggering signals and digital phase shift compensator for phase shifting signal passed through |
-
1983
- 1983-09-21 JP JP17317383A patent/JPS6066672A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4797802A (en) * | 1987-12-03 | 1989-01-10 | Sundstrand Corp. | Multiple phase rectifier with active filter for removing noise in triggering signals and digital phase shift compensator for phase shifting signal passed through |
| WO1989005541A1 (en) * | 1987-12-03 | 1989-06-15 | Sundstrand Corporation | Converter for converting a multiple phase variable frequency ac voltage into dc |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0435992B2 (en) | 1992-06-12 |
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