JPS6064535A - Longitudinal balance adjusting circuit - Google Patents
Longitudinal balance adjusting circuitInfo
- Publication number
- JPS6064535A JPS6064535A JP17244683A JP17244683A JPS6064535A JP S6064535 A JPS6064535 A JP S6064535A JP 17244683 A JP17244683 A JP 17244683A JP 17244683 A JP17244683 A JP 17244683A JP S6064535 A JPS6064535 A JP S6064535A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- resistors
- gain
- operational amplifier
- operational amplifiers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M19/00—Current supply arrangements for telephone systems
- H04M19/001—Current supply source at the exchanger providing current to substations
- H04M19/005—Feeding arrangements without the use of line transformers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Signal Processing (AREA)
- Devices For Supply Of Signal Current (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【発明の詳細な説明】
（ａｌ 発明の技術分野
本発明は縦バランス調整回路に係り、特に電話器への給
電回路の縦バランス調整回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a vertical balance adjustment circuit, and more particularly to a vertical balance adjustment circuit for a power supply circuit to a telephone.
（ｂ） 従来技術と問題点
第１図は２線−４線変換回路を含む給電回路の一般的構
成図を示す。(b) Prior Art and Problems FIG. 1 shows a general configuration diagram of a power supply circuit including a 2-wire to 4-wire conversion circuit.
同図に於て、点線内が給電回路を、１は直流帰還回路を
、２は交流帰還回路を、３はハイブリッド回路をそれぞ
れ示す。In the figure, the dotted line indicates a power supply circuit, 1 indicates a DC feedback circuit, 2 indicates an AC feedback circuit, and 3 indicates a hybrid circuit.
又、端子２１及び２２の左側が２線側で、電話器（図示
せず）が接続される。一方、４１！送信端子２３及び４
線受信端子２４の右側は４線側で、４線送信端子２３は
２線側から送られて来た信号を取出し４線側に送出し、
４線受信端子２４は４線側から送られて来た送信信号を
２線側に送出する。Further, the left side of the terminals 21 and 22 is the two-wire side, to which a telephone (not shown) is connected. On the other hand, 41! Transmission terminals 23 and 4
The right side of the line receiving terminal 24 is the 4-line side, and the 4-line transmitting terminal 23 takes out the signal sent from the 2-line side and sends it to the 4-line side.
The 4-wire receiving terminal 24 sends the transmission signal sent from the 4-wire side to the 2-wire side.
第１図に示した各ブロックの動作は次の様である。The operation of each block shown in FIG. 1 is as follows.
端子２１及び２２に加えられた電話器からの信号は互い
に逆相であるから演算増幅器４で２倍の振幅の信号が検
出された後、４線送信端子２３に送られると同時に、低
域ろ波器１１．演算増幅器１２から構成された直流帰還
回路１及び高域ろ波器１０及び演算増幅器１３から構成
された交流帰還回路２を通して給電回路６に加えられる
。Since the signals from the telephones applied to the terminals 21 and 22 are in opposite phases to each other, a signal with twice the amplitude is detected by the operational amplifier 4, and is sent to the 4-wire transmitting terminal 23, at the same time as the low-frequency filter. Wave device 11. It is applied to the power supply circuit 6 through a DC feedback circuit 1 comprising an operational amplifier 12 and an AC feedback circuit 2 comprising a high-pass filter 10 and an operational amplifier 13.
尚、前記の直流帰還回路は端子２１及び２２に接続され
る電話器（図示せず）に流す直流電流を決定し、交流帰
還回路は電話器に接続されるインピーダンスを６００Ω
になる様にしている。The DC feedback circuit described above determines the DC current to be passed through the telephone (not shown) connected to the terminals 21 and 22, and the AC feedback circuit sets the impedance connected to the telephone to 600Ω.
I'm trying to make it happen.
又、ハイブリッド回路３は４線受信端子２４に加えられ
た４線側からの送信信号が演算増幅器５．８及び４を通
った前記の送信信号と、４線受信端子２４に加えられた
送信信号の一部とを加える事に依って４線送信端子２３
から４線側に出るのを防ぐ為のものである。Further, the hybrid circuit 3 receives the transmission signal from the 4-wire side applied to the 4-wire reception terminal 24, the aforementioned transmission signal which has passed through the operational amplifiers 5.8 and 4, and the transmission signal applied to the 4-wire reception terminal 24. By adding a part of the 4-wire transmission terminal 23
This is to prevent it from going out to the 4th line side.
一方、例えば近接した送電線に依って前記の２線に誘導
された同相信号に対して、端子２５から演算増幅器８の
方を見た同相インピーダンスと、端子２６から演算増幅
器９の方を見た同相インピーダンスがそれぞれ例えば１
５０Ωになっていれば演算増幅器４の出力側では互いに
打消され相手側にこの同相信号は送られないが、前記の
同相インピーダンスのバランスが崩れているとそれに対
応する同相信号が増幅器４の出力側に取出され、この同
相信号は相手側と前記２つの帰還回路を通って増幅器５
に加えられる。On the other hand, for a common-mode signal induced into the two wires by, for example, a nearby power transmission line, the common-mode impedance seen from the terminal 25 toward the operational amplifier 8 and the common-mode impedance seen from the terminal 26 toward the operational amplifier 9 are determined. For example, if the common mode impedance is 1
If it is 50Ω, they will cancel each other out on the output side of the operational amplifier 4 and this in-phase signal will not be sent to the other side, but if the above-mentioned common-mode impedance is unbalanced, the corresponding in-mode signal will be sent to the output side of the amplifier 4. This in-phase signal is taken out to the output side and passes through the other side and the two feedback circuits to the amplifier 5.
added to.
ところで、給電回路６の中の演算増幅器７は端子２１及
び２２の同相信号を検出して演算増幅器８及び９に帰還
をかけ同相インピーダンスを前記の１５０Ωに設定する
役目をしているが、この同相インピーダンスの一致の程
度は演算増幅器７と８及び演算増幅器７と９との利得の
一致の程度に依って決まる。By the way, the operational amplifier 7 in the power supply circuit 6 has the role of detecting the common-mode signal at the terminals 21 and 22 and feeding it back to the operational amplifiers 8 and 9 to set the common-mode impedance to the aforementioned 150Ω. The degree of common-mode impedance matching is determined by the degree of matching of gains between operational amplifiers 7 and 8 and operational amplifiers 7 and 9.
従って、縦バランスを良くする為に（よ２つの同相イン
ピーダンスを出来るだけ一致させる事がａ・要であり、
その為には演算増幅器８及び９の利（ｑ決定用の抵抗器
を調整する事が不可欠である。Therefore, in order to improve the vertical balance, it is important to match the two common mode impedances as much as possible.
For this purpose, it is essential to adjust the resistor for determining the efficiency of operational amplifiers 8 and 9 (q).
第２図は第１図に示した給電回路６のより詳細な回路図
を示す。FIG. 2 shows a more detailed circuit diagram of the power supply circuit 6 shown in FIG.
同図に於て、演算増幅器８の利得ば抵抗器１７−３とＲ
−１の値の比で、演算増幅器９の利得は同しく抵抗器Ｒ
−５とＲ−４の値の比でそれぞれ決まる。In the same figure, the gain of operational amplifier 8 is determined by resistor 17-3 and R.
-1 value, the gain of operational amplifier 9 is also equal to resistor R
Each is determined by the ratio of the values of -5 and R-4.
一方、給電回路６をＬＳＩ化する場合調整を要する抵抗
器は外付けにする必要があるので、ＬＳＩ内の抵抗器と
外付けの抵抗器の温度特性を揃えなければならない。し
かし、この様な、ことは一般には不可能なので、利得を
決める抵抗器はすべて外イ１けにせざるを得ない。On the other hand, when the power supply circuit 6 is integrated into an LSI, the resistors that require adjustment must be externally attached, so the temperature characteristics of the resistors inside the LSI and the external resistors must be made the same. However, since this is generally impossible, all the resistors that determine the gain have to be used externally.
即ち抵抗器Ｒ−１を外付けにすると、それと対をなす抵
抗器Ｒ−３も、又演算増幅器８と９の利得特性を揃える
為に抵抗器Ｒ−４及びＲ−５も外付けにせざるを得なか
った。In other words, if resistor R-1 is externally connected, the paired resistor R-3 must also be externally connected, and in order to match the gain characteristics of operational amplifiers 8 and 9, resistors R-4 and R-5 must also be externally connected. I didn't get it.
その為に給電回路をＬＳＩ化する場合、外付は部品が増
えると云う問題があった。Therefore, when converting the power supply circuit into an LSI, there is a problem in that the number of external components increases.
（Ｃ） 発明の目的
本発明は上記従来技術の問題に鑑みなされたものであっ
て、調整用抵抗器１本のみを外付けにしたＬＳＩ化され
た縦バランス調整回路を提供する事を目的としている。(C) Purpose of the Invention The present invention has been made in view of the problems of the prior art described above, and its purpose is to provide an LSI-based vertical balance adjustment circuit in which only one adjustment resistor is externally attached. There is.
（ｄ） 発明の構成
上記発明の目的は、２線の同相信号を検出する検出手段
と該検出手段からの出力を２つの演算増幅器に帰還して
同相インピーダンスを設定する手段を含むＬＳＩ化され
た給電回路に於て、該２つの演算増幅器の何れか１つの
演算増幅器の帰還利得を決定する第１及び第２の抵抗器
のうち第２の抵抗器に該抵抗器の値の約１０倍の値を持
つ抵抗器を外部から並列接続した事を特徴とする縦バラ
ンス調整回路を提供する事に依り達成される。(d) Structure of the Invention The object of the invention is to provide an LSI which includes a detection means for detecting a two-wire in-phase signal and a means for feeding back the output from the detection means to two operational amplifiers to set a common-mode impedance. In the power supply circuit, the second resistor of the first and second resistors that determines the feedback gain of one of the two operational amplifiers has a value approximately 10 times that of the resistor. This is achieved by providing a vertical balance adjustment circuit characterized by externally connecting resistors having a value of .
＋１４１ 発明の実施例 第３図は本発明の一実施例の概略の接続図である。+141 Examples of the invention FIG. 3 is a schematic connection diagram of an embodiment of the present invention.
図中１．７，８及び９はそれぞれ演算増幅器を、２５〜
２９はそれぞれ端子を、Ｒ−１〜Ｒ−１２はそれぞれ抵
抗器を示す。In the figure, 1.7, 8, and 9 are operational amplifiers, and 25 to 9 are respectively operational amplifiers.
29 each represents a terminal, and R-1 to R-12 each represent a resistor.
尚、第２図と同一の記号は同一の部分を示し、本発明の
部分は点線で囲った部分である。Note that the same symbols as in FIG. 2 indicate the same parts, and the parts of the present invention are surrounded by dotted lines.
これらの部品は概路次の様に接続されている。These parts are connected as shown below.
端子２５は抵抗器Ｒ−６．演算増幅器８．抵抗器Ｒ−７
を介して端子２７と、端子２６は同じく抵抗器Ｒ−８．
演算増幅器９．抵抗器Ｒ−９を介して端子２８と接続さ
れる。Terminal 25 is connected to resistor R-6. Operational amplifier8. Resistor R-7
via terminal 27, and terminal 26 is also connected to resistor R-8.
Operational amplifier9. It is connected to terminal 28 via resistor R-9.
又、端子２５と２６を接続する２本の直列抵抗器Ｒ−１
０及びＲ−１１の共通の接続点は、演算増幅器７を介し
て抵抗器Ｒ−ｉとＲ−２との並列接続抵抗を介して演算
増幅器８の一端子及び抵抗器Ｒ−４を介して演算増幅器
９の一端子にそれぞれ接続される。Also, two series resistors R-1 connect terminals 25 and 26.
The common connection point of 0 and R-11 is connected to one terminal of the operational amplifier 8 through the parallel connection of resistors R-i and R-2 through the operational amplifier 7 and through the resistor R-4. Each is connected to one terminal of the operational amplifier 9.
尚、演算増幅器７の一端子は抵抗器Ｒ−１２を介して端
子２９に接続される。Note that one terminal of the operational amplifier 7 is connected to a terminal 29 via a resistor R-12.
同図に於て、抵抗器１？−１，Ｒ−３，Ｒ−４，Ｒ−５
はＬＳＩ内部に構成され抵抗器Ｒ−２を外付けとする。In the same figure, resistor 1? -1, R-3, R-4, R-5
is configured inside the LSI, and the resistor R-2 is attached externally.
この時、抵抗器Ｒ−２は抵抗器Ｒ−１の８倍に選んであ
り、演算増幅器８の利得に対する感度は抵抗器１１−１
の約１／８である。つまり、演算増幅器８と９の利得は
殆ど内蔵の抵抗器Ｒ１１，Ｒ−３，Ｒ−４，Ｒ−５で決
まる。At this time, resistor R-2 is selected to be eight times as large as resistor R-1, and the sensitivity to the gain of operational amplifier 8 is determined by resistor 11-1.
It is about 1/8 of that. That is, the gains of the operational amplifiers 8 and 9 are mostly determined by the built-in resistors R11, R-3, R-4, and R-5.
従って外付けの調整抵抗器Ｒ−２と内蔵の抵抗器の温度
係数が違ったとしても、全体の利得への影響は殆どない
。Therefore, even if the temperature coefficients of the external adjusting resistor R-2 and the built-in resistor are different, this has almost no effect on the overall gain.
第４図は具体例を示す。FIG. 4 shows a concrete example.
今抵抗器Ｒ−１が２２．５にΩ、１１−２が１８０にΩ
の時その並列抵抗器Ｒｔの値は２０ ＫΩで抵抗器Ｒ−
４と同じ値になる様にしである。この時抵抗器Ｒ−２の
値を変化させた時の並列抵抗器Ｒｔの値の変化を示した
ものが第４図である。同図から判る様に並列抵抗器Ｒ１
の値の変化は約ｌ／１０になっている。Now resistor R-1 is 22.5Ω, and resistor 11-2 is 180Ω.
When the value of the parallel resistor Rt is 20 KΩ, the value of the resistor R-
The value is set to be the same as 4. FIG. 4 shows the change in the value of the parallel resistor Rt when the value of the resistor R-2 is changed at this time. As you can see from the figure, parallel resistor R1
The change in value is approximately 1/10.
（ｆ） 発明の詳細
な説明した様に本発明によれば、演算増幅器の利得を決
定する抵抗器をＬＳＩ内部に構成し、調整抵抗器を一本
だけ外付けにする事により給電回路の縦バランスを温度
特性を損なう事なく調整する事が出来る。(f) As described in detail, according to the present invention, the resistor that determines the gain of the operational amplifier is configured inside the LSI, and only one adjustment resistor is attached externally, thereby reducing the vertical Balance can be adjusted without impairing temperature characteristics.
第１図は２線／４線変換機能を含んだ給電回路の一般的
構成例を、第２図は給電回路図の従来例を、第３図は本
発明の一実施例を、第４図は本発明の詳細な説明する為
の図をそれぞれ示す。
図中、７．８及び９はそれぞれ演算増幅器を、Ｒ−１〜
Ｒ−１２はそれぞれ抵抗器を、２５〜２９はそれぞれ端
子を示す。
菓２図
第３図
第４区
／ｌρ ／７ρ ／８ρ ／ｙρ ２ρρＡ？ｚ ＫΩFig. 1 shows a general configuration example of a power supply circuit including a 2-wire/4-wire conversion function, Fig. 2 shows a conventional example of a power supply circuit diagram, Fig. 3 shows an embodiment of the present invention, and Fig. 4 2A and 2B respectively show diagrams for explaining the present invention in detail. In the figure, 7.8 and 9 indicate operational amplifiers, R-1 to
R-12 each represents a resistor, and 25 to 29 each represent a terminal. Figure 2 Figure 3 District 4 /lρ /7ρ /8ρ /yρ 2ρρA? z KΩ
Claims (1)
の出力を２つの演算増幅器に帰還して同相インピーダン
スを設定する手段を含むＬＳＩ化された給電回路に於て
、ｓｌつの演算増幅器の何れか１つの演算増幅器の帰還
利得を決定する第１及び第２の抵抗器のうち第２の抵抗
器に該第２の抵抗器の値の約１０倍の値を持つ抵抗器を
外部から並列接続した事を特徴とする縦バランス調整回
路。In an LSI power supply circuit including a detection means for detecting a two-wire common-mode signal and a means for feeding back the output from the detection means to two operational amplifiers to set a common-mode impedance, sl operational amplifiers are used. A resistor having a value approximately 10 times the value of the second resistor is externally connected to the second resistor of the first and second resistors that determine the feedback gain of any one of the operational amplifiers. A vertical balance adjustment circuit characterized by parallel connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17244683A JPS6064535A (en) | 1983-09-19 | 1983-09-19 | Longitudinal balance adjusting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17244683A JPS6064535A (en) | 1983-09-19 | 1983-09-19 | Longitudinal balance adjusting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6064535A true JPS6064535A (en) | 1985-04-13 |
Family
ID=15942128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17244683A Pending JPS6064535A (en) | 1983-09-19 | 1983-09-19 | Longitudinal balance adjusting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6064535A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01202972A (en) * | 1988-02-09 | 1989-08-15 | Oki Electric Ind Co Ltd | Transmission characteristic temperature compensation method |
-
1983
- 1983-09-19 JP JP17244683A patent/JPS6064535A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01202972A (en) * | 1988-02-09 | 1989-08-15 | Oki Electric Ind Co Ltd | Transmission characteristic temperature compensation method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2898165B2 (en) | Hybrid circuit | |
| US6218872B1 (en) | Line driver with output impedance synthesis | |
| JPH0669834A (en) | Two-wire/four-wire converter | |
| JPS5816782B2 (en) | Telephone transmitter/receiver circuit | |
| JPS6041909B2 (en) | Telephone communication network | |
| JPS6064535A (en) | Longitudinal balance adjusting circuit | |
| CA1078536A (en) | Bilateral voice-signal controller for use in the two-wire portion of the telephone circuit | |
| US6795495B2 (en) | Line driver with output impedance synthesis | |
| US4500755A (en) | Electric hybrid circuits | |
| JPS59135961A (en) | Speech signal suppressing circuit for telephone set | |
| EP1089450B1 (en) | Telephone line interface circuit | |
| JPS5912638A (en) | Impedance synthesis type line circuit | |
| JPH07288577A (en) | Telephone set | |
| KR20040032781A (en) | Bridge circuit to suppress echoes in communication devices | |
| JPH0736196B2 (en) | Summing amplifier with complex weighting factors and interface with such summing amplifier | |
| JPS63200623A (en) | Automatic hybrid circuit | |
| JPH033009Y2 (en) | ||
| AU681169B2 (en) | Line termination circuit | |
| JPS60112348A (en) | Anti-side tone circuit | |
| JPS6160021A (en) | Electronic hybrid circuit | |
| RU1803983C (en) | Device for suppressing local effect of telephone set | |
| JP3031518B2 (en) | Sidetone circuit | |
| JP2646669B2 (en) | Electronic hybrid circuit | |
| JPS6146629A (en) | Ac inducing noise eliminating circuit | |
| JPH03231520A (en) | Two-wire/four-wire conversion circuit |