JPS6062119A - Semiconductor wafer - Google Patents
Semiconductor waferInfo
- Publication number
- JPS6062119A JPS6062119A JP58170168A JP17016883A JPS6062119A JP S6062119 A JPS6062119 A JP S6062119A JP 58170168 A JP58170168 A JP 58170168A JP 17016883 A JP17016883 A JP 17016883A JP S6062119 A JPS6062119 A JP S6062119A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- mark
- sections
- layer
- grooves
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 29
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 239000010408 film Substances 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 239000002184 metal Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
- G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、各種の半導体装置を製造する際に用いられ
る半導体ウェハに関し、イ☆１ｈ′合せマークの並行す
る輪郭部分をいずれも溝で構成したことにより高精度の
位置合せを可能にしたものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor wafers used in manufacturing various semiconductor devices, and the parallel outline portions of the A☆1h' alignment marks are all formed with grooves, thereby achieving highly accurate positioning. This makes it possible to combine
一般に、半導体ウェハとレチクル（又はホトマスク）と
の位置合せは、ウェハに設けた位置合せマークとレチク
ル等に設けた位置合せマークとンパターン比較して行な
われている。ウェハ表ｍ１に設けられる位置合せマーク
としては、細長形状のもの、方形状のもの、十字状のも
の、逆ハの字状のものなど種々のものが提案されている
が、いずれも単純な凸状又は凹状のパターンを有し、そ
の輪郭部分は断面が段差状をなしている。Generally, alignment between a semiconductor wafer and a reticle (or photomask) is performed by comparing alignment marks provided on the wafer with alignment marks provided on the reticle or the like. Various types of alignment marks have been proposed to be provided on the wafer surface m1, such as elongated ones, rectangular ones, cross-shaped ones, and inverted C-shaped ones, but all of them are simple convex ones. It has a shaped or concave pattern, and its contour portion has a step-like cross section.
ｉｌ 図（−１〜（ｄ）は、従来の種々のウェハマーク
の断面構造を示すもので、（ａｌは、シリコン等からな
る半導体ウェハ１０の表面を選択酸化してシリコンオキ
サイドからなる絶縁膜１２ヲ形成し、その上にポリシリ
コン層１４を堆積して凹状パターンを形成した例、（ｂ
）は、ウェハ１００表面に（、）の場合と同様にして絶
縁膜１２及びポリシリコン層１４により凸状パターンを
形成した例、（ｃｌは、ウェハ１００表面に絶縁膜１２
ヲ選択的に配置すると共にその上にＡＡ等の金属層１６
ヲ被着して凹状パターンを形成した例、（ｄｉは、（ｃ
）の場合と同様にして絶縁膜１２及び金属層１６によシ
凸状パターンを形成した例である。il Figures (-1 to (d) show cross-sectional structures of various conventional wafer marks; An example in which a concave pattern is formed by depositing a polysilicon layer 14 on it,
) is an example in which a convex pattern is formed on the surface of the wafer 100 by the insulating film 12 and the polysilicon layer 14 in the same manner as in the case of (, );
A metal layer 16 such as AA is placed thereon selectively.
In an example where a concave pattern is formed by depositing (di), (c
This is an example in which a convex pattern is formed on the insulating film 12 and the metal layer 16 in the same manner as in the case of ).
上記した（ａｌ〜（ｄｌのいずれの例においても、ウェ
ハマークの並行する輪郭部分は断面が段差状をなしてい
る。、このようなウェハな用いて集積回路装置等を製作
する場合、ウェハ上面にホトレジストを回転塗布法によ
シ被着してホトレジスト層１８を形成した後、ウェハの
マーク及びレチクル等のマークをパターン比較して位置
合せン行ない、しかる後露光処理によシレチクル等の回
路パターンをホトレジスト層１８に転写する。In any of the examples of (al to (dl) described above, the parallel outline portions of the wafer marks have a step-like cross section. When manufacturing integrated circuit devices etc. using such wafers, the top surface of the wafer After forming a photoresist layer 18 by applying photoresist by spin coating, the marks on the wafer and the marks on the reticle are compared and aligned, and then exposed to form the circuit pattern on the reticle. is transferred to the photoresist layer 18.
このような工程においては、ウェハとレチクル（又はホ
トマスク）とを高精度で位置合せすることが要求される
が、上記した従来のウェハマーク構造では十分な位置合
せ精度が得られない不都合があった。すなわち、ホトレ
ジスト乞回転塗布した場合、ホトレジスト層１８は均一
な厚さで下地の凹凸をおおうのではなく、広い領域にわ
たりゆるやかに厚さが変化する。特にマーク設置個所に
おいては、第１図に示すように、塗布条件、ウェハ上の
マーク位置及び方向等によシホトレリスト層１８の厚さ
が変化し、マーク中心Ａ −Ａ’ に関して左右の段差
部分で非対称的な変化を示すことがある。In such a process, it is required to align the wafer and reticle (or photomask) with high precision, but the conventional wafer mark structure described above has the disadvantage that sufficient alignment accuracy cannot be obtained. . That is, when the photoresist layer 18 is spin-coated, the photoresist layer 18 does not cover the irregularities of the base with a uniform thickness, but the thickness changes gradually over a wide area. In particular, at the mark installation location, as shown in FIG. 1, the thickness of the photoresist layer 18 changes depending on the coating conditions, the mark position and direction on the wafer, etc. May exhibit asymmetrical changes.
このようにホトレジスト層の厚さが非対称的な変化ケ示
していると、ウェハ上のポリシリコン、シリコンナイト
ライド、シリコンオキサイド等の薄膜とホトレジスト層
との界面からの反射光が干渉し合うため位置合゛せ観察
窓において良好なマーク像が得られず、マーク合せ精度
が低下する。例えば、第２図に示すようにある種の縮少
露光装置ヲ用いてウェハ上のマークんとレチクル上のマ
ークｎとを合せようとすると、同図（ａ）に示すように
左右の段差に対応する部分２ＯＡ及び２０Ｂの幅ｄ１及
びｄｌが異なったシ、同図（ｂ）に示すように左右の段
差に対応する部分２ＯＡ及び２０Ｂが複数に分れたシす
ることがある。また、ｄｌ 及びｄｌ の値そのものも
要求される合せ精度を得るために十分小さいものではな
いつ
この発明の目的は、上記した従来技術の問題点を解決す
ることのできる功規な位置合せマーク構造ン有する半導
体ウェハな提供することにある。If the thickness of the photoresist layer exhibits an asymmetrical change like this, the light reflected from the interface between the photoresist layer and the thin film of polysilicon, silicon nitride, silicon oxide, etc. on the wafer will interfere with each other. A good mark image cannot be obtained in the alignment observation window, and the mark alignment accuracy decreases. For example, when trying to align the mark on the wafer with the mark n on the reticle using a type of reduction exposure device as shown in Figure 2, there is a difference in level between the left and right sides as shown in Figure 2(a). If the corresponding portions 2OA and 20B have different widths d1 and dl, the portions 2OA and 20B corresponding to the left and right steps may be divided into a plurality of parts, as shown in FIG. Furthermore, the values of dl and dl themselves are not small enough to obtain the required alignment accuracy.An object of the present invention is to develop an effective alignment mark structure that can solve the problems of the prior art described above. Our goal is to provide semiconductor wafers with
この発明による半導体ウェハは、位置合せマークの並行
する輪郭部分をいずれも溝で構成したことを特徴どする
ものである。すなわち、これを第３図について説明する
と、従来は同図（ａｌに示すようにマーク中心Ａ−Ａ’
の左右の輪郭部分がいずれも段差で構成されていたの
に対し、この発明では同図（ｔ、ｌに示すようにマーク
中心Ａ −Ａ’ の左右の輪郭部分がいずれも断面凹状
の溝で構成嘔れる。The semiconductor wafer according to the present invention is characterized in that the parallel contour portions of the alignment marks are all formed by grooves. That is, to explain this with reference to FIG. 3, conventionally, as shown in FIG.
Whereas the left and right contours of the mark were both formed by steps, in this invention, the left and right contours of the mark center A-A' are both grooves with a concave cross section, as shown in the same figure (t and l). The composition is disgusting.
この場合において、各港の幅Ｗ及び深婆りをいずれも適
当に小さく設定すると、ホトレジスト層１８ン前述のよ
うに形成した際にその上面がほぼ平担になシ、マーク中
心Ａ −Ａ’ に関して左右の溝部分でホトレジスト層
１８の厚さがほぼ等しくなる。In this case, if the width W and depth of each port are set appropriately small, when the photoresist layer 18 is formed as described above, its upper surface will be almost flat, and the mark center A-A' The thickness of the photoresist layer 18 is approximately equal in the left and right groove portions.
このため、第２図に示Ｌ７たｄｌ 及びｄｌ の値はほ
ぼ等しくなシ、マーク像の端縁部分２０Ａ及び２０Ｂは
分れることなく、しかもｄｌ 及びｄｌ の値そのもの
も十分不埒くすることができる。従って、マーク合せ精
度乞大幅に向上させることができる。Therefore, the values of dl and dl shown in FIG. can. Therefore, the accuracy of mark alignment can be greatly improved.
第４図（ａ）〜（ｄ）は、いずれも第３図（ｂ）の構造
を具体化した例ン示すもので、第４図（ａ）及び（ｂ）
は溝の幅Ｗ及び深さＤＹ小１くした例でろシ、Ｉａ１図
（ｅ）及び（ｄ）溝の幅Ｗを小さくした例である。Figures 4(a) to (d) all show examples that embody the structure of Figure 3(b), and Figures 4(a) to (b)
Figures (e) and (d) are examples in which the width W and depth DY of the groove are reduced by 1. FIGS.
第４図において、（ａ）は、シリコン等からなる半道伏
つェノ１１０の弗面ン、−＋１釈陸４）−１，てシ１」
コンオキサイドからなる絶縁膜１２ヲ形成し、その上に
ポリシリコン層１４をＣＶＤ （ケミカル◆イーパー・
デポジション）法によシ堆積した例、（ｂ）は、ウエノ
為１０の表面にＫＯＨ等ン用いた異方性エツチングによ
多断面Ｖ字状の溝を形成した後、表面に絶縁膜１２を形
成した例、（Ｃ）は、ウエノ１０の一面に絶縁膜１２ヲ
形成した後、これに異方性エツチングにより断面凹状の
溝を形成し、その上にポリシリコン層１４”ａ？ｃＶＤ
法により堆積した例、（ｄ）は、ウェハ１００表面に
絶縁膜１２ヲ形成した後、これに異方性エツチングによ
り断面凹状の溝を形成し、その上にＡｄ等の金属層１６
Ｙスパツタ法によシ被着した例である。In Figure 4, (a) is a half-faced 110 made of silicon, etc.
An insulating film 12 made of conoxide is formed, and a polysilicon layer 14 is deposited on it using chemical vapor deposition (CVD).
(b) shows an example in which multi-sectional V-shaped grooves are formed on the surface of the wafer film 10 by anisotropic etching using KOH or the like, and then the insulating film 12 is deposited on the surface. In (C), an insulating film 12 is formed on one surface of the wafer 10, a groove with a concave cross section is formed by anisotropic etching, and a polysilicon layer 14''a?cVD is formed on the insulating film 12.
(d) is an example in which an insulating film 12 is formed on the surface of a wafer 100, and then grooves with a concave cross section are formed by anisotropic etching, and a metal layer 16 such as Ad is deposited on the insulating film 12.
This is an example of coating by the Y sputter method.
上記した（ａ）〜（ｄ）のいずれの例においても、ウェ
ハマークの輪郭部分は断面が凹状ンなしており、回転塗
布法によりマークをおおってホトレジスト層１８Ｙ形成
すると、その上面は第３図（ｂ）Ｋついて述べたと同様
にほぼ平担になるものである。In any of the examples (a) to (d) described above, the outline portion of the wafer mark has a concave cross section, and when the photoresist layer 18Y is formed covering the mark by the spin coating method, the upper surface thereof is as shown in FIG. (b) As mentioned for K, it is almost flat.
以上の門うに、この発明によれば、ウェハマークの並行
する輪郭部分をいずれも溝で構成したので、ホトレジス
）Ｙ塗布した際にその上面がほば平担化され、良好なマ
ーク像が得られる。このため、高精度のウェハ位置合ぜ
を達成することができる。As described above, according to the present invention, since the parallel outline portions of the wafer mark are all formed by grooves, when the photoresist (Y) is applied, the upper surface is almost flattened, and a good mark image can be obtained. It will be done. Therefore, highly accurate wafer alignment can be achieved.
第１図（ａ）〜（ｄｌは、従来の種々の位置合せマーク
構造乞示すウェハ断面図、
第２図（＆）及び（ｂ）は、位置合せ観察窓におけるＶ
チクル及びウェハのマーク合せ状況を示す平面図、第３
図（ａ）及び（ｂ）は、同一形状の位置合せマークにつ
いて従来構造及びこの発明の構造を対比して示すウェハ
断面図、
第４図（，１〜（ｄ）は、この発明による柚々の位置合
せマーク構造を示すウェハ断面図である。
１０・・・半導体ウェハ、１２・・・絶縁膜、１４・・
・ポリシリコン層、１６・・・金属層、１８・・・ホト
レジスト層。
出願人 日本楽器製造株式会社
代理人 弁理士 伊沢敏昭
第１図
第１図
第２図
第３図
Ａ
第４図FIGS. 1(a) to (dl) are wafer cross-sectional views showing various conventional alignment mark structures. FIGS. 2(&) and (b) are wafer cross-sectional views showing various conventional alignment mark structures.
Plan view showing the mark alignment situation of tickle and wafer, 3rd
Figures (a) and (b) are wafer cross-sectional views showing the conventional structure and the structure of the present invention for alignment marks of the same shape. 10 is a cross-sectional view of a wafer showing an alignment mark structure. 10... Semiconductor wafer, 12... Insulating film, 14...
- Polysilicon layer, 16...metal layer, 18... photoresist layer. Applicant Nippon Musical Instruments Co., Ltd. Agent Patent Attorney Toshiaki Izawa Figure 1 Figure 1 Figure 2 Figure 3 A Figure 4
Claims (1)
て、前記位置合せマークの並行する輪郭部分ケいずれも
溝で構成したこと’＆ ％徴とする半導体ウェハ。A semiconductor wafer having an alignment mark provided on its surface, wherein all parallel contour portions of the alignment mark are constituted by grooves.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58170168A JPS6062119A (en) | 1983-09-14 | 1983-09-14 | Semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58170168A JPS6062119A (en) | 1983-09-14 | 1983-09-14 | Semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6062119A true JPS6062119A (en) | 1985-04-10 |
Family
ID=15899941
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58170168A Pending JPS6062119A (en) | 1983-09-14 | 1983-09-14 | Semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6062119A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01272117A (en) * | 1988-04-23 | 1989-10-31 | Sony Corp | Semiconductor device |
| EP0640880A1 (en) * | 1993-08-18 | 1995-03-01 | AT&T Corp. | Alignment of wafers for lithographic patterning |
-
1983
- 1983-09-14 JP JP58170168A patent/JPS6062119A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01272117A (en) * | 1988-04-23 | 1989-10-31 | Sony Corp | Semiconductor device |
| EP0640880A1 (en) * | 1993-08-18 | 1995-03-01 | AT&T Corp. | Alignment of wafers for lithographic patterning |
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