JPS6060764A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6060764A JPS6060764A JP16812983A JP16812983A JPS6060764A JP S6060764 A JPS6060764 A JP S6060764A JP 16812983 A JP16812983 A JP 16812983A JP 16812983 A JP16812983 A JP 16812983A JP S6060764 A JPS6060764 A JP S6060764A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- semiconductor device
- substrate
- diffusion
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 25
- 230000015556 catabolic process Effects 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 6
- 238000010884 ion-beam technique Methods 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 2
- 230000003068 static effect Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 1
- 230000005611 electricity Effects 0.000 abstract 1
- 230000009993 protective function Effects 0.000 abstract 1
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 1
- 230000006378 damage Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は集積回路の信頼性向上にかかわり、特に静電気
の放電による集積回路の破壊を防ぐ半導体装置に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to improving the reliability of integrated circuits, and more particularly to a semiconductor device that prevents destruction of integrated circuits due to electrostatic discharge.
従来集積回路は、拡散層の接合降服あるいは、ＭＯ８形
トランジスタのドレイン接合降服により静電気の放電に
よる集積回路の破壊を防いでいた。Conventionally, integrated circuits have been prevented from being destroyed by electrostatic discharge by junction breakdown of a diffusion layer or drain junction breakdown of an MO8 transistor.
しかし、上記拡散層の接合おるいはドレイン接合の降服
電圧が高いと、接合部で発生される局所的な電力により
接合破かいがおこつｆｃｔ）、ＭＯＳトランジスタのゲ
ート絶縁膜が破壊されるという欠点があった。However, if the breakdown voltage of the junction or drain junction of the above diffusion layer is high, the local power generated at the junction tends to break the junction (fct), and the gate insulating film of the MOS transistor is destroyed. There were drawbacks.
本発明の目的は、上記欠点を局所的な不純物形成により
、集積回路の特性をかえることなく改善する半導体装置
を提供することである。An object of the present invention is to provide a semiconductor device that improves the above-mentioned drawbacks by locally forming impurities without changing the characteristics of the integrated circuit.
従来の不純物層の形成方法としては、熱拡散法又はイオ
ン打込み法等が一般的に用いられておりこの様な方法で
は、ホトレジストの加工寸法の限界により拡散層の微細
化が制限されていた。例えば今日一般的に用いられてい
る技術においては、３μｍＸ３μｍ がその最小寸法で
あり、これ以下の平面寸法の拡散層は形成できずまた必
らずホトレジストの加工の工程を必要とするため、特別
な拡散工程を追加すると製造コストが高くなる欠点があ
った。本発明は、イオンビームを用いた不純物のＳｌ中
への注入を用いることによ如１μｍレベル又は１μｍ以
下の幅をもつ不純物層をホトレジストの加工を必要とせ
ず、微細拡散層が形成できること金利用するものである
。この様な微細拡散層の形成は上記説明により従来技術
では不可能であることは明白である。As a conventional method for forming an impurity layer, a thermal diffusion method, an ion implantation method, or the like is generally used, and in such methods, miniaturization of the diffusion layer is restricted due to the limitations of the processing dimensions of the photoresist. For example, in the technology commonly used today, the minimum dimensions are 3 μm x 3 μm, and it is impossible to form a diffusion layer with a planar dimension smaller than this, and it necessarily requires a photoresist processing process, so a special process is required. Adding a diffusion step has the disadvantage of increasing manufacturing costs. The present invention provides that a fine diffusion layer can be formed by implanting impurities into Sl using an ion beam to form an impurity layer with a width of 1 μm level or less than 1 μm without the need for photoresist processing. It is something to do. From the above explanation, it is clear that formation of such a fine diffusion layer is impossible with the prior art.
他方、素子の微細化にともない静電破壊に対する集積回
路の強さは低下する一方であり、これに対する有効な方
策は見当らない状態である。本発明ハ主に上記イオンビ
ームによる微細拡散層の形成により入出力ピンと低抵抗
で電気的に結合された拡散層の降服電圧を精度よく制御
し、静電気の放電による集積回路の破壊を防ぐことを基
本的な原理とする。On the other hand, with the miniaturization of elements, the strength of integrated circuits against electrostatic discharge damage continues to decline, and no effective countermeasures have yet been found. The main objective of the present invention is to precisely control the breakdown voltage of the diffusion layer electrically connected to the input/output pins with low resistance by forming a fine diffusion layer using the ion beam, thereby preventing damage to the integrated circuit due to electrostatic discharge. This is the basic principle.
第１図は本発明の実施例を示すものである。第１図面は
平面図、０はＡ−Ａ’断面図、（ＱはＢ−Ｂ′断面図、
■はＣ−Ｃ’断面図を示す。１は集積回路チツ六２はＡ
ｔ等の良導電材よりなる入出力パッド及びそれにつなが
る配線、３はｎ９拡散層４と上記２とを電気的に接続す
る為のスルーホール、４及び５はソース又はドレインｎ
９拡散層、６はゲート電極、７は微細ｐ００拡散、８は
ｐ形基板、９は層間絶縁膜、１０はｓｉ酸化膜である。FIG. 1 shows an embodiment of the invention. The first drawing is a plan view, 0 is an AA' sectional view, (Q is a BB' sectional view,
(2) shows a CC' cross-sectional view. 1 is an integrated circuit 62 is A
3 is a through hole for electrically connecting the n9 diffusion layer 4 and the above 2, 4 and 5 are source or drain n.
9 is a diffusion layer, 6 is a gate electrode, 7 is a fine p00 diffusion, 8 is a p-type substrate, 9 is an interlayer insulating film, and 10 is a Si oxide film.
本実施例にｄいてはＢ−Ｂ’断面部分の４′と８との接
合耐圧は、比較的太きく、例えばケート長３μｍ、ｆｉ
”拡散深さ０．４μｍの構造においてはドレイン耐圧は
約２０Ｖ程度になる。他方ｃ−ｃ’断面図における４′
と８及び７との接合耐圧は７′のｐ型不純物濃度を１０
１７〜１０１９程度に制御することにより６Ｖ〜１５Ｖ
程度に容易設定することができる。したがって本実施例
では接合耐圧を７′を形成することにより２０Ｖ以下の
比較的広い範囲で制御することができ、例えば５Ｖの電
源を使用する場合には接合耐圧は８ｖ程効果を大きくす
ることができる。なお本実施例においては、ｐ＋拡散層
７及び７′の幅は、イオンビームの走査によ９１μｍ以
下の値に容易にすることができ、ゲート６の幅に対して
十分小さな値となるため ７，７／の注入による回路特
性の変化は十分無視できるものでゲート幅の寸法を変更
する等の余分の集積回路設計変更を必要としない。In this embodiment, the junction breakdown voltage between 4' and 8 in the B-B' cross section is relatively large, for example, the gate length is 3 μm, the fi
``In a structure with a diffusion depth of 0.4 μm, the drain breakdown voltage is approximately 20V.On the other hand, 4' in the cc' cross-sectional view
The junction breakdown voltage between and 8 and 7 is 7' p-type impurity concentration 10
6V to 15V by controlling to about 17 to 1019
Can be easily set up to a certain degree. Therefore, in this embodiment, by forming 7', the junction breakdown voltage can be controlled over a relatively wide range of 20V or less. For example, when using a 5V power supply, the effect of the junction breakdown voltage can be increased to 8V. can. In this example, the width of the p+ diffusion layers 7 and 7' can be easily reduced to a value of 91 μm or less by scanning with an ion beam, which is a sufficiently small value with respect to the width of the gate 6. , 7/ is sufficiently negligible and does not require any additional changes in the integrated circuit design such as changing the gate width dimension.
すなわち従来の製品に本発明を実施することにより、製
品の性能をかえることなく静電破壊に対する強度を大き
くすることができるという利点のあることは明らかであ
る。なお一度４′−７′間の接合降服がおきると、基板
抵抗の効果により４′−５′間に電流の通路ができるこ
とは公知であり、４ ／ ５ ／間の接合が熱的に破か
いされることはない。That is, it is clear that by applying the present invention to a conventional product, there is an advantage that the strength against electrostatic discharge damage can be increased without changing the performance of the product. It is well known that once junction breakdown occurs between 4' and 7', a current path is created between 4' and 5' due to the effect of substrate resistance, and the junction between 4' and 5' is thermally ruptured. It will not be done.
第２図は他の実施例を示すものである。第２図面は平面
図、■はＡ−Ａ’断面図、（ＱはＢ−Ｂ’断面図である
。ここで４“は通常静電破かい防止の為に用いられるｎ
０拡散層である。本実施例では微細ｐ＋層が４“をクロ
スする様に形成されており、第１図の実施例と同様、
＋ ｐ ＋間の接合耐圧を低くして静電耐圧を向上する
ものである。FIG. 2 shows another embodiment. The second drawing is a plan view, ■ is a cross-sectional view along A-A', and Q is a cross-sectional view along B-B'.
0 diffusion layer. In this embodiment, the fine p+ layer is formed so as to cross 4", and as in the embodiment shown in FIG.
This is to lower the junction breakdown voltage between + p + and improve the electrostatic breakdown voltage.
効果は、第１図の実施例と全く同様に説明できる。The effect can be explained in exactly the same way as the embodiment of FIG.
なお本実施例においては、電極２から遠い稈長数本のｐ
１微細領域７′を設けることにより、人出カパツドから
遠い部分での静電荷の放電能力を大きくすることができ
、４”ｎ＋拡散層による集積回路の保護機能を大きくす
ることができる。これは、集積回路と接続される配線部
の電位が、複数本の７′により効果的にクランプされる
ことによる。In this example, several culm lengths far from the electrode 2 are
By providing one fine region 7', it is possible to increase the ability to discharge static charges in a portion far from the outgoing capacitor, and it is possible to increase the protection function of the integrated circuit by the 4''n+ diffusion layer. This is because the potential of the wiring section connected to the integrated circuit is effectively clamped by the plurality of wires 7'.
以上述べたように本発明によれば、ホトマスク工程を追
加することなく集積回路の静電破かいに対する保両機能
を向上することができ、したがって、低価格で信頼性の
高い集積回路を提供することができる。As described above, according to the present invention, it is possible to improve the protection function against electrostatic damage of an integrated circuit without adding a photomask process, and therefore to provide a low-cost and highly reliable integrated circuit. be able to.
第１図は本発明の実施例を、第２図は他の実施例を示す
。
４／ 、５／・・・ソース、ドレインｎ＋拡散層、６・
・パ■ｊ図
鱈 ２ 図
第１頁の続き
０発 明 者 西 松 茂
国分寺市東恋ケ窪１丁目２８幡地 株式会社日立製作所
中央研究所内FIG. 1 shows an embodiment of the invention, and FIG. 2 shows another embodiment. 4/, 5/...source, drain n+ diffusion layer, 6.
・Pa■j Diagram Cod 2 Continuation of Figure 1 Page 0 Author: Shigeru Nishimatsu 1-28 Hata, Higashikoigakubo, Kokubunji City, Hitachi, Ltd. Central Research Laboratory
Claims (1)
、入出力端子と低抵抗材料を介して電気的に接続された
縞２導電型の第１の拡散層が上記基板表面に形成されて
おり、当該拡散層の表面近傍に上記第１導電型の基板と
接しかつ上記第２導電型の拡散層と接する様に上記基板
より不純物濃度の大きな微細な第１導電型の第２の拡散
層が形成されていることを特徴とする半導体装置。 ２、前記第２導電形の拡散層が、ＭＯ８形トランジスタ
のソースあるいはドレインであることを特徴とする特許
請求の範囲第１項記載の半導体装置。 ３、前記第２の拡散層が、前記ＭＯ８形トランジスタの
ゲートと重なっていることを特徴とする特許請求の範囲
第２項に記載の半導体装置。 ４、前記第２の拡散層が前記ＭＯＳトランジスタのソー
スドレイン方向に形成されており、かつ当該拡散層の幅
が、前記ＭＯ８）ランジスタのチャネル幅に対しｌ／１
０以下の寸法であることを特徴とする特許請求の範囲第
３項記載の半導体装置。 ５、前記第２の拡散層は添加不純物の微細なビームを用
いて形成されたことを特徴とする特許請求の範囲第１項
記載の半導体装置。[Claims] 1. In a semiconductor integrated circuit comprising a substrate of a first conductivity type, a striped first diffusion layer of a conductivity type 2 electrically connected to an input/output terminal via a low-resistance material is connected to the substrate. A fine first conductivity type substrate having a higher impurity concentration than the substrate is formed on the surface of the diffusion layer, and is in contact with the first conductivity type substrate and in contact with the second conductivity type diffusion layer near the surface of the diffusion layer. A semiconductor device characterized in that a second diffusion layer is formed. 2. The semiconductor device according to claim 1, wherein the second conductivity type diffusion layer is a source or drain of an MO8 transistor. 3. The semiconductor device according to claim 2, wherein the second diffusion layer overlaps the gate of the MO8 type transistor. 4. The second diffusion layer is formed in the source-drain direction of the MOS transistor, and the width of the second diffusion layer is l/1 with respect to the channel width of the MO8) transistor.
4. The semiconductor device according to claim 3, wherein the semiconductor device has a dimension of 0 or less. 5. The semiconductor device according to claim 1, wherein the second diffusion layer is formed using a fine beam of doped impurities.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16812983A JPS6060764A (en) | 1983-09-14 | 1983-09-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16812983A JPS6060764A (en) | 1983-09-14 | 1983-09-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6060764A true JPS6060764A (en) | 1985-04-08 |
Family
ID=15862373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16812983A Pending JPS6060764A (en) | 1983-09-14 | 1983-09-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6060764A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6250710B1 (en) * | 1998-09-30 | 2001-06-26 | Fuji Jukogyo Kabushiki Kaisha | Front body structure of vehicle |
-
1983
- 1983-09-14 JP JP16812983A patent/JPS6060764A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6250710B1 (en) * | 1998-09-30 | 2001-06-26 | Fuji Jukogyo Kabushiki Kaisha | Front body structure of vehicle |
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