JPS6057715B2 - Optically coupled semiconductor integrated device - Google Patents
Optically coupled semiconductor integrated deviceInfo
- Publication number
- JPS6057715B2 JPS6057715B2 JP53019647A JP1964778A JPS6057715B2 JP S6057715 B2 JPS6057715 B2 JP S6057715B2 JP 53019647 A JP53019647 A JP 53019647A JP 1964778 A JP1964778 A JP 1964778A JP S6057715 B2 JPS6057715 B2 JP S6057715B2
- Authority
- JP
- Japan
- Prior art keywords
- light
- shielding wall
- integrated device
- optically coupled
- receiving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
Description
【発明の詳細な説明】
本発明は光結合半導体装置に係り、特に光結合集積回路
素子における漏光障害の除去による集積度の改良に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an optically coupled semiconductor device, and more particularly to improving the degree of integration by eliminating light leakage problems in an optically coupled integrated circuit element.
一般にホトカプラは入出力間を電気的に絶縁できる利点
をもつため、結合すべき回路間の電気的相互干渉を防止
する必要がある場合等に両回路間ｉ−←：Ｊ 卜ｈｈコ
魯上Ｕ・ ｊ−」一 一声 Ｌ−、八最近複数の回路を
光結合するため複数の光結合素子を集積した光結合集積
回路装置が要望されてきている。In general, photocouplers have the advantage of electrically insulating input and output, so when it is necessary to prevent mutual electrical interference between circuits to be coupled, it is necessary to・J-"1 L-, 8Recently, there has been a demand for an optical coupling integrated circuit device in which a plurality of optical coupling elements are integrated in order to optically couple a plurality of circuits.
この装置は例えは発光ダイオードアレーとホトサイリス
タアレーを対向させ、各発光ダイオードと各ホトサイリ
スタが１対１で光結合するようにせしめた光結合サイリ
スタアレーや同様の構成の光結合トランジスタアレー、
光結合ダイオードアレー等である。又、受光素子にホト
サイリスタとホトトランジスタを混在せしめ、各々個別
の発光ダイオードと光結合させた構成の光結合集積装置
等てもある。ところで従来単体の光結合素子の構造が多
種類提案されているが、これらはいずれも複数の光結合
素子を集積化した場合に生ずる特有の問題、すなわち漏
光による光結合素子間の相互干渉については何ら配慮が
なされていない。This device includes, for example, a photocoupled thyristor array in which a light emitting diode array and a photothyristor array are placed opposite each other so that each light emitting diode and each photothyristor are optically coupled one-to-one, and a photocoupled transistor array with a similar configuration.
Such as an optically coupled diode array. There is also an optically coupled integrated device in which a photothyristor and a phototransistor are mixed in the light receiving element, each of which is optically coupled to an individual light emitting diode. By the way, many types of structures for single optical coupling elements have been proposed in the past, but all of them have problems that arise when multiple optical coupling elements are integrated, namely mutual interference between optical coupling elements due to light leakage. No consideration was given.
このため従来構造を用いて漏光による相互干渉のない光
結合集積素子を構成しようとすると光結合素子間を漏光
による相互干渉の生じない程度まで隔離しなければ゜な
らず集積度が著るしく低下してしまう。本発明の目的は
上述の従来技術の欠点を克服し漏光による光結合素子間
の相互干渉を防止し高集積化するのに好適な光結合半導
体集積装置を提供することにある。本発明の目的は相互
に対向する受光集積素子のいずれかの表面に低融点金属
の遮光壁を形成することによつて達成される。Therefore, when trying to construct an optical coupling integrated device using a conventional structure without mutual interference due to light leakage, the optical coupling elements must be isolated to the extent that mutual interference due to light leakage does not occur, resulting in a significant decrease in the degree of integration. Resulting in. SUMMARY OF THE INVENTION An object of the present invention is to provide an optically coupled semiconductor integrated device which overcomes the above-mentioned drawbacks of the prior art, prevents mutual interference between optically coupled elements due to light leakage, and is suitable for high integration. The object of the present invention is achieved by forming a light-shielding wall made of a low melting point metal on either surface of the mutually opposing light-receiving integrated elements.
この遮光壁は漏光による相互干渉を避けるべき受光素子
間に形成され、その高さは受発光集積素子間の距離以上
あることが好ましい。この遮光壁を構成する低融点金属
は遮光壁を形成する素子の表面を構成する物質（例えば
ＳｌＯ２やＳｉ３Ｎ４，Ｐ２Ｏ５等）と接着力が弱い必
要があり、通常軟ろう材と呼称される金属が好適である
。従つて遮光壁と素子表面物質とは両者に接着力の強く
且つ遮光壁を構成する金属よりも融点の高い中間物質を
介在させて固着される。この中間物質は必すしも単一物
質でなく積層物質でも良い。積層物質の場合素子表面側
は表面物質と接着力の強い物質Ａ１低融点金属側はこの
金属と接着力の強い物質Ｂて構成される必要があり両者
の間にはＡ，Ｂと接着力の強い物質Ｃを介在させでも良
い。中間物質は単に接着機能を有すれば良いため５μｍ
以下の薄さで十分であり、ホトエッチング技術で容易に
集積素子にコンバチブルな高精度形状加工ができる。This light-shielding wall is formed between the light-receiving elements to avoid mutual interference due to light leakage, and its height is preferably greater than the distance between the light-receiving and emitting integrated elements. The low melting point metal that makes up this light-shielding wall must have a weak adhesive strength with the substance that makes up the surface of the element that forms the light-shielding wall (for example, SlO2, Si3N4, P2O5, etc.), and the metal that is usually called a soft filler metal is used. suitable. Therefore, the light-shielding wall and the element surface material are fixed to each other by interposing an intermediate material which has a strong adhesive force and has a higher melting point than the metal constituting the light-shielding wall. This intermediate material is not necessarily a single material, but may be a laminated material. In the case of a laminated material, the element surface side must be composed of a material A that has strong adhesive strength with the surface material, and the low melting point metal side must be composed of a material B that has strong adhesive strength with this metal. A strong substance C may be used. The intermediate material only needs to have an adhesive function, so the thickness is 5 μm.
The following thickness is sufficient, and photo-etching technology can be used to easily fabricate a high-precision shape that is convertible into an integrated device.
一方遮光壁の高さは受発光素子間距離以上にするのが好
ましく通常５０μｍ以上であり、このような厚さの精密
加工形状加工は困難である。しかし、本発明に於ては遮
光壁を構成する金属−は素子表面物質との接着力が弱い
ため、素子表面の中間物質上に中間物質よりも大きい形
状に例えばマスク接着技術等で被着せしめても低融点金
属を溶融させることにより中間物質上に凝縮させること
ができる。On the other hand, the height of the light-shielding wall is preferably greater than the distance between the light receiving and emitting elements, which is usually 50 μm or more, and precision machining and shaping of such a thickness is difficult. However, in the present invention, since the metal constituting the light-shielding wall has weak adhesion to the element surface material, it is deposited onto the intermediate material on the element surface in a shape larger than the intermediate material using, for example, mask adhesion technology. However, by melting the low melting point metal, it can be condensed onto the intermediate material.
この結果凝縮後の遮光壁の底面形状はホトエッチング技
術の精度で微細加工されたと等しくなり、高集積化に好
適にできる。As a result, the shape of the bottom surface of the light-shielding wall after condensation becomes the same as if it had been microfabricated with the precision of photo-etching technology, making it suitable for high integration.
又遮光壁被着面積を中間物質面積の一定比率Ｒ倍だけ大
きくしておけば凝縮後は被着時の厚さの大よそＲ倍の高
さに．”できるので被着時間の短縮や被着物質の節約等
に効果が甚大でもある。以下実施例に基づいて本発明の
内容と効果を具体的に述べる。Also, if the area of the light-shielding wall adhered to is increased by a fixed ratio R times the area of the intermediate material, the height after condensation will be approximately R times the thickness when applied. ``Because of this, it is extremely effective in shortening the deposition time and saving materials to be deposited.'' The contents and effects of the present invention will be specifically described below based on examples.
第１図は本発明になる第１の実施例を示す。FIG. 1 shows a first embodiment of the present invention.
まくず装置の構成を説明する。本装置は発光ダイオード
の設置穴１を設けた２層セラミック基板の上層２にＳｉ
を材料とする受光集積素子３を、上記穴１内にはＣａＡ
ｓを材料とする発光ダイオード４Ａ〜４Ｄを４素子マウ
ントして構成される。受光集積素子にはゲートカソード
間に抵抗を連結せしめたラテラルホトサイリスタ５Ａ〜
５Ｄが４組集積されている。各発光ダイオードはそれぞ
れホトサイリスタに１：１に対向している。なお第１図
では省略してあるが、セラミック基板の上層２には受光
集積素子用の配線が、下層２″には発光ダイオード用の
配線が施されて所定のリードピン例えば６，６″に接続
されている。リードピンは本光結・合集積装置と他の電
子部品との連結に用いるものである。受光集積素子は周
知のＣＣＢ（ＣＯｎｔｒＯｌｌｅｄＣＯｌｌａｐｓｅＢ
Ｏｎｄｉｎｇの略）ボンデング技術によつてセラミック
基板にマウントせしめてある。各ホトサイリスタの周囲
にはＣＣＢ用のバッドと同材質であるＰｂ−Ｓｎ半田か
らなる遮光壁６Ａ〜６Ｃが設けられている。第２，第３
図は遮光壁の詳細を示す。遮光壁は受光集積素子を被覆
するＳｉＯ２膜７上に積層されたＣｒ８−Ｃｕ９の積層
膜上に形成されている。Ｃｒ８はＳｉＯ２膜７との接着
力が強い。一方ＣＵ９はＰｂ−Ｓｎ半田とアロイして合
金化するので遮光壁６Ｂとの接着力は強大である。遮光
壁は発光ダイオードと受光素子の間の距離よりも高くな
るように形成される。第４，５図は発光素子とそのマウ
ント部を示す。発受素子４は液相成長で形成したＳｉド
ープＧａＡｓ発光ダイオードであり、接合に平行な２表
面にはオーミックコンタクト用電極１０，１『が全面に
設けられ、かつマウント用のブロック状Ａｇ電極１１，
１「が設けられている。発光素子のマウント部はセラミ
ック基板２″上に印刷技術で作製された配線１２，１２
″（例えば基板側からタングステンとニッケルを印刷し
て積層。）とガラス膜（１３，１３′，１３″及びＰｂ
−Ｓｎハンダ部１４，１４″により構成される。ガラス
被覆間隔すなわちハンダ部の巾はブロック状Ａｇ電極間
の巾と同じに設定してある。発光ダイオードはＡｇ電極
端を半田部にろう付することによりボンデングする。本
装置は第１図に於て例えば発光ダイオード４Ｂを付勢し
てホトサイリスタ５Ｂを光点弧々させることにより作動
される。ところで発光ダイオード４Ｂを付勢した場合、
接合に平行な表面はオーミック電極１０，１『で被覆さ
れているためこの表面からは光は外に漏れない。一方ホ
トサイリスタ５Ｂに対向する発光ダイオード表面からは
通常あらゆる方向に光が射出する。これはＧａＡｓ発光
ダイオードとＳｉ受光素子の間に介在する物質は透光性
を要求されるため通常ＧａＡｓよりも屈折率の小さい物
質が使われることによる。この結果Ｇａ，Ａｓの表面で
全反射現象が生じる。従つて全反射の臨界角付近でＧａ
Ａｓ表面に進光した発光は９００に近い屈折角でＧａＡ
ｓ外に射出してしまう訳である。しかし本装置では、遮
光壁が受発光素子間の距離より高いのでこれらの光は全
て遮光壁で反射もしくは吸収され近接するホトサイリス
タを照射することはない。又ホトサイリスタに対向する
面とは反対の発光ダイオード表面から射出する光はＡｇ
電極１１，１「と基板のハンダ１４，１４゛とのろう付
部分で遮光され外部には出ない。一方ホトサイリスタに
対向する表面及び接合面と直角な表面からも光が射出す
るが本実施例ではこの方向にはホトサイリスタを配置し
ないので問題ない、このように発光ダイオード間を遮光
壁で仕切つた結果、発光ダイオード４Ｂを付勢した際に
隣接ホトサイリスタ５Ａや５Ｃが漏光で照射され誤点弧
したり、リーク電流の増大すなわち耐圧の低下をきたし
たり、Ｄｖ／Ｄｔ耐量が低下したりするような障害は解
消できる。ところで本実施例に於ては遮光壁は次の手順
で作製される。１素子の拡散及びＮ配線、ＳｉＯ２被覆
を終了したウェハー上に蒸着によりＣｒとＣｕを全面に
被着する。The configuration of the sawdust device will be explained. This device is made of Si on the upper layer 2 of a two-layer ceramic substrate with a hole 1 for installing a light emitting diode.
A light receiving integrated device 3 made of CaA is placed in the hole 1.
It is constructed by mounting four light emitting diodes 4A to 4D made of S as a material. The light-receiving integrated element includes a lateral photothyristor 5A with a resistor connected between the gate and cathode.
Four sets of 5D are integrated. Each light emitting diode faces the photothyristor in a 1:1 ratio. Although omitted in Fig. 1, the upper layer 2 of the ceramic substrate has wiring for a light-receiving integrated element, and the lower layer 2'' has wiring for a light emitting diode, which are connected to predetermined lead pins, for example, 6, 6''. has been done. Lead pins are used to connect this optical coupling/integration device to other electronic components. The light receiving integrated element is a well-known CCB (CONtrOlledCollapseB).
It is mounted on a ceramic substrate using bonding technology. Around each photothyristor, light shielding walls 6A to 6C made of Pb-Sn solder, which is the same material as the CCB pad, are provided. 2nd, 3rd
The figure shows details of the blackout wall. The light shielding wall is formed on a Cr8-Cu9 laminated film laminated on the SiO2 film 7 covering the light receiving integrated element. Cr8 has a strong adhesive force with the SiO2 film 7. On the other hand, since the CU9 is alloyed with the Pb-Sn solder, its adhesive strength with the light shielding wall 6B is strong. The light shielding wall is formed to be higher than the distance between the light emitting diode and the light receiving element. Figures 4 and 5 show the light emitting element and its mount. The transmitter/receiver element 4 is a Si-doped GaAs light emitting diode formed by liquid phase growth, and electrodes 10, 1' for ohmic contact are provided on the entire surface of the two surfaces parallel to the junction, and a block-shaped Ag electrode 11 for mounting is provided. ，
1" is provided. The mounting portion of the light emitting element is provided with wiring 12, 12 made by printing technology on the ceramic substrate 2".
'' (for example, tungsten and nickel are printed and laminated from the substrate side) and glass film (13, 13', 13'' and Pb
-Constructed by Sn solder parts 14, 14''.The glass coating interval, that is, the width of the solder part is set to be the same as the width between the block-shaped Ag electrodes.The light emitting diode is made by brazing the ends of the Ag electrodes to the solder part. This device is operated by, for example, energizing the light-emitting diode 4B and causing the photothyristor 5B to flash light, as shown in FIG.
Since the surface parallel to the junction is covered with ohmic electrodes 10, 1', no light leaks from this surface. On the other hand, light is normally emitted in all directions from the surface of the light emitting diode facing the photothyristor 5B. This is because the material interposed between the GaAs light emitting diode and the Si light receiving element is required to be transparent, and therefore a material with a refractive index smaller than that of GaAs is usually used. As a result, a total reflection phenomenon occurs on the surfaces of Ga and As. Therefore, near the critical angle of total reflection, Ga
The light emitted from the As surface has a refraction angle close to 900, and the GaA
This means that it is ejected outside of s. However, in this device, since the light shielding wall is higher than the distance between the light receiving and emitting elements, all of this light is reflected or absorbed by the light shielding wall and does not illuminate the adjacent photothyristor. Also, the light emitted from the surface of the light emitting diode opposite to the surface facing the photothyristor is Ag.
The light is blocked by the brazed parts between the electrodes 11, 1'' and the solders 14, 14'' on the board, and does not go outside.On the other hand, light also exits from the surface facing the photothyristor and the surface perpendicular to the bonding surface, but in this implementation In the example, there is no problem because the photothyristor is not placed in this direction.As a result of partitioning the light-emitting diodes with a light-shielding wall in this way, when the light-emitting diode 4B is energized, the adjacent photothyristors 5A and 5C are irradiated due to light leakage, causing erroneous irradiation. Problems such as ignition, an increase in leakage current, that is, a decrease in withstand voltage, and a decrease in Dv/Dt withstand capacity can be eliminated.By the way, in this example, the light-shielding wall is manufactured by the following procedure. Cr and Cu are deposited over the entire surface by vapor deposition on the wafer after diffusion of one element, N wiring, and SiO2 coating.
ＣＣｕとＣｒを順次ホトエッチングにより遮光壁の底面
に相当する所定の形状に整形加工する。Ｃｕのエッチャ
ントとしては塩化第２鉄水溶液、Ｃｒのエッチャントと
しては赤血液アルカリ液が好適である。３Ｐｂ−Ｓｎを
Ｃｒ−Ｃｕ膜上にマスク蒸着する。CCu and Cr are sequentially photoetched to form a predetermined shape corresponding to the bottom surface of the light shielding wall. A ferric chloride aqueous solution is suitable as an etchant for Cu, and a red blood alkaline solution is suitable as an etchant for Cr. 3Pb-Sn is mask-deposited on the Cr-Cu film.
この場合マスクの形状はＣｒ−Ｃ４より大きくする。こ
れは蒸着材料及び蒸着時間を節減するためである。４ウ
ェハーを３５０℃に昇温しＰｂ−Ｓｎハンダをウェット
バックしＣｒ−Ｃ４上に凝縮させて盛り上げ遮光壁を完
成する。In this case, the shape of the mask is made larger than that of Cr-C4. This is to save deposition materials and deposition time. 4 wafer is heated to 350° C., Pb-Sn solder is wet-backed and condensed on Cr-C4, and raised to complete a light-shielding wall.
以上の工程を用いることにより遮光壁の底面形状はＣｒ
−Ｃｕ膜の形状にほとんど合致する。By using the above steps, the bottom shape of the light shielding wall is made of Cr.
-It almost matches the shape of the Cu film.
すなわち遮光壁の底面形状の精度はホトエッチング技術
の精度と同等である。Ｃｒ−Ｃｕ膜はＰｂ−Ｓｎハンダ
をＳｉＯ２膜上に固着する機能を果すのみで良いため通
常各々０．２μ，０．５μ程度である。従つてホトエッ
チングが生じるサイドエッチは容易に２μｍ以下にでき
るため極めて高精度である。遮光壁は受発光素子間の距
離より大きくする必要があり通常５０μｍ以上である。
５０ｐｍ厚の物質をエッチングした場合に両サイドに５
０ｐずつ計１００μ程度のサイドエッチを逃がれないこ
とを考えれば本実施例の精度の良さは明らかであろう。In other words, the accuracy of the bottom shape of the light-shielding wall is equivalent to the accuracy of photo-etching technology. Since the Cr--Cu film only has to function to fix the Pb--Sn solder onto the SiO2 film, the thickness thereof is usually about 0.2 .mu.m and 0.5 .mu.m, respectively. Therefore, the side etch where photoetching occurs can be easily made to 2 μm or less, resulting in extremely high precision. The light shielding wall needs to be larger than the distance between the light receiving and emitting elements, and is usually 50 μm or more.
5 on both sides when etching a material with a thickness of 50 pm.
Considering that side etching of about 100 μm in total for each 0p cannot be avoided, the high precision of this embodiment will be obvious.
又遮光壁はウェットバックし凝縮させてもり上げるため
、遮光壁の高さを底面の巾よりも大きくすることが容易
である。例えば高さ１００μの遮光壁の底面巾を容易に
６０μ程度にできる。結局本実施例によれば遮光壁の底
面積を小さくでき、かつ遮光壁の位置や底面積の形状を
ホトエッチング精度で形成できるので高集積化に好適で
ある。第６，７図は本発明になる第２の実施例である。Further, since the light shielding wall is wet-backed and condensed, it is easy to make the height of the light shielding wall larger than the width of the bottom surface. For example, the bottom width of a light-shielding wall having a height of 100 μm can be easily reduced to about 60 μm. After all, according to this embodiment, the bottom area of the light-shielding wall can be reduced, and the position and shape of the bottom area of the light-shielding wall can be formed with photoetching precision, making it suitable for high integration. 6 and 7 show a second embodiment of the present invention.
ＩＣチップ３にはホトサイリスタ５とホトサイリスタに
連結される回路１５及びＬＥＤ駆動用回路１４が各４ケ
ずつ誘電分離技術を用いて相互に絶縁された状態で集積
されている。発光素子４Ｅ，４ＦはＩＣ上にマウントさ
れホトサイリスタ５と絶縁された状態で光結合され、一
方駆動用回路１４とはアノード電極１１を介して接続さ
れている。この詳細は同一発明者が特開５２−５７７８
９で開示してあるので参照されたい。発光ダイオード４
Ｅと４Ｆ間には第１の実施例と同様の遮光壁６Ｅが設け
られており、発光ダイオード間の漏光が遮ぎられる。第
８図は発光ダイオード４Ｅ，４Ｆの上面図でありＩＣ３
に対向する面を示す。発光ダイオードは主発光領域であ
るＰ層が３つに分断され各々にオーミック電極１０とＮ
電極１１が”設けられている。Ｐ層４Ｅ１と４Ｅ３は各
々ホトサイリスタと対向し光駆動用の光源として働く。
一方Ｐ層４Ｅ２は４Ｅ１と４Ｅ３の漏光に対する遮光壁
として働く。第９図は第６図と同様の断面図であるがＰ
層４Ｅ２を切断するａ−ａ″に沿つた・断面図である。
但し集積素子３内の素子構造は省略してある。（第６図
はＰ層４Ｅ１又は４Ｅ３を切断するｂ−ｂ″又はｃｍｃ
″に沿つた断面図である。）受発光素子間には遮光壁１
６Ｅ，１６Ｆが設けられている。この遮光壁は第８図に
点線で示ノした形状を有し、発光ダイオードのカソード
電極１「及びＰ層４Ｅ２のＮ電極１１Ｅ２とアロイされ
ている。この遮光壁は更にＩＣ３上を延在しセラミック
基板２の配線に連結され、発光ダイオード４Ｅ，４Ｆの
カソード配線として働く。この遮光壁１６Ｅ，１６Ｆに
より受発光素子の間隙を伝わるＰ層４Ｅ１及び４Ｅ３か
らの漏光がさえぎられ、相互干渉が防止される。ところ
で第６図のＬＥＤボンデング用ハンダ部１７は遮光壁と
同一工程で製作される。On the IC chip 3, a photothyristor 5, a circuit 15 connected to the photothyristor, and an LED driving circuit 14 are integrated in four pieces each in a state that they are insulated from each other using dielectric isolation technology. The light emitting elements 4E and 4F are mounted on an IC and optically coupled to the photothyristor 5 in an insulated state, while being connected to the driving circuit 14 via the anode electrode 11. The details are published in Japanese Patent Publication No. 52-5778 by the same inventor.
9, so please refer to it. light emitting diode 4
A light shielding wall 6E similar to that in the first embodiment is provided between E and 4F to block light leakage between the light emitting diodes. FIG. 8 is a top view of light emitting diodes 4E and 4F, and is a top view of IC3.
Indicates the surface facing the In the light emitting diode, the P layer, which is the main light emitting region, is divided into three parts, each of which has an ohmic electrode 10 and an N layer.
An electrode 11 is provided. P layers 4E1 and 4E3 each face the photothyristor and serve as a light source for optical driving.
On the other hand, the P layer 4E2 acts as a light shielding wall against leakage of light from 4E1 and 4E3. Figure 9 is a cross-sectional view similar to Figure 6, but P
FIG. 3 is a cross-sectional view taken along line a-a'' through layer 4E2.
However, the element structure within the integrated element 3 is omitted. (Figure 6 shows bb″ or cmc cutting P layer 4E1 or 4E3.
) There is a light shielding wall 1 between the light receiving and emitting elements.
6E and 16F are provided. This light-shielding wall has the shape shown by the dotted line in FIG. 8, and is alloyed with the cathode electrode 1'' of the light emitting diode and the N electrode 11E2 of the P layer 4E2.This light-shielding wall further extends over the IC3. It is connected to the wiring of the ceramic substrate 2 and serves as cathode wiring for the light emitting diodes 4E and 4F.The light shielding walls 16E and 16F block light leakage from the P layers 4E1 and 4E3 that propagates through the gap between the light receiving and emitting elements, thereby preventing mutual interference. Incidentally, the LED bonding solder portion 17 shown in FIG. 6 is manufactured in the same process as the light shielding wall.
但しこのハンダ部は遮光壁よりも高くならないように配
慮されている。即ちＣｒ−Ｃ礒が遮光壁と同一巾である
場合は、Ｐｂ−Ｓｎハンダ蒸着用のマスクにおける発光
ダイオードボンデング部のパターンの巾は遮光壁のパタ
ーン巾よりも狭くする等である。本実施例では遮光壁が
実施例１と同様微細に形成できる他に遮光壁を発光ダイ
オードの配線として兼用するので２層配線の効果が期待
でき集積度の向上により好適である。また発光ダイオー
ドのボンディング用ハンダ部がホトエッチング精度（例
えば±５μ以下）で形成できるので受発光素子の対向精
度を高くでき光結合効率を実施例１より容易に大きくで
きる。However, care has been taken to ensure that this solder part is not higher than the light shielding wall. That is, when the Cr--C layer has the same width as the light-shielding wall, the width of the pattern of the light-emitting diode bonding part in the mask for Pb--Sn solder deposition is made narrower than the pattern width of the light-shielding wall. In this example, the light-shielding wall can be formed finely as in Example 1, and the light-shielding wall is also used as the wiring for the light emitting diode, so the effect of two-layer wiring can be expected and it is more suitable for improving the degree of integration. Further, since the solder portion for bonding the light emitting diode can be formed with photoetching precision (for example, ±5 μm or less), the facing precision of the light receiving and emitting elements can be increased, and the optical coupling efficiency can be easily increased compared to the first embodiment.
実施例１では対向精度はセラミック基板の製作精度程度
（約±５０ｐ以上）であり、この精度を良くしようとす
ると歩留りが下がり価格の増大を逃がれえない。以上２
実施例に基づき説明したが、本発明はこれらに限定され
るものではなく各種変形応用が可能である。In the first embodiment, the facing accuracy is on the order of the manufacturing accuracy of the ceramic substrate (approximately ±50p or more), and if this accuracy is attempted to be improved, the yield will decrease and the price will inevitably increase. Above 2
Although the present invention has been described based on examples, the present invention is not limited to these examples, and various modifications and applications are possible.
例えば第１０図はプレーナ発光ダイオードアレーを用い
た場合の変形例である。プレーナ発光ダイオード４はＺ
ｎを拡散したＰ領域４Ｇ，４Ｈを有している。Ｐ領域４
Ｇにはアノード電極１７Ｇ″が設けられ、Ｐ領域の周囲
にはカソード電極１７ＧがＰ領域を取り囲むように設け
ら．れている。このカソード電極の巾領域側端部は電極
を設けている発光ダイオード表面に平行な接合面の最近
接端からＤｔａｎＯｃ以上離すのが好ましい。ここでｄ
はＰ層の拡散深さ、０ｃはＧａＡｓ界面における全反射
臨界角である。周知のごとくＺｎドープＧａＡｓ発光ダ
イオードの主発光領域は巾領域である。このＰ領域で発
光し受光集積素子３に対向する表面から射出する光はカ
ソード電極１７Ｇで遮光されるので、このＰ領域４Ｇに
対向する受光素子（図では省略）以外の素子を照射する
ことはない。Ｐ領域４Ｈについても同様である。ところ
で本実施例における電極１７Ｇ，Ｇ″，Ｈ，Ｈ″は発光
ダイオード側からＧａＡｓとのオーミックコンタクト用
電極−Ｐｂ，ＳｎハンダーＣｕ−Ｃｒの順で構成されて
おり、Ｃｒは受光集積素子表面に設けられたに配線と接
続している。このＡｌ配線は当然受光集積素子のＡｌ配
線とは電気的に絶縁されている。本実施例は発光ダイオ
ードが１チップに集積されるので実装が容易であるとい
う利点を有する。For example, FIG. 10 shows a modification in which a planar light emitting diode array is used. Planar light emitting diode 4 is Z
It has P regions 4G and 4H in which n is diffused. P area 4
An anode electrode 17G'' is provided in G, and a cathode electrode 17G is provided around the P region so as to surround the P region. It is preferable to distance DtanOc or more from the nearest end of the junction plane parallel to the diode surface. Here, d
is the diffusion depth of the P layer, and 0c is the critical angle of total reflection at the GaAs interface. As is well known, the main light emitting region of a Zn-doped GaAs light emitting diode is a width region. Since the light emitted in this P region and emitted from the surface facing the light receiving integrated element 3 is blocked by the cathode electrode 17G, it is impossible to irradiate any element other than the light receiving element (not shown in the figure) facing this P region 4G. do not have. The same applies to the P region 4H. By the way, the electrodes 17G, G'', H, H'' in this embodiment are composed of an electrode for ohmic contact with GaAs from the light emitting diode side - Pb, Sn solder Cu-Cr, and Cr is formed on the surface of the light-receiving integrated element. Provided with wiring and connection. Naturally, this Al wiring is electrically insulated from the Al wiring of the light-receiving integrated element. This embodiment has the advantage that the light emitting diodes are integrated into one chip, making it easy to implement.
この他本発明の変形例としてハンダ材質や中間物質等の
材質が前述した条件を満たす他の物質例えばＮ−Ｓｎハ
ンダ、Ａｇ−Ｎｉ−Ｔｉ膜等に置き換えること等もある
。以上に述べた如く本発明によれば遮光壁を集積素子と
コンパチブルな高精度の微細形状にできるので、光結合
集積素子において漏光による光結合素子間の相互干渉を
招くことなく集積度を著るしく向上できるという効果が
ある。In addition, as a modification of the present invention, the materials such as the solder material and the intermediate material may be replaced with other materials satisfying the above-mentioned conditions, such as N-Sn solder or Ag-Ni-Ti film. As described above, according to the present invention, the light-shielding wall can be made into a highly precise micro-shape that is compatible with the integrated device, so that the degree of integration can be increased without causing mutual interference between the optical coupling devices due to light leakage in the optically coupled integrated device. This has the effect of helping you improve your skills.
第１図は本発明の第１の実施例を示す概略断面図、第２
図及び第３図は第１図で使用する受光素子の断面図及び
平面図、第４図及び第５図は第１図て使用する発光素子
の平面図及び断面図、第６図は本発明の第２の実施例を
示す概略断面図、第７図は第６図で使用する受光素子の
平面図、第８図は第６図で使用する発光素子の平面図、
第９図は本発明の第３の実施例を示す概略断面図、第１
０図は本発明の第４の実施例を示す概略断面図である。FIG. 1 is a schematic sectional view showing the first embodiment of the present invention;
3 and 3 are a sectional view and a plan view of the light receiving element used in FIG. 1, FIGS. 4 and 5 are a plan view and a sectional view of the light emitting element used in FIG. 7 is a plan view of the light receiving element used in FIG. 6, FIG. 8 is a plan view of the light emitting element used in FIG. 6,
FIG. 9 is a schematic cross-sectional view showing the third embodiment of the present invention;
FIG. 0 is a schematic sectional view showing a fourth embodiment of the present invention.
Claims (1)
子と複数個の発光素子もしくは複数個の発光素子を集積
した発光集積素子から構成され上記発光素子と受光素子
が相対向して光結合された光結合素子を複数組有する光
結合集積装置において、上記光結合素子間に受光素子と
発光素子との距離以上の高さを有し、かつ少なくとも金
属から構成される遮光壁を中間物質を介して受発光集積
素子のいずれかの対向表面に具備せしめ、この中間物質
は上記素子表面材料及び遮光壁材料と接着力が強く且つ
遮光壁材料よりも融点の高い金属もしくは金属の積層膜
で構成されたことを特徴とする光結合半導体集積装置。 ２ 特許請求の範囲第１項において上記遮光壁が発光素
子の電極もしくは配線の一部を兼ねることを特徴とする
光結合半導体集積装置。[Claims] 1. A light-receiving integrated device that integrates at least a plurality of light-receiving elements and a plurality of light-emitting devices or a light-emitting integrated device that integrates a plurality of light-emitting devices, the light-emitting device and the light-receiving device facing each other. In the optical coupling integrated device having a plurality of sets of optical coupling elements optically coupled together, a light shielding wall having a height greater than the distance between the light receiving element and the light emitting element and made of at least metal is provided between the optical coupling elements. The intermediate material is provided on either opposing surface of the light emitting/receiving integrated element via an intermediate substance, and the intermediate substance is a metal or a metal laminate that has a strong adhesive force with the element surface material and the light-shielding wall material and has a melting point higher than that of the light-shielding wall material. An optically coupled semiconductor integrated device comprising a film. 2. The optically coupled semiconductor integrated device according to claim 1, wherein the light shielding wall also serves as a part of an electrode or wiring of a light emitting element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53019647A JPS6057715B2 (en) | 1978-02-24 | 1978-02-24 | Optically coupled semiconductor integrated device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53019647A JPS6057715B2 (en) | 1978-02-24 | 1978-02-24 | Optically coupled semiconductor integrated device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54113287A JPS54113287A (en) | 1979-09-04 |
| JPS6057715B2 true JPS6057715B2 (en) | 1985-12-16 |
Family
ID=12005021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53019647A Expired JPS6057715B2 (en) | 1978-02-24 | 1978-02-24 | Optically coupled semiconductor integrated device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6057715B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0246766B2 (en) * | 1985-05-31 | 1990-10-17 | Honda Giken Kogyo Kk |
-
1978
- 1978-02-24 JP JP53019647A patent/JPS6057715B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0246766B2 (en) * | 1985-05-31 | 1990-10-17 | Honda Giken Kogyo Kk |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54113287A (en) | 1979-09-04 |
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