JPS6056062B2 - Gate circuit of gate turn-off thyristor - Google Patents
Gate circuit of gate turn-off thyristorInfo
- Publication number
- JPS6056062B2 JPS6056062B2 JP52032396A JP3239677A JPS6056062B2 JP S6056062 B2 JPS6056062 B2 JP S6056062B2 JP 52032396 A JP52032396 A JP 52032396A JP 3239677 A JP3239677 A JP 3239677A JP S6056062 B2 JPS6056062 B2 JP S6056062B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- thyristor
- turn
- capacitor
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0812—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
- H03K17/08124—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit in thyristor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/12—Modifications for increasing the maximum permissible switched current
- H03K17/125—Modifications for increasing the maximum permissible switched current in thyristor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/72—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region
- H03K17/722—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region with galvanic isolation between the control circuit and the output circuit
- H03K17/723—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region with galvanic isolation between the control circuit and the output circuit using transformer coupling
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Power Conversion In General (AREA)
- Thyristor Switches And Gates (AREA)
Description
【発明の詳細な説明】
本発明はゲートターンオフサイリスタ（以下ＧＴＯと
いう）のオフゲート回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an off-gate circuit for a gate turn-off thyristor (hereinafter referred to as GTO).
ＧＴＯは第１図ａ、ｂに示すように、サイリスタと同
様アノードＡ−カソードに−ゲートＧの３・端子からな
り、通常入手できるＧＴＯはＰベースＰｂにゲート端子
Ｇが設けられており、アノードＡに正の電圧が印加され
ている状態でＧ、に間に正のパルスを加えるとＡ．．Ｋ
の向きにアノード電流が流れ、Ｇ．．Ｋ間に負のパルス
を加えるとアノード電流が零に転する。ＧＴＯを使用す
る際にはオフゲート回路をいかに構成するかが極めて重
要てある。As shown in Figure 1a and b, the GTO consists of three terminals, an anode A, a cathode, and a gate G, similar to a thyristor.Generally available GTOs have a gate terminal G on a P base Pb, and an anode When a positive voltage is applied to A and a positive pulse is applied between G and A. ．． K
An anode current flows in the direction of G. ．． Applying a negative pulse across K causes the anode current to turn to zero. When using a GTO, how the off-gate circuit is configured is extremely important.
このオフゲート回路はサイリスタ回路における転流回路
に相当するもので、装置の機能上、信頼性上に及ほす影
響が大きい。従来、ＧＴＯは大容量のものが得られなか
つたのでオフゲート回路も簡単なものでよかつたが、２
００Ａ〜６００Ａ級の大電力ＧＴＯが出現するにおよび
、オフゲート回路も低圧で１００Ａ〜２００Ａ級でしか
も電流の立上り（以下ｄ１／Ｄｔ）が数１０ＡＩｐｓ流
すことのできるものが必要になり、従来の回路では実現
が困難となつてきている。This off-gate circuit corresponds to a commutation circuit in a thyristor circuit, and has a large effect on the functionality and reliability of the device. Conventionally, a GTO with a large capacity could not be obtained, so a simple off-gate circuit was sufficient, but 2
With the emergence of high power GTOs in the 00A to 600A class, there is a need for off-gate circuits that are low voltage, 100A to 200A class, and can flow a current rise (hereinafter referred to as d1/Dt) of several tens of AIps. It is becoming difficult to realize this.
第２図はＧＴＯのターンオフ過程を示したものてあるが
、ａ図はアノード電流１Ａ，．ｂ図はＧｌＫ間電圧Ｖｃ
そしてｃ図はゲート逆電流１ｃである。Figure 2 shows the turn-off process of the GTO, and Figure a shows an anode current of 1A, . Figure b shows the GlK voltage Vc
Figure c shows the gate reverse current 1c.
ｔ＝ＴＯの時点で負のゲート電流１ｃが流れるとｔ＝ち
の時点でカソード電流は零になり、ＡｌＫ間のインピー
ダンスが増大する。このためアノード電流１Ａも減少し
始める。この時点でＰベースＰｂのキャリアは零となり
、Ｇ．．Ｋ間のＮＥＰｂ接合の絶縁は回復する。引き続
きＮ５のキャリヤがゲート電流１０として排出して完全
にブロック状態に戻る。ここで、ＧＴＯのオフゲート電
流としての具備条件をあげると次の通りである。When the negative gate current 1c flows at the time t=TO, the cathode current becomes zero at the time t=TO, and the impedance between AlK increases. Therefore, the anode current 1A also begins to decrease. At this point, the carrier of P base Pb becomes zero, and G. ．． The insulation of the NEPb junction between K is restored. Subsequently, carriers in N5 are discharged as gate current 10, completely returning to the blocked state. Here, the conditions for the off-gate current of the GTO are as follows.
（１）ゲート電流１ｃの波高値１ｃｐが所定値以上だせ
るものであること。(1) The peak value 1cp of the gate current 1c must be greater than a predetermined value.
ターンオフ可能なアノード電流１Ａとそのときのゲート
電流１０との比１Ａ／１０をターンオフゲインＧという
が、代表的な例としてはＧ＝３〜５である。したがつて
Ｉぇ＝６００ＡとすれはＧ＝３としたときＩｃｐ＝２０
０Ａは必要てある。（２）ＤＩｃ／Ｄｔが高いこと。The ratio of 1 A/10 of the anode current that can be turned off to the gate current 10 at that time is called the turn-off gain G, and a typical example is G=3 to 5. Therefore, when I=600A and G=3, Icp=20
0A is required. (2) DIc/Dt is high.
この電流勾配が低いとターンオフタイムが延びて遂には
ターンオフできなくなる。通常数１０ＡＩｐｓの立上り
が要求される。（３）Ｐｂ．（５Ｎｂの蓄積電荷Ｑｓｔ
ｇを吸収し得るもので・あること。If this current gradient is low, the turn-off time will be extended and eventually turn-off will not be possible. A rise of several 10 AIps is normally required. (3) Pb. (5Nb accumulated charge Qst
It must be something that can absorb g.
即ち、オフゲート電源の供給し得る電荷量ＱｓがＱｓ＞
Ｑｓｔｇを満足しなければならない次に従来の回路例で
はいかなる点が問題となるかを説明する。従来から使用
されている代表的なオフゲート回路としては、第３図ａ
のコンデンサ放電式と同図ｂのパルストランス式とがあ
る。ａ図のものは予かじめコンデンサ２１を図示しない
充電回路で図示極性に充電しておきＧＴＯｌをターンオ
フすべき時点でスイッチ２２を閉じてＧＴＯｌのＧ．Ｋ
間に逆電流しを流すようにしたものである。通常ＧＴＯ
ｌのゲート、カソード端子とオフゲート電源との閉回路
は、どのように配Ｌ線を短かくしても最低１〜２μＨの
インダクタンスが存在するから、もしｄ■。／Ｄｔ＝３
０ＡＩｐｓとすると、コンデンサ電圧Ｖｃは３０〜６０
■に充電すればゲート条件（１）は満足する。また閉回
路の抵抗分を低くすればゲート条件（２）も満足する。
さらにゲート条件（３）に対してはＱｓｔｇ／■Ｃて定
まる容量以上のコンデンサを選定すればよいことになる
。この値は数１０〜１００ｐＦのオーダになる。こうし
て得られたオフゲート回路は以下で述べるような実際上
非常に大きな問題がある。That is, the amount of charge Qs that can be supplied by the off-gate power supply is Qs>
Qstg must be satisfied Next, we will explain what problems arise in conventional circuit examples. A typical off-gate circuit conventionally used is shown in Figure 3a.
There are two types: the capacitor discharge type shown in Fig. 1 and the pulse transformer type shown in Figure b. In the case shown in Fig. a, the capacitor 21 is charged in advance to the polarity shown in the figure using a charging circuit (not shown), and when the GTOl is to be turned off, the switch 22 is closed to turn off the GTOl. K
A reverse current is passed between them. Normal GTO
In the closed circuit between the gate and cathode terminal of L and the off-gate power supply, there is an inductance of at least 1 to 2 μH no matter how short the L wire is, so if d■. /Dt=3
Assuming 0AIps, the capacitor voltage Vc is 30 to 60
If the battery is charged to (2), gate condition (1) is satisfied. Furthermore, if the resistance of the closed circuit is reduced, gate condition (2) is also satisfied.
Furthermore, for gate condition (3), it is sufficient to select a capacitor with a capacity equal to or greater than Qstg/■C. This value is on the order of several tens to 100 pF. The off-gate circuit obtained in this way has a very serious problem in practice as described below.
その１“つはコンデンサの充電装置である。ＧＴＯを各
種の装置に適用する場合に、なんらかの異常ですぐにオ
フしたいときとか高周波て使用するときのためには、で
きるだけ短時間（１００ｐｓのオーダ）でこのコンデン
サを充電することが望ましいが、充電時間に反比例して
電流が増し充電回路のコストアップが著しい。他の１つ
はＧＴＯ（：りＧ，，Ｋ間電圧■。１の保護装置に関す
るものてある。One of them is a capacitor charging device. When applying the GTO to various devices, it must be kept as short as possible (on the order of 100 ps) in case you want to turn it off immediately due to some kind of abnormality or when using it at high frequency. Although it is desirable to charge this capacitor at There are things.
第２図ｂでｔ＝ちの時点でＧ．．Ｋ間が回復するとその
ときのコンデンサ電圧と回路インピーダンスで決まる電
圧がＧ．．Ｋ間にＶＣＲとして生じる。コンデンサ電圧
が高い程Ｖａ。は高くなる。しかしＧＴＯのＮＥＰ，接
合のブレークダウン電圧は１５Ｖ前後であり、これを越
えるとこの接合部が壊れてしまうので、なんらかの保護
装置が必要である。この保護装置が第３図のダイオード
１１とツェナーダイオード１２である。これによりＶＣ
Ｒをツェナー電圧に制限することができる。尚、ダイオ
ード１１は図示しないオンゲート電源からの流れ込みを
おさえるために挿入されている。しかし、オフゲート電
源が供給すべきターンオフ電力はターンオフ可能な最大
アノード電流に対応して決めるので、ＧＴＯのアノード
電流が極めて低い値のときはオフゲート電源の供給電力
の極く一部がターンオフに使用され、残りの水部分はツ
ェナーダイオード１２などの保護要素に消費される。In FIG. 2b, at the time t=chi, G. ．． When the voltage between G and K is restored, the voltage determined by the capacitor voltage and circuit impedance at that time becomes G. ．． It occurs as a VCR between K. The higher the capacitor voltage, the Va. becomes higher. However, the breakdown voltage of the GTO's NEP junction is around 15V, and if this voltage is exceeded, this junction will break, so some kind of protection device is required. This protection device is the diode 11 and Zener diode 12 shown in FIG. This allows VC
R can be limited to the Zener voltage. Note that the diode 11 is inserted to suppress the flow from an on-gate power source (not shown). However, the turn-off power to be supplied by the off-gate power supply is determined according to the maximum anode current that can be turned off, so when the anode current of the GTO is extremely low, only a small portion of the power supplied by the off-gate power supply is used for turn-off. , the remaining water portion is consumed by protection elements such as the Zener diode 12.
ＧＴＯが大形化するにつれオフゲート電力は高いものが
必要で、例えば１００Ｗオーダの電力が必要である。こ
の１００Ｗオーダの電力をすべてツェナーダイオードで
消費させることが如何に困難てあるかは市販の最大定格
のツェナーダイオードを約托個も並列にしなければなら
ないことからも容易に理解てきる。つぎに第３図ｂのパ
ルストランス方式ではターンオフ時、スイッチ３２と３
３を閉じると図示しない直流電源でパルストランス３１
が励磁され、ＧＴＯｌのＧ．，Ｋ間に逆電流１０が流れ
る。この方式てはスイッチ３２と３３との投入に対する
制約が少ないので高周波用に適しているが、パルストラ
ンス３１は漏洩インダクタンスが伴なうのでＤＩｃ／Ｄ
ｔがａ図回路に比し相当低く（例えばａ図回路の１Ｂ程
度）、それだけ電源電圧をあげないとゲート条件（１）
を満足しない。その場合、Ｇ．．Ｋ間電圧ＶＧＲの保護
装置をさらに大容量化しなければならないことになる。
以上要約すると、従来のオフゲート電源はゲート条件（
１）、（２）、（３）すべてを満足させようとするとＧ
．．Ｋ間の保護装置が非常に大きくなり、性能、コスト
、部品配置のあらゆる点で実用性に乏しいものであつた
。As the GTO becomes larger, a higher off-gate power is required, for example, on the order of 100 W. It is easy to understand how difficult it is to consume all of this power on the order of 100 W by Zener diodes, from the fact that about a dozen commercially available Zener diodes with the highest ratings must be connected in parallel. Next, in the pulse transformer system shown in Fig. 3b, at turn-off, switches 32 and 3
When 3 is closed, a pulse transformer 31 is connected to the DC power supply (not shown).
is excited, and G. of GTOl is excited. , K flows between them. This method is suitable for high frequencies because there are few restrictions on turning on the switches 32 and 33, but since the pulse transformer 31 is accompanied by leakage inductance, the DIc/D
If t is considerably lower than that of the circuit shown in figure A (for example, about 1B in the circuit shown in figure A), and the power supply voltage is not increased by that much, the gate condition (1) will be met.
not satisfied. In that case, G. ．． This means that the capacity of the protection device for the voltage between K and VGR must be further increased.
To summarize the above, conventional off-gate power supplies have gate conditions (
If you try to satisfy all of 1), (2), and (3), G
．． ．． The protective device between K became very large and was impractical in all respects of performance, cost, and parts arrangement.
本発明は以上の欠点を解決するためになされたものて、
ＤＩｃ／Ｄｔが高く且つ保護要素の生じる損失の少ない
大電力用に適したＧＴＯのオフゲート回路を提供するこ
とを目的とする。The present invention has been made to solve the above-mentioned drawbacks.
It is an object of the present invention to provide a GTO off-gate circuit suitable for high power use, which has a high DIc/Dt and little loss caused by protection elements.
以下、図面を参照して本発明の一実施例を説明する。Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第４図が本発明のオフゲート回路の基本回路図で、図で
２は例えばコンデンサの直接放電による急速なＤｌｃ／
Ｄｔを持ち持続時間の短かいパルスを供給することがで
きる第１のオフゲート電源、３は例えばパルストランス
を介して行なうものてＤＩｃ／Ｄｔを若干犠牲にして低
電圧の電源で長時限且つ大電流を流すことのできる第２
のオフゲート電源で、この２つのオフゲート電源２，３
が並列的にＧＴＯｌのＧ．．Ｋ間に図示極性となるよう
に接続されている。２１は図示しない電源により図示極
性に充電されているコンデンサ、２２はスイッチ、３１
はパルストランス、３２と３３はスイッチである。Figure 4 is a basic circuit diagram of the off-gate circuit of the present invention.
The first off-gate power supply 3 is capable of supplying short-duration pulses with Dt, for example, through a pulse transformer, and is a low-voltage power supply that provides long-term and large current at a slight sacrifice of DIc/Dt. The second
These two off-gate power supplies 2 and 3
G. of GTOl in parallel. ．． K is connected to have the polarity shown. 21 is a capacitor charged with the polarity shown by a power supply (not shown); 22 is a switch; 31
is a pulse transformer, and 32 and 33 are switches.
スイッチ３２は図示しない直流電源の十極に、パルスト
ランス３１の他端はこの直流電源の一極に接続される。
この第４図回路で、ｔ＝ちの時点でスイッチ２２，２３
及び３３を閉じると、第５図に示すような電流が流れる
。The switch 32 is connected to ten poles of a DC power source (not shown), and the other end of the pulse transformer 31 is connected to one pole of the DC power source.
In this circuit of FIG. 4, at the time t=chi, the switches 22 and 23
When 33 and 33 are closed, a current as shown in FIG. 5 flows.
第５図の波形ａは第１のオフゲート電流２から流れる電
流し、、波形ｂは第２のオフゲート電源３からの電流１
Ｐ２、波形ｃはそれらの合成電流てＧＴＯのゲート電流
１ｃてある。電流■。１は高いＤＩＯｌ／Ｄｔを得るた
めに設けたものでパルス幅は短かい。Waveform a in FIG. 5 represents the current flowing from the first off-gate current 2, and waveform b represents the current flowing from the second off-gate power source 3.
P2 and waveform c are their combined current, which is the gate current 1c of the GTO. Current■. 1 is provided to obtain high DIOl/Dt, and its pulse width is short.
電流１Ｐ２はＤＩｐ２／Ｄｔは低いがパルス幅は長い。
本発明はこのように、主としてゲート条件（１）と（２
）を満足する第１のオフゲート電源２と、主としてゲー
ト条件（３）を満足する第２のオフゲート電源３とを並
列的に使用することを特徴としている。第６図は本発明
の具体的回路例である。一点鎖線で囲んだ２及び３はそ
れぞれ第１及び第２のオフゲート電源である。この図で
はＧＴＯｌのオンゲート回路とコンデンサの充電回路も
合わせて示している。まずトランジスタ１０２をオンす
ると、直流電源１００でパルストランス１０１が励磁さ
れ、その２次側に電圧が誘起する。その電圧で１つは抵
抗１０３−ＧＴＯｌのゲートＧ−ＧＴＯｌのカソードＫ
−パルストランス１０１の閉回路、そして他の１つはダ
イオード１０４−リアクトル１０５−コンデンサ２１−
ＧＴＯｌのゲートＧ−ＧＴＯｌのカソードＫ−パルスト
ランス１０１の閉回路て電流が流れ、ＧＴＯｌがターン
オフすると共にコンデンサ２１が充電される。その電圧
■。はリアクトル１０５の作用によりパルストＪランス
１０１の２次誘起電圧の約２倍になる。リアクトル１０
５とコンデンサ２１で決まる振動電流の周波数は回路の
周波数より十分高くなるようにしておく。トランジスタ
１０２はコンデンサ２１の充電後は特に回路上必要がな
けれはオフす７る。つぎに、ＧＴＯｌをオフする際は、
トランジスタ３２をオンする。The current 1P2 has a low DIp2/Dt but a long pulse width.
In this way, the present invention mainly deals with gate conditions (1) and (2).
) and a second off-gate power supply 3 that mainly satisfies gate condition (3) are used in parallel. FIG. 6 shows a specific circuit example of the present invention. 2 and 3 surrounded by dashed lines are the first and second off-gate power supplies, respectively. This figure also shows the GTOl on-gate circuit and the capacitor charging circuit. First, when the transistor 102 is turned on, the pulse transformer 101 is excited by the DC power supply 100, and a voltage is induced on its secondary side. At that voltage, one resistor 103 - the gate G of GTOl - the cathode K of GTOl
- A closed circuit of the pulse transformer 101, and the other one is a diode 104 - a reactor 105 - a capacitor 21 -
A current flows through the gate G of GTOl, the cathode K of GTOl, and the closed circuit of the pulse transformer 101, turning off GTOl and charging the capacitor 21. Its voltage ■. is approximately twice the secondary induced voltage of the pulse transformer J transformer 101 due to the action of the reactor 105. reactor 10
The frequency of the oscillating current determined by 5 and the capacitor 21 is made to be sufficiently higher than the frequency of the circuit. After charging the capacitor 21, the transistor 102 is turned off unless it is particularly necessary for the circuit. Next, when turning off GTOl,
Turn on transistor 32.
すると、パルストランス３１には・を付した極性に正の
電圧が発生する。それによつてサイリスタ２２と３３の
ゲートには正の電圧が印加されてそれぞれオンする。ま
ずサイリスタ２２のオンによつてコンデンサ２１の電荷
がコンデンサ２１−サイリスタ２２−ＧＴＯｌのＫ−Ｇ
ＴＯｌのＧ−コンデンサ２１の閉回路で急速に放電する
。その電流の流れる様子は第５図の曲線ａに示す通りて
ある。またサイリスタ３３のオンによりパルストランス
３１を介して直流電源１００からＧＴＯｌのＧ．．Ｋ間
に逆電流が流れる。その様子は第５図の曲線ｂに示す通
りである。この２つの合成電流によりＧＴＯｌはターン
オフする。コンデンサ２１の容量は前述のように小さな
容量とし、第５図の曲線ａに示すように早めに放電させ
るのて、サイリスタ２２の電流は保持電流以下になり、
オフした後更にＧＴＯｌのＧ．．Ｋ間に生じる逆電圧が
サイリスタ２２のアノード・カソード間にそのまま加わ
り、サイリスタ２２のターンオフが助勢される。Then, a positive voltage is generated in the pulse transformer 31 with the polarity marked with . As a result, a positive voltage is applied to the gates of thyristors 22 and 33, turning them on. First, when the thyristor 22 is turned on, the electric charge of the capacitor 21 is changed to K-G of the capacitor 21 - thyristor 22 - GTOl.
It is rapidly discharged in the closed circuit of the G-capacitor 21 of TOl. The manner in which the current flows is as shown by curve a in FIG. Furthermore, when the thyristor 33 is turned on, the G.sub. ．． A reverse current flows between K. The situation is as shown by curve b in FIG. GTOl is turned off by these two combined currents. As mentioned above, the capacitor 21 has a small capacity, and by discharging it early as shown in curve a of FIG. 5, the current of the thyristor 22 becomes less than the holding current.
After turning off, GTOl's G. ．． The reverse voltage generated between K is directly applied between the anode and cathode of the thyristor 22, and the turn-off of the thyristor 22 is assisted.
ＧＴＯｌの蓄積キャリヤが排出し終るとパルストランス
３１の２次巻線３１２の電圧がツエナータイオード１２
のツェナー電圧より低ければ、抵抗１３を通る電流のみ
となりパルストランス３１の電流は殆んど零となる。When the accumulated carriers of GTOl are completely discharged, the voltage of the secondary winding 312 of the pulse transformer 31 changes to the Zener diode 12.
If the Zener voltage is lower than the Zener voltage, only the current passes through the resistor 13, and the current in the pulse transformer 31 becomes almost zero.
この時点でトランジスタ３２をオフする。２次巻線３１
２の電圧がツェナー電圧以上てあるとＧＴＯｌの蓄積キ
ャリヤを排出するに必要な電流以外にツェナーダイオー
ド１２とダイオード１１を通る電流もパルストランス３
１が流すことになるので、できるだけ２次巻線３１２の
電圧はＧＴＯｌのＧ．．Ｋ間電圧の保護レベル以下に選
んでおくことが望ましい。At this point, transistor 32 is turned off. Secondary winding 31
If the voltage of 2 is higher than the Zener voltage, the current passing through the Zener diode 12 and the diode 11 in addition to the current required to discharge the accumulated carriers of the GTOl will also be lower than the pulse transformer 3.
1 of the GTOl, the voltage of the secondary winding 312 is kept as close as possible to the G.1 of the GTOl. ．． It is desirable to select a voltage below the protection level of the K voltage.
トランジスタ３２のオフによりサイリスタ３３もオフす
る。以上が第６図の回路におけるターンとオフの過程で
ある。つぎに他の実施例を説明する。When the transistor 32 is turned off, the thyristor 33 is also turned off. The above is the turn-on and turn-off process in the circuit of FIG. Next, another embodiment will be described.
第６図の回路で、サイリスタ３３はＧＴＯｌのオンゲー
ト回路．からの流れ込みを防止するために挿入されてい
る。したがつて第７図に示すようにサイリスタ３３の代
わりにダイオード３３″を数個直列に接続し、ＧＴＯｌ
のゲートトリガ電圧よりこの電圧降下を高くしておけば
、オン電流がパルストランス！３１側に流れ込むことは
防止てきる。第８図は第６図のトランジスタ３２とサイ
リスタ３３の各々にダイオード３７と３６を図示極性に
並列に設け、ダイオード１１とツェナーダイオード１２
からなる保護装置を省略したものであＺる。In the circuit shown in FIG. 6, the thyristor 33 is the on-gate circuit of GTOl. It is inserted to prevent water from flowing in. Therefore, as shown in FIG. 7, several diodes 33'' are connected in series instead of the thyristor 33, and the GTOl
If this voltage drop is set higher than the gate trigger voltage, the on-current will be a pulse transformer! This prevents it from flowing into the 31 side. In FIG. 8, diodes 37 and 36 are provided in parallel with the transistor 32 and thyristor 33 shown in FIG.
The protective device consisting of the following is omitted.
ＧＴＯｌのアノード電流ｈがほぼ零のときにターンオフ
回路を動作させると、第６図ではＧＴＯｌは直ちにオフ
するのてコンデンサ２１の放電電流はツェナーダイオー
ド１２を流れここで殆んど消費される。しかし第８図の
回路ては、ツェナーダイオード１２がない代わりにコン
デンサ２１−サイリスタ２２−パルストランス２次巻線
３１２−ダイオード３６−コンデンサ２１の閉回路が形
成される。この結果パルストランス３１の１次側にはダ
イオート３７を介して電Ｔｔ，ｉ３ｌｌが流れ、直流電
源１００にコンデンサ２１のエネルギーが戻ることにな
る。パルストランス３１の２次巻線３１２の電圧はＧＴ
ＯｌのＧ．．Ｋ間のフノレークタウン電圧以下となるよ
うにしておけばよい。トランジスタ３２はオンしても、
２次巻線から見た閉回路はダイオード１０６と抵抗１０
３の直列回路のみてあるから、そのときに流れる電流は
極く僅かである。このように、ＧＴＯｌが軽負荷の場合
は第１のオフゲート電源２のエネルギーは電源側に回生
され、第２のオフゲート電源３の電流は極く少ない。一
方、ＧＴＯｌが全負荷の場合は、前述のようにゲート条
件（１）、（２）、（３）を満足しているから極めて実
用性の高いオフゲート電源てある。第９図はコンデンサ
２１の充電方法とサイリスタ３２を符号２２″で示す位
置に変えたものである。When the turn-off circuit is operated when the anode current h of GTOl is approximately zero, in FIG. 6, GTOl is immediately turned off and the discharge current of capacitor 21 flows through Zener diode 12, where most of it is consumed. However, in the circuit of FIG. 8, there is no Zener diode 12, but instead a closed circuit of capacitor 21-thyristor 22-pulse transformer secondary winding 312-diode 36-capacitor 21 is formed. As a result, current Tt,i3ll flows to the primary side of the pulse transformer 31 via the diode 37, and the energy of the capacitor 21 is returned to the DC power supply 100. The voltage of the secondary winding 312 of the pulse transformer 31 is GT
Ol G. ．． What is necessary is to set it so that it is equal to or lower than the Funo Lake Town voltage between K. Even if the transistor 32 is turned on,
The closed circuit seen from the secondary winding is a diode 106 and a resistor 10.
Since there are only 3 series circuits, the current flowing at that time is extremely small. In this way, when the GTOl is under a light load, the energy of the first off-gate power supply 2 is regenerated to the power supply side, and the current of the second off-gate power supply 3 is extremely small. On the other hand, when GTOl is at full load, it satisfies the gate conditions (1), (2), and (3) as described above, so it is an extremely practical off-gate power supply. FIG. 9 shows a method of charging the capacitor 21 and a change in the position of the thyristor 32 indicated by the reference numeral 22''.
コンデンサ２１の充電はＧＴＯｌのゲートを介していな
いのて、ＧＴＯｌのゲート電流上の制約から無関係とな
り、電流値を自由に選択できる。またダイオード２４と
ダイオード３８により２つのオフゲート電源２，３を並
列化し、サイリスタを第６図のものと比較し１個少なく
した点に特徴がある。動作は第６図と略同様てあるから
省略する。第１０図は第２のオフゲート電源をオンゲー
ト電源と一部を共用化した点に特徴がある。まずＧＴＯ
ｌをオンするためにトランジスタ４２を点弧すると、図
示の・の極性に正の電圧が誘起し、パルストランス４１
の巻線４１２と４１３に生じた電圧でＧＴＯｌが点弧す
る。さらに２次巻線４１４に生じた電圧でコンデンサ２
１がリアクトル１０５の作用で共振充電される点は前述
と変りない。しかし第６図と異なり、ＧＴＯｌをオンす
べき期間中トランジスタ４２は導通したままにしておく
。その間にパルストランス４１は飽和し１次巻線４１１
の電流は抵抗４３て制限された値となる。いま、直流電
源１００の電圧をＥ、抵抗４３の抵抗値をＲとするとパ
ルストランス４１の１次電流はＥ／Ｒとなる。Since the charging of the capacitor 21 does not occur through the gate of GTOl, the current value can be freely selected since it is unrelated to the restriction on the gate current of GTOl. Another feature is that the two off-gate power supplies 2 and 3 are paralleled by the diode 24 and the diode 38, and the number of thyristors is reduced by one compared to the one shown in FIG. The operation is substantially the same as that in FIG. 6, so a description thereof will be omitted. FIG. 10 is characterized in that a portion of the second off-gate power supply is shared with the on-gate power supply. First, GTO
When the transistor 42 is turned on to turn on the pulse transformer 41, a positive voltage is induced in the polarity shown in the figure.
The voltage developed across windings 412 and 413 causes GT01 to fire. Furthermore, the voltage generated in the secondary winding 414 causes the capacitor 2 to
The point that 1 is resonantly charged by the action of the reactor 105 is the same as described above. However, unlike FIG. 6, transistor 42 remains conductive during the period when GTOl is to be turned on. During that time, the pulse transformer 41 is saturated and the primary winding 411
The current has a value limited by the resistor 43. Now, if the voltage of the DC power supply 100 is E and the resistance value of the resistor 43 is R, the primary current of the pulse transformer 41 is E/R.
またパルストランス４１の各巻線４１１〜４１６の巻数
をそれぞれＮｌ，ｎ２・・・・・・・・・Ｎ６とする。
つぎに、ＧＴＯｌをオフするためにトランジスタ４２を
オフすると、パルストランス４１の励磁電流をしや断す
ることになるので、その瞬間・の付した側が負の極性の
電圧がパルストランス４１の各巻線に生じる。その結果
、サイリスタ２２のゲートにはダイオード２５、抵抗２
３を介して正電圧が印加されサイリスタ２２は点弧する
。同様に、サイリスタ３３も抵抗３４を介してゲートに
正電圧が印加され点弧する。したがつて、コンデンサ２
１はサイリスタ２２を介してＧＴＯｌのＧ．Ｋ間に逆電
流を供給する一方、パルストランス４１に蓄積されたエ
ネルギにより巻線４１３−ＧＴＯｌのＫ−ＧＴＯｌのＧ
−サイリスタ３３一巻線４１３の閉回路て電流が流れる
。その電流の大きさは最大ＮｌｌｌＥ：／Ｎ３Ｒで与え
られる。かくして立上りの早いコンデンサ２１の放電電
流と持続時間の長いパルストランス４１からの電流によ
りＧＴＯｌがオフすることになる。この回路でＧＴＯｌ
が軽負荷でコンデンサ２１が完全に放電し終らないうち
にＧＴＯｌのＧ，．Ｋ間の絶縁が回復したときは、コン
デンサ２１−サイリスタ２２−パルストランス４１の３
次巻線４１３−ダイオード３６−コンデンサ２１の閉回
路で放電する。Further, the number of turns of each of the windings 411 to 416 of the pulse transformer 41 is set to Nl, n2, . . ., N6, respectively.
Next, when the transistor 42 is turned off in order to turn off the GTOl, the excitation current of the pulse transformer 41 is cut off, so that at that moment a voltage of negative polarity is applied to each winding of the pulse transformer 41. occurs in As a result, a diode 25 and a resistor 2 are connected to the gate of the thyristor 22.
A positive voltage is applied through the thyristor 3 and the thyristor 22 is fired. Similarly, a positive voltage is applied to the gate of the thyristor 33 via the resistor 34, causing it to fire. Therefore, capacitor 2
1 of GTOl via thyristor 22. While supplying a reverse current between K, the energy stored in the pulse transformer 41 causes the winding 413-GTOl to
- Current flows through the closed circuit of the thyristor 33 and the winding 413. The magnitude of that current is given by the maximum NlllE:/N3R. In this way, the GTOl is turned off due to the discharge current of the capacitor 21 which rises quickly and the current from the pulse transformer 41 which lasts a long time. With this circuit, GTOl
is under a light load, and before the capacitor 21 is completely discharged, G, . When the insulation between K is restored, the capacitor 21 - thyristor 22 - pulse transformer 41 3
Discharge occurs in the closed circuit of the next winding 413 - diode 36 - capacitor 21.
その結果、パルストランス４１の第６次巻線４１６の巻
線ｊと巻線４１３の巻数Ｎ３の比を適当に選ぶと巻線４
１６の・側の電位が直流電源１００の負極より低下しダ
イオード４５が導通し巻線４１６の端子電圧は電圧Ｅに
クランプされる。したがつて巻線４１３の電圧はｎェ／
Ｎ６になる。この大きさが、ＧＴＯｌのＧ．，Ｋ間のブ
レークダウン電圧以下となるように巻数比を選ぶことに
なる。このようにして、コンデンサ２１のエネルギの一
部を電源に戻すことができる。尚、上記説明で、パルス
トランスに代えて貫通変流器を用いることもてきる。以
上記載の如く本発明ではＧＴＯオフ電源として、ＤＩＯ
／Ｄｔが高く幅の狭いパルスを供給する第１のオフゲー
ト電源と、低圧大電流を流し得る第２のオフゲート電源
を並列にＧＴＯのＧ．．Ｋ間に接続して構成するもので
あるが、この本発明によれば次の効果が得られる。As a result, if the ratio between the winding j of the sixth winding 416 of the pulse transformer 41 and the number of turns N3 of the winding 413 is appropriately selected, the winding 4
16 becomes lower than the negative electrode of the DC power supply 100, the diode 45 becomes conductive, and the terminal voltage of the winding 416 is clamped to the voltage E. Therefore, the voltage of winding 413 is n/
It becomes N6. This size is the G. The turns ratio is selected so that the breakdown voltage between , and K is lower than or equal to the breakdown voltage. In this way, part of the energy in capacitor 21 can be returned to the power supply. Incidentally, in the above explanation, a feedthrough current transformer may be used instead of the pulse transformer. As described above, in the present invention, the DIO
A first off-gate power supply that supplies a narrow pulse with a high /Dt and a second off-gate power supply that can flow a low voltage and large current are connected in parallel to the G. ．． According to the present invention, the following effects can be obtained.
（１）第１のオフゲート電源の電圧を上げてＤＩｃｌ／
Ｄｔを高くしてもパルス幅が狭いので、保護装置の平均
損失は小さいものでよく、またその損失を原理的には極
めて小さくすることができる。(1) Increase the voltage of the first off-gate power supply to
Even if Dt is increased, the pulse width is narrow, so the average loss of the protection device may be small, and in principle, the loss can be made extremely small.
コンデンサ放電式を使う場合、電荷量が小さくてよいか
らコンデンサの値を低くできる。このことは充電装置も
簡単となり、高周波化がてきることを示す。（２）第２
のオフゲート電源はＤＩ，２／Ｄｔは低くてよいからそ
の出力電圧をＧＴＯ（７）Ｇ．．Ｋ間のブレークダウン
電圧より低めに選ふことも可能となる。When using the capacitor discharge method, the value of the capacitor can be lowered because the amount of charge is small. This means that the charging device will also be simpler and higher frequency will be possible. (2) Second
Since the off-gate power supply of DI and 2/Dt may be low, its output voltage is set to GTO(7)G. ．． It is also possible to select a voltage lower than the breakdown voltage between K.
したがつてＧ．Ｋ間の接合部が絶縁回復後印加される逆
電圧ＶＣＲがブレークダウン電圧に達しないようにする
ことができるので保護装置を完全に省略若しくは簡略化
することが可能となる。Therefore, G. Since it is possible to prevent the reverse voltage VCR applied to the junction between K after insulation recovery from reaching the breakdown voltage, it is possible to completely omit or simplify the protection device.
第１図Ａ，ｂはＧＴＯの記号と内部モデル図、第２図Ａ
，ｂ，ｃはＧＴＯのターンオフ時の波形図、第３図Ａ，
ｂはコンデンサ放電式及びパルストランス式のそれぞれ
従来のＧＴＯのオフゲート電源の回路図、第４図は本発
明の基本的実施例の回路図、第５図は本発明におけるオ
フゲート電流波形図、第６図乃至第１０図は本発明の他
実施例を説明するそれぞれ回路図てある。
１・・・・・・ＧＴＯｌ２・・・・・・第１のオフゲー
ト電源、３・・・・・・第２のオフゲート電源、２１，
４４・・・・・・コンデンサ、２２，３３，２２″・・
・・・・サイリスタ、１１，１０４，１０６，３３″，
２４，２５，３６，３７，３８，４５・・・・・・ダイ
オード、４１・・・・・・パルストランス、３２，４２
・・・・・・トランジスタ、１００・・・・・・電源。Figure 1 A and b are GTO symbols and internal model diagrams, Figure 2 A
, b, c are waveform diagrams at turn-off of GTO, Fig. 3A,
b is a circuit diagram of a conventional off-gate power supply of a capacitor discharge type and a pulse transformer type GTO, FIG. 4 is a circuit diagram of a basic embodiment of the present invention, FIG. 5 is an off-gate current waveform diagram in the present invention, and FIG. Figures 1 through 10 are circuit diagrams for explaining other embodiments of the present invention. 1...GTOl2...First off-gate power supply, 3...Second off-gate power supply, 21,
44... Capacitor, 22, 33, 22''...
...thyristor, 11,104,106,33'',
24, 25, 36, 37, 38, 45... Diode, 41... Pulse transformer, 32, 42
...Transistor, 100...Power supply.
Claims (1)
より励磁され２次巻線からダイオードを介してゲートタ
ーンオフサイリスタのオンゲート電流を供給するターン
オン用パルストランスと、１次巻線が第２のスイッチン
グ素子を介して電源により励磁され２次巻線からダイオ
ードまたはサイリスタを介してゲートターンオフサイリ
スタのオフゲート電流を供給するターンオフ用パルスト
ランスと、前記ターンオン用パルストランスの２次巻線
側に設けられ前記第１のスイッチング素子の閉路時に前
記ダイオードを介して充電されるコンデンサと、前記ゲ
ートターンオフサイリスタをターンオフする際に、前記
第２のスイッチング素子の閉路と同期して閉路し前記コ
ンデンサの充電電荷を前記ゲートターンオフサイリスタ
のオフゲート電流として放電させるための第３のスイッ
チング素子と、前記ゲートターンオフサイリスタのゲー
トとカソード間に接続されゲートターンオフサイリスタ
ターンオフ後の前記コンデンサの放電電荷を消費させる
ダイオードおよびツェナーダイオードからなる保護装置
とを備えて成ることを特徴とするゲートターンオフサイ
リスタのゲート回路。 ２ １次巻線が第１のスイッチング素子を介して電源に
より励磁され２次巻線からダイオードを介してゲートタ
ーンオフサイリスタのオンゲート電流を供給するターン
オン用パルストランスと、１次巻線が第２のスイッチン
グ素子を介して電源により励磁され２次巻線からダイオ
ードまたはサイリスタを介してゲートターンオフサイリ
スタのオフゲート電流を供給するターンオフ用パルスト
ランスと、前記ターンオン用パルストランスの２次巻線
側に設けられ前記第１のスイッチング素子の閉路時に前
記ダイオードを介して充電されるコンデンサと、前記ゲ
ートターンオフサイリスタをターンオフする際に、前記
第２のスイッチング素子の閉路と同期して閉路し前記コ
ンデンサの充電電荷を前記ゲートターンオフサイリスタ
のオフゲート電流として放電させるための第３のスイッ
チング素子と、前記第２のスイッチング素子に並列に設
けられた回生用の第１のダイオードと、前記ダイオード
またはサイリスタに逆並列に設けられた回生用の第２の
ダイオードとを備えて成ることを特徴とするゲートター
ンオフサイリスタのゲート回路。[Claims] 1. A turn-on pulse transformer whose primary winding is excited by a power supply through a first switching element and which supplies an on-gate current of a gate turn-off thyristor from a secondary winding through a diode; a turn-off pulse transformer whose winding is excited by a power supply through a second switching element and supplies an off-gate current of a gate turn-off thyristor from a secondary winding through a diode or thyristor; and a secondary winding of the turn-on pulse transformer. A capacitor provided on the line side and charged via the diode when the first switching element is closed, and a capacitor that is closed in synchronization with the closing of the second switching element when the gate turn-off thyristor is turned off. a third switching element for discharging the charge of the capacitor as an off-gate current of the gate turn-off thyristor; and a third switching element connected between the gate and cathode of the gate turn-off thyristor to consume the discharge charge of the capacitor after the gate turn-off thyristor is turned off. A gate circuit for a gate turn-off thyristor, comprising a protection device consisting of a diode and a Zener diode. 2. A turn-on pulse transformer whose primary winding is excited by a power supply through a first switching element and supplies an on-gate current of a gate turn-off thyristor from a secondary winding through a diode; a turn-off pulse transformer that is excited by a power supply through a switching element and supplies an off-gate current of a gate turn-off thyristor from a secondary winding through a diode or a thyristor; When the first switching element is closed, the capacitor is charged via the diode, and when the gate turn-off thyristor is turned off, the capacitor is closed in synchronization with the closing of the second switching element, and the charge charged in the capacitor is transferred to the capacitor. a third switching element for discharging as an off-gate current of the gate turn-off thyristor; a first diode for regeneration provided in parallel with the second switching element; and a first diode provided in antiparallel with the diode or thyristor. A gate circuit for a gate turn-off thyristor, comprising a second diode for regeneration.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52032396A JPS6056062B2 (en) | 1977-03-24 | 1977-03-24 | Gate circuit of gate turn-off thyristor |
| US05/888,365 US4203047A (en) | 1977-03-24 | 1978-03-20 | Gate circuit of gate turn-off thyristor |
| GB11358/78A GB1583620A (en) | 1977-03-24 | 1978-03-22 | Gate circuit of gate turnoff thyristor |
| DE2812632A DE2812632C2 (en) | 1977-03-24 | 1978-03-22 | Control circuit for a GTO thyristor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52032396A JPS6056062B2 (en) | 1977-03-24 | 1977-03-24 | Gate circuit of gate turn-off thyristor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53117368A JPS53117368A (en) | 1978-10-13 |
| JPS6056062B2 true JPS6056062B2 (en) | 1985-12-07 |
Family
ID=12357783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52032396A Expired JPS6056062B2 (en) | 1977-03-24 | 1977-03-24 | Gate circuit of gate turn-off thyristor |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4203047A (en) |
| JP (1) | JPS6056062B2 (en) |
| DE (1) | DE2812632C2 (en) |
| GB (1) | GB1583620A (en) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2801722A1 (en) * | 1978-01-16 | 1979-07-19 | Siemens Ag | CIRCUIT ARRANGEMENT FOR REDUCING THE RELEASE TIME OF A THYRISTOR |
| DE2937672C2 (en) * | 1979-09-14 | 1986-04-30 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Control circuit for a turn-off thyristor |
| JPS56501861A (en) * | 1979-12-28 | 1981-12-17 | ||
| JPS56136023A (en) * | 1980-03-27 | 1981-10-23 | Toshiba Corp | Pulse amplifying circuit |
| US4447767A (en) * | 1981-03-31 | 1984-05-08 | John J. Barni | SCR Motor speed control |
| US4455526A (en) * | 1982-06-29 | 1984-06-19 | The United States Of America As Represented By The Secretary Of The Air Force | FET Switching regulator |
| DE3230714A1 (en) * | 1982-08-18 | 1984-02-23 | Siemens AG, 1000 Berlin und 8000 München | SEMICONDUCTOR WITH A TURN-OFF THYRISTOR AND A TURN-OFF CIRCUIT |
| JPS5983569A (en) * | 1982-10-30 | 1984-05-15 | Toshiba Corp | Trouble detecting circuit for gate turn-off thyristor |
| US4593204A (en) * | 1983-12-27 | 1986-06-03 | General Electric Company | Driver circuits for gate turn-off thyristors and bipolar transistors |
| DE3418657C2 (en) * | 1984-05-17 | 1987-02-12 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Arrangement for controlling high-power turn-off thyristors |
| US4791350A (en) * | 1984-12-04 | 1988-12-13 | Square D Company | Current regulated switching regulator for gating gate turnoff devices |
| DE3503323A1 (en) * | 1985-01-29 | 1986-07-31 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Arrangement for accelerated turn-off of a GTO thyristor |
| JPS61221528A (en) * | 1985-03-25 | 1986-10-01 | 三菱電機株式会社 | Snubber circuit for gate turn-off thyristor |
| DE3512092A1 (en) * | 1985-03-29 | 1986-10-02 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Drive circuit for a GTO thyristor |
| JPS62141963A (en) * | 1985-12-16 | 1987-06-25 | Toshiba Corp | Off gate circuit for gto |
| JPS62256529A (en) * | 1986-04-22 | 1987-11-09 | アレン−ブラツドリイ カンパニ−，インコ−ポレ−テツド | Thyristor circuit |
| DE19731836A1 (en) * | 1997-07-24 | 1999-01-28 | Asea Brown Boveri | Method and device for driving a shutdown thyristor |
| DE10218456A1 (en) * | 2002-04-25 | 2003-11-06 | Abb Patent Gmbh | Switching power supply arrangement |
| US20080054986A1 (en) * | 2006-04-17 | 2008-03-06 | Berkebile Lee E | Resonant-Current-Source Gate Drive for Simultaneous Operation of Thyristors Using Alternating-Current in the Resonant Circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4831879U (en) * | 1971-08-20 | 1973-04-18 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3928775A (en) * | 1974-06-20 | 1975-12-23 | Gen Electric | Turn-off circuit for gate turn-off thyristors and transistors using snubber energy |
| US4001607A (en) * | 1975-06-09 | 1977-01-04 | Rca Corporation | Drive circuit for a gate semiconductor device |
-
1977
- 1977-03-24 JP JP52032396A patent/JPS6056062B2/en not_active Expired
-
1978
- 1978-03-20 US US05/888,365 patent/US4203047A/en not_active Expired - Lifetime
- 1978-03-22 GB GB11358/78A patent/GB1583620A/en not_active Expired
- 1978-03-22 DE DE2812632A patent/DE2812632C2/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4831879U (en) * | 1971-08-20 | 1973-04-18 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53117368A (en) | 1978-10-13 |
| DE2812632A1 (en) | 1978-09-28 |
| GB1583620A (en) | 1981-01-28 |
| DE2812632C2 (en) | 1985-03-07 |
| US4203047A (en) | 1980-05-13 |
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