JPS6055657A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6055657A JPS6055657A JP58164545A JP16454583A JPS6055657A JP S6055657 A JPS6055657 A JP S6055657A JP 58164545 A JP58164545 A JP 58164545A JP 16454583 A JP16454583 A JP 16454583A JP S6055657 A JPS6055657 A JP S6055657A
- Authority
- JP
- Japan
- Prior art keywords
- tantalum
- oxide film
- film
- wiring
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Abstract
Description
【発明の詳細な説明】
本発明は半導体集積回路における不働態素子の構成に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a passive element in a semiconductor integrated circuit.
従来、半導体集積回路における配線、抵抗体、容量等の
不働態素子は、配線にはＢｉ、ＡＪ、あるいはタングス
テン・シリサイド、モリブデン・シリサイド等の膜が用
いられ、抵抗体はＳＺ膜が用いられ、容量にはＳＺ酸化
膜が用いられるのが１−
通例であった。Conventionally, in passive elements such as wiring, resistors, and capacitors in semiconductor integrated circuits, films such as Bi, AJ, tungsten silicide, molybdenum silicide, etc. are used for wiring, and SZ films are used for resistors. 1- It was customary to use an SZ oxide film for the capacitor.
しかし、上記従来技術によると、例えばｓ６配線の低抵
抗化、抵抗体の抵抗値の制御性向上、容量の大容量化が
同一金属材料膜を加工して得られれば好都合であるにも
かかわらず、それが不可能であるという欠点があった。However, according to the above-mentioned conventional technology, it would be advantageous if, for example, lower resistance of the S6 wiring, improved controllability of the resistance value of the resistor, and increased capacitance could be obtained by processing the same metal material film. , the drawback was that it was impossible.
本発明は、かかる従来技術の欠点を彦くシ、より高い制
御性と高性能化を計ることができる不働態素子を同一材
料膜により半導体集積回路に集積化できる技術を提供す
ることを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to overcome the drawbacks of the prior art and to provide a technology that allows passive elements to be integrated into a semiconductor integrated circuit using the same material film, which allows for higher controllability and higher performance. do.
上記目的を達成するための本発明の基本的な構成は、半
導体装置に於て、半導体集積回路には、タンタル膜また
はタンタル珪化膜またはタンタル窒化膜を用いた配線、
タンタル窒化膜を用いた抵抗体、タンタル酸化膜を用い
た容量のいずれか２つ以上の不働体素子が同一基板上に
一体となって形成されて成ることを特徴とする。The basic configuration of the present invention for achieving the above object is that in a semiconductor device, a semiconductor integrated circuit includes wiring using a tantalum film, a tantalum silicide film, or a tantalum nitride film;
It is characterized in that two or more passive elements, either a resistor using a tantalum nitride film or a capacitor using a tantalum oxide film, are integrally formed on the same substrate.
以下、実施例により本発明を詳述する。Hereinafter, the present invention will be explained in detail with reference to Examples.
第１図は本発明の一実施例を示す半導体装置の断面図で
ある。すなわち、ＳＺ基板ｌの表面には、２−
拡散層２．フィールド酸化膜３．ゲート酸化膜４．ポリ
８ｉゲート電極５．ボＩＪ Ｅｌ ｔ ５上及び拡散層
２上には電極配線の低抵抗化の為のタンタル硅素膜６が
タンタル膜を蒸着後熱処理することによシ形成されてＭ
ＯＥＩ型ＦＥＴを構成し、フィールド酸化膜３上にはタ
ンタル膜を蒸着した後アンモニア雰囲気で窒化処理した
窒化タンタル膜からなる抵抗体７．タンタル膜を蒸着し
た後に陽極酸化によシタンタル酸化膜８となした容量が
ｓ７配線５と、工程形成される。Ａｉ配線９１とに挾ま
れて形成され、層間絶縁膜１０を形成して、へ！配線９
．９雪によシ結線して成る。FIG. 1 is a sectional view of a semiconductor device showing one embodiment of the present invention. That is, on the surface of the SZ substrate 1, there are 2-diffusion layers 2. Field oxide film 3. Gate oxide film 4. Poly8i gate electrode5. A tantalum silicon film 6 for lowering the resistance of the electrode wiring is formed on the IJ El t 5 and the diffusion layer 2 by heat-treating the tantalum film after vapor deposition.
A resistor 7 constituting an OEI type FET, which is made of a tantalum nitride film which is deposited on the field oxide film 3 and then nitrided in an ammonia atmosphere. After the tantalum film is deposited, a tantalum oxide film 8 is formed by anodic oxidation, and a capacitor is formed as the s7 wiring 5 in a process. The interlayer insulating film 10 is formed between the Ai wiring 91, and then to! Wiring 9
．． 9 It is made up of wires connected to each other in the snow.
上記の如く、半導体装置基板上にタンタル・シリサイド
による電極、メンタル窒化膜による抵抗体、タンタル酸
化膜による容量等の不働態素子を一体として構成するこ
とにより、よ多制御性の良い抵抗体、よシ低抵抗の電極
配線、よシ小面積で大容量のコンデンサー等が高集積で
形成できる効果がある。As mentioned above, by integrally configuring passive elements such as tantalum silicide electrodes, mental nitride film resistors, and tantalum oxide film capacitors on a semiconductor device substrate, resistors with better controllability, etc. It has the advantage of being able to form highly integrated low-resistance electrode wiring and large-capacity capacitors in a very small area.
尚、窒化タンタルは多結晶ｓ４配線の抵抗値よ３−
シ小さく出来るので、ＳＺ配線上にタンタル・シリサイ
ドではなくタンタル窒化膜を形成しても良く、タンタル
・シリサイド形成と同等の効果がある。Incidentally, since tantalum nitride can have a resistance value 3-x smaller than that of the polycrystalline S4 wiring, a tantalum nitride film may be formed on the SZ wiring instead of tantalum silicide, and the same effect as tantalum silicide formation can be obtained.
第１図は本発明による半導体装置の一実施例を示す断面
図である。
１・・・半導体基板 ２・・・拡散層 ３・・・フィー
ルド酸化膜 ４・・ゲート酸化膜 ５゜５１拳拳・ＳＺ
電極配線 ６・拳・メンタル硅素化膜 ７・・・タンタ
ル窒化膜 ８・・・タンタル酸化膜 ９．９１・・・Ａ
ｉ配線 ｌＯ・φ・層間絶縁膜。
以 上
出願人 株式会社諏訪精工舎
代理人 弁理士最 上 務
４−FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. 1... Semiconductor substrate 2... Diffusion layer 3... Field oxide film 4... Gate oxide film 5゜51 fist・SZ
Electrode wiring 6.Fist/mental silicide film 7...Tantalum nitride film 8...Tantalum oxide film 9.91...A
i-wiring lO, φ, interlayer insulating film. Applicant Suwa Seikosha Co., Ltd. Agent Patent Attorney Mogami 4-
Claims (1)
化膜またはタンタル窒化膜を用いた配線、タンタル窒化
膜を用いた抵抗体、タンタル酸化膜を用いた容量のいず
れか２つ以上の不働態素子が同一基板上に一体となって
形成されて成ることを特徴とする半導体装置。1. A semiconductor integrated circuit includes two or more of the following passive elements: wiring using tantalum film, tantalum silicide film, or tantalum nitride film, resistor using tantalum nitride film, and capacitor using tantalum oxide film. A semiconductor device characterized in that it is formed integrally on the same substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58164545A JPS6055657A (en) | 1983-09-07 | 1983-09-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58164545A JPS6055657A (en) | 1983-09-07 | 1983-09-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6055657A true JPS6055657A (en) | 1985-03-30 |
Family
ID=15795188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58164545A Pending JPS6055657A (en) | 1983-09-07 | 1983-09-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6055657A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5741626A (en) * | 1996-04-15 | 1998-04-21 | Motorola, Inc. | Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC) |
| EP0836229A3 (en) * | 1996-10-10 | 1999-06-02 | General Electric Company | Method and structure for integration of passive components on flexible film layers |
-
1983
- 1983-09-07 JP JP58164545A patent/JPS6055657A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5741626A (en) * | 1996-04-15 | 1998-04-21 | Motorola, Inc. | Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC) |
| EP0836229A3 (en) * | 1996-10-10 | 1999-06-02 | General Electric Company | Method and structure for integration of passive components on flexible film layers |
| US6323096B1 (en) | 1996-10-10 | 2001-11-27 | General Electric Company | Method for fabricating a flexible interconnect film with resistor and capacitor layers |
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