JPS6054464A - Three-dimensional integrated circuit device - Google Patents
Three-dimensional integrated circuit deviceInfo
- Publication number
- JPS6054464A JPS6054464A JP16391983A JP16391983A JPS6054464A JP S6054464 A JPS6054464 A JP S6054464A JP 16391983 A JP16391983 A JP 16391983A JP 16391983 A JP16391983 A JP 16391983A JP S6054464 A JPS6054464 A JP S6054464A
- Authority
- JP
- Japan
- Prior art keywords
- layers
- yield
- dimensional
- equation
- density
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010410 layer Substances 0.000 claims abstract description 35
- 230000007547 defect Effects 0.000 claims abstract description 16
- 239000002356 single layer Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- DWPVVZZGGGCRRM-UHFFFAOYSA-N (4-methoxyphenyl)-(4-methylpiperazin-1-yl)methanone Chemical compound C1=CC(OC)=CC=C1C(=O)N1CCN(C)CC1 DWPVVZZGGGCRRM-UHFFFAOYSA-N 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 244000000626 Daucus carota Species 0.000 description 1
- 235000002767 Daucus carota Nutrition 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Coils Or Transformers For Communication (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Laminated Bodies (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
ｌａ） 発明の技術分野
本発明は三次元集積回路装置（三次元ＬＳＩ）に係かり
、最も良い歩留が得られる積層数を有する三次元ＬＳＩ
に関する。[Detailed Description of the Invention] la) Technical Field of the Invention The present invention relates to a three-dimensional integrated circuit device (three-dimensional LSI), and the present invention relates to a three-dimensional integrated circuit device (three-dimensional LSI), which has a number of stacked layers that provides the best yield.
Regarding.
（ｂｌ 技術の背景
周知のように、半導体集積回路（ＩＣ）はＬ ＳＩ、Ｖ
ＬＳＩと二次元（平面）領域で微細化、高集積化されて
きたが、それは高度に集積化すれば高速動作等、極めて
利点が多いからである。しかしながら、微細化にも限度
があり、例えばＭＯＳＦＥＴのゲート長が１μｍあるい
はそれ以下ではホットエレクトロン効果が顕著に現れる
というような微細化に伴う物理的限界が見えてきた。(bl Technology Background As is well known, semiconductor integrated circuits (ICs) are LSI, V
LSI and two-dimensional (planar) areas have been miniaturized and highly integrated, because a high degree of integration has many advantages, such as high-speed operation. However, there is a limit to miniaturization, and physical limits associated with miniaturization have become apparent, for example, when the gate length of a MOSFET is 1 μm or less, the hot electron effect becomes noticeable.
一方、絶縁；、ｔ；＋Ｖ＋−に半導体層を被着し、ビー
ム・アユ ルし゛ＣＣ結晶基点して、その半導体結晶基
１ｋに素子を形成し、更にその−にに配線層を設けで、
これを多層に積みトげる構造が開発されており、これら
を基に１７で三次元ｌ、ＳＩが大きくクローズアンプｔ
ノできた・
」ユ記の、Ｌうな微細化の眼界を考え合わせると、翫°
１体的な一次元］、Ｓ１は今後にＩＣが発展するための
最大課眉１であると思われる。On the other hand, a semiconductor layer is deposited on the insulating layer;
A structure in which these are stacked in multiple layers has been developed, and based on these, the three-dimensional l, SI is large, and the close amplifier t is used.
"I was able to do it." Considering the visual field of L-like miniaturization in the Book of Yu,
S1 is considered to be the biggest challenge for the future development of IC.
（に）ｊＩ来１に術と問題）ｊλ
このような二次元ＬＳＩにおいて、どのような４１ｈ
ｉｓ’ｊの三次元ＬＳＩを形成するかは設計上極めてｒ
ｌ’ｆ 要な問題である。今後、例えば論理回路ＬＳＩ
において５０万ゲ−１・の二次元ＬＳＩを２層に積層す
るか、またＩ （１万ゲ−１・の二次元ＬＳＩを＋０＋
Ｉ８ｆにＪＩ’Ｊ Ｉｔｄするかの選択を迫られること
が当然枦想される。(to) jI to 1 techniques and problems) jλ In such a two-dimensional LSI, what kind of 41h
It is extremely difficult to form a three-dimensional LSI of is'j in terms of design.
l'f This is an important issue. In the future, for example, logic circuit LSI
2D LSIs with 500,000 gamuts are stacked in two layers, or I
It is natural to imagine that I8f will be forced to choose between JI'J Itd.
通常、−次元１．Ｓｌのプロセスおよび設計は性能、′
７ス１．納期の３つを考慮して決定されるが、′：Ｉス
トは強く歩留（ｖｉｅｌｄ ）に左右されることが知ら
れている。Usually - dimension 1. The process and design of Sl is performance,'
7th 1. It is determined by considering three factors, including the delivery date, but it is known that the ':I strike is strongly influenced by the yield.
＋ｄｌ 発明の目的
本発明はプロセスおよび設計の定数が与えられた場合に
、最も低いコストで三次元ＬＳＩを製作できる最適の積
層数、言い換えれば最も高い歩留で三次元ＬＳＩを製作
できる最適の積層数を提案するものである。+dl Purpose of the Invention The present invention aims to determine the optimal number of stacked layers that can produce a three-dimensional LSI at the lowest cost, given process and design constants, or in other words, the optimal number of stacked layers that can produce a three-dimensional LSI with the highest yield. It proposes a number.
ｒａｔ 発明の構成
その目的は、三次元夏、Ｓｌにおける能動素子形成層の
積層数を
Ｙ（Ｋ、Ｍ）、 ＝ ｙ ｏ ｅｘｐ （−ｎ−ａ・Ｉ
）Ｋ ２／ Ｍ）但し、Ｙ（Ｋ）’Ｉ） ｉ全歩留
ｙｏ ；各工程の平均工程歩留
ｎ；単層の工程数
ａ；回路゛密度に関する比例定数
Ｄ；平均欠陥密度
に；チップ当たりの能動素子数
Ｍ；能動素子形成層の積層数
なる式をＭで偏微分してつＹ／ａＭ＝０として微分して
えられるＭ＝Ｍｏを積層数とし、Ｍｏなる１ｉ数を有す
る三次元重積回路装置によって達成される。また、三次
元１．５１における能動素子が形成された４ＩＪ１−数
をＭ。として
Ｍ、、＝にん■じ何エガコ７ゴ
イ１１シ、Ｋ；チップ当たりの能動素子数ａ；回ｖ８密
度に関する比例定数
＋１ ； ｉｌｌ均欠陥密度
、。；平均工程歩留
からなる式で」ｊえられるＭ。なる層数を有する三次元
隼偵回１？８装置１ｖによっても達成される。rat Structure of the Invention The purpose is to calculate the number of laminated active element forming layers in Sl in a three-dimensional summer as Y (K, M), = yo exp (-n-a・I
)K2/M) However, Y(K)'I) iTotal yield yo; Average process yield of each process n; Number of single layer processes a; Proportionality constant D regarding circuit density; Average defect density; Number of active elements per chip M: Partially differentiate the formula for the number of laminated layers of active element forming layers by M, and differentiate as Y/aM=0.M=Mo is the number of laminated layers, and has a 1i number of Mo. This is accomplished by a three-dimensional stacked circuit device. Also, M is the number of 4IJ1-active elements formed in three dimensions 1.51. As M, , = carrot *jika egako7 goi 11shi, K; number of active elements per chip a; proportionality constant for v8 density +1; ill average defect density; ; M can be calculated by the formula consisting of the average process yield. This can also be achieved by a three-dimensional Hayabusa scout 1 to 8 device 1v having a number of layers.
（「）発明の実施例
１７７士、ｉｉ”ｆ細に説明すると、本発明にかかる積
層数決定方法しに一次元ＬＳＩの歩留計算法を基礎に１
−７でいるため、まず二次元ｔｓｒの歩留計算法の暑Ｉ
！Ｉｌ要をｊ見明する。(``) Embodiment 177 of the invention, ii''f To explain in detail, the method for determining the number of stacked layers according to the present invention is based on the yield calculation method for one-dimensional LSI.
-7, first the heat I of the two-dimensional tsr yield calculation method.
! I have a clear idea of the key points.
欠陥密度はポアソン分布に依存すると仮定する。It is assumed that the defect density depends on the Poisson distribution.
そうすると、Ｔ稈数ｒ−によって完成される半導体つ１
ハ の・°ノエハー歩留Ｙは次式で表わされる。Then, the semiconductor unit 1 completed by the T culm number r-
The Noeher yield Y of C is expressed by the following formula.
ここに、）＋、、 Ａ、、ｌ）、ばそれぞれ１番目工程
の工程歩留、欠陥に関連ある面積、欠陥密度で、本式に
おける有頂のｎｙなる因子は各工程歩留の積、指数関数
因子は欠陥の面積依存を表すものである。Here, )+, , A, , l) are the process yield of the first process, the area related to defects, and the defect density, respectively, and the eclipsed factor ny in this equation is the product of the yields of each process, The exponential factor represents the area dependence of defects.
欠陥密度り、とは結晶欠陥のみならずゴミの付着など、
電気的特性に及ぼす色々の欠陥を意味しており、欠陥に
関連ある面積Ａ、とはそれの起こり易い領域の面積、単
層にはチップ上の能動素子領域の占める面積を意味して
いる。Defect density refers not only to crystal defects but also to particles such as adhesion of dust.
It refers to various defects that affect electrical characteristics, and the defect-related area A means the area of the area where defects are likely to occur, and the single layer refers to the area occupied by the active element area on the chip.
（１）式は複雑であるから、これを簡単して、Ｙ ＝
ｙ ｏｅｘｐ （−ｎ−Ａ−Ｄ） −−−−−−＋２１
と仮定する。ここに、ｙｏは全工程数ｎの平均工程歩留
、Ａはチップ面積、Ｄはチップ面積の欠陥密度とする。Since equation (1) is complicated, we can simplify it and get Y =
y oexp (-n-A-D) --------+21
Assume that Here, yo is the average process yield of the total number of processes n, A is the chip area, and D is the defect density of the chip area.
また、チップ面積Ａとチップ当たり素子数Ｋ（トランジ
スタ、ゲートなどの能動素子を素子と略称する）との関
係は、
Ａ（Ｋ） ＝ａ、に２−−−−−−−−−−−−−−−
−−−−−（３）と仮定する。Ａ（Ｋ＞は素子数Ｋを有
するチップ面積を表わし、ａは回路密度に関する比例定
数である。このように素子数の２乗にチップ面積が比例
するわし」は、素子−が増えると配線数が増加するから
であり、理論的ｉ１Ｆ明ノ）なされていて、且つ（３）
式はＣＭＯＳゲー１７レイの実際の製品の値と良い一致
を示している。In addition, the relationship between the chip area A and the number of elements per chip (active elements such as transistors and gates are abbreviated as elements) is as follows: A(K) = a, 2 ------
------- (3) Assume. A (K> represents the chip area with the number of elements K, and a is a proportionality constant related to the circuit density. In this way, the chip area is proportional to the square of the number of elements.) As the number of elements increases, the number of wires increases. (3)
The formula shows good agreement with the actual product values of CMOS game 17 rays.
（；５）式を（２日（に入れると、次式が１ｑられる。If we put the equation (;5) into (2nd), the following equation becomes 1q.
Ｙ（Ｋ） ＝ ｙ＋Ｉ ｅｘｌｌ（ｎ・ａ−Ｉ）−に２
） −−−−−−（４１ごの（引代は歩留Ｙ （Ｋ）が
素子数Ｋに依存することを示しているものである。Y(K) = y+I exll(n・a−I)−2
) --------(The shipping charge for each 41st unit indicates that the yield Y (K) depends on the number of elements K.
以にに説明した二次元ＬＳＩの式を基礎にして、三次元
ＬＳＩにおＩＪる同様の式を計算する。この場合、素子
を形成した層の積層数をＭとすれば、」二重工程数ｎを
Ｍ倍繰り返して形成すると考えてよいから、−次元式の
ｎは三次元式ではＭ Ｘ ｎと置き換えられる。Based on the formula for the two-dimensional LSI described above, a similar formula for the three-dimensional LSI is calculated. In this case, if the number of laminated layers forming the element is M, it can be considered that the number of double steps n is repeated M times, so n in the -dimensional formula is replaced with M X n in the three-dimensional formula. It will be done.
また、三次元に１旨」る見掛は上のチップ面積はＡ（Ｋ
）＝ａ・（Ｋ／Ｍ）２−−−−−−−−−（５１となり
、二次元に才団る（３）式は三次元では（５）式に代わ
る。In addition, the apparent chip area of ``one effect in three dimensions'' is A(K
)=a・(K/M)2−−−−−−−−(51), and the formula (3) that is effective in two dimensions is replaced by the formula (5) in three dimensions.
これら２つの条件を（２）式に入れると、（４）式に代
わって次式かえられる。When these two conditions are put into equation (2), equation (4) is replaced by the following equation.
ＹＫＭ） −）’ｏ ｅｘｐ （−ｎ−ａ−Ｄ−に２
／Ｍ） −＋６１この式の有頂のｙ。は工程に関連する
歩留であり、後項は欠陥に関連する歩留、例えば作業間
違いや製造装置の故障などが関係する歩留である。（６
）式はＭ＝１とすれば、（４）式かえられるから二次元
ＬＳＩを含む式となる。YKM) -)'o exp (-n-a-D-ni 2
/M) −+61 the eclipsed y of this equation. is the yield related to the process, and the latter term is the yield related to defects, for example, the yield related to operational errors and failures of manufacturing equipment. (6
) can be changed to equation (4) by setting M=1, so it becomes an equation that includes a two-dimensional LSI.
この（６）式において、歩留Ｙ（ＫＭ）がＭに関し極大
値をもち、その時のＭ−Ｍｏが最適の素子形成層の積層
数となる。また、（６）式をＭで偏微分する（ａｙ／ａ
Ｍ＝０）と、
Ｍｏ ＝Ｋ ａ＝Ｄ／ ｌＬｏｇ ）’ｏ ｌ −−−
−１７）なる式かえられる。この式でＭ（、≧２とする
にはｙｏ≧ｅｘｐ （−ａ−１）Ｋ２／ ４） −−−
−−（８１の条件が必要になる。In this equation (6), the yield Y (KM) has a maximum value with respect to M, and M-Mo at that time becomes the optimal number of stacked element forming layers. Also, partial differentiation of equation (6) with respect to M (ay/a
M=0) and Mo=Ka=D/lLog)'ol ---
-17) The expression can be changed. In this formula, M(, To make ≧2, yo≧exp (-a-1)K2/ 4) ---
--(81 conditions are required.
さて、上記にえられた（６）式により、一定条件を与え
た歩留Ｙ（Ｋ、Ｍ ）と積層数Ｍとの関係を図表に示し
ている。条件は次の通りである。Now, based on the equation (6) obtained above, the relationship between the yield Y (K, M) and the number of stacked layers M under certain conditions is shown in a chart. The conditions are as follows.
ｎ＝２０工程
ａ ＝ ２Ｘ ｌ Ｏ−”ｃＪ／ （素子）２Ｄ＝０．
０５／ｃ＋Ｊ
Ｋ−５Ｘｌｌ 素子／チップ
かくして、平均歩留（ｙｏ ）が０．９９の場合が実線
Ｉ、平均歩留が０．９９９の場合が実線■で示され、ご
の３１、うにして真１算した１通の積層数Ｍ（１を三次
元１．３Ｉの素子形成層の積層数とすれば、最低コス１
のＩＣが得られる。n=20 steps a=2X l O−”cJ/ (element) 2D=0.
05/c+J K-5Xll element/chip Thus, when the average yield (yo) is 0.99, the solid line I is shown, and when the average yield is 0.999, the solid line ■ is shown. The number of laminated layers M (1 is the number of laminated layers of a three-dimensional 1.3I element forming layer, then the minimum cost is 1)
This results in an IC of
１ｇ） 発明の効果
以上の説明から明らかなように、本発明によれば二次元
１．３Ｉを（ｊ（：ｒストで製造できるため、三次元１
．Ｓｒの進歩に顕著に寄与するものである。1g) Effects of the Invention As is clear from the above explanation, according to the present invention, two-dimensional 1.3I can be manufactured by
．． This will significantly contribute to the progress of Sr.
図表は本発明により１ηられた歩留Ｍｌ（Ｍ ）と積層
数Ｍとの関係図表である。
ＯＩｏ ２０The chart is a relationship chart between the yield Ml (M 2 ), which is reduced by 1η according to the present invention, and the number of laminated layers M. OIO 20
Claims (2)
を Ｙ（ＫＭ） ＝ ）’ ｏ ｅｘｐ （−ｎ−ａ−Ｄ−
に２／Ｍ）但し、Ｙ（ＫｌＭ） ；全歩留 ｙｏ ；各工程の平均工程歩留 ｎ；単層の工程数 ａ；回路密度に関する比例定数 Ｄ；平均欠陥密度 に；チップ当たりの能動素子数 Ｍ；能動素子形成層の積層数 なる式をＭで偏微分し３Ｙ／”７５Ｍ＝０としてえられ
るＭ＝ＭＯを積層数とし、ＭＯなる層数を有することを
特徴とする三次元集積回路装置。(1), the number of laminated active element formation layers in a three-dimensional LSI is Y (KM) = )' o exp (-n-a-D-
2/M) However, Y(KlM); total yield yo; average process yield of each process n; number of single layer processes a; proportionality constant D for circuit density; average defect density; active elements per chip A three-dimensional integrated circuit characterized in that the number M is the number of laminated layers, where M=MO, which is obtained by partially differentiating the formula 3Y/"75M=0 by partially differentiating the formula M: the number of laminated layers of active element formation layers, is MO, and the number of laminated layers is MO. Device.
をＭ、として Ｍｏ＝ＫＪｉ「７丁ｌｏｇ ）Ｆｏ １但し、Ｋ；チッ
プ当たりの能動素子数 ａ；回路密度に関する比例定数 Ｄ；平均欠陥密度 ｙｏ ；平均工程歩留 からなる式で与えられるＭ。なる層数を有することを特
徴とする三次元集積回路装置。(2), where M is the number of laminated active element formation layers in a three-dimensional LSI, Mo = KJi 7 log ) Fo 1, where K: number of active elements per chip a; proportionality constant related to circuit density D: average defect A three-dimensional integrated circuit device characterized by having a number of layers M given by an equation consisting of density yo; average process yield.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16391983A JPS6054464A (en) | 1983-09-05 | 1983-09-05 | Three-dimensional integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16391983A JPS6054464A (en) | 1983-09-05 | 1983-09-05 | Three-dimensional integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6054464A true JPS6054464A (en) | 1985-03-28 |
| JPH0518257B2 JPH0518257B2 (en) | 1993-03-11 |
Family
ID=15783313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16391983A Granted JPS6054464A (en) | 1983-09-05 | 1983-09-05 | Three-dimensional integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6054464A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1072556C (en) * | 1995-12-27 | 2001-10-10 | 日立造船株式会社 | Fold construction of corrugated fiberboard |
-
1983
- 1983-09-05 JP JP16391983A patent/JPS6054464A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1072556C (en) * | 1995-12-27 | 2001-10-10 | 日立造船株式会社 | Fold construction of corrugated fiberboard |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0518257B2 (en) | 1993-03-11 |
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