JPS6054334U - integrated circuit device - Google Patents

integrated circuit device

Info

Publication number
JPS6054334U
JPS6054334U JP14724083U JP14724083U JPS6054334U JP S6054334 U JPS6054334 U JP S6054334U JP 14724083 U JP14724083 U JP 14724083U JP 14724083 U JP14724083 U JP 14724083U JP S6054334 U JPS6054334 U JP S6054334U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
gates
disposed
registration request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14724083U
Other languages
Japanese (ja)
Inventor
弘道 木村
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP14724083U priority Critical patent/JPS6054334U/en
Publication of JPS6054334U publication Critical patent/JPS6054334U/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の記憶回路を含むゲートアレーの構成を示
す図、第２図は本考案による記憶回路を含むゲートアレ
ーの構成を示す一例である。 Ａ、　Ｂ・・・・・・チップ外形を示す、３，４・・・
・・・論理回路部、２・・・・・・記憶回路部の為の配
線領域、１゜５、６．７・・・・・・記憶回路部。FIG. 1 is a diagram showing the structure of a gate array including a conventional memory circuit, and FIG. 2 is an example showing the structure of a gate array including a memory circuit according to the present invention. A, B... Indicates the chip outline, 3, 4...
...Logic circuit section, 2... Wiring area for memory circuit section, 1°5, 6.7... Memory circuit section.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数個のゲートを含み、該複数個のゲートを選択的に使
用し目的の機能を得る構成を有する集積回路に於て、該
集積回路内に複数個のメモリー機能集団を分散的に配置
して成ることを特徴とする集積回路装置。In an integrated circuit that includes a plurality of gates and is configured to selectively use the plurality of gates to obtain a desired function, a plurality of memory function groups are disposed in a distributed manner within the integrated circuit. An integrated circuit device characterized by comprising:
JP14724083U 1983-09-22 1983-09-22 integrated circuit device Pending JPS6054334U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14724083U JPS6054334U (en) 1983-09-22 1983-09-22 integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14724083U JPS6054334U (en) 1983-09-22 1983-09-22 integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6054334U true JPS6054334U (en) 1985-04-16

Family

ID=30327493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14724083U Pending JPS6054334U (en) 1983-09-22 1983-09-22 integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6054334U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5571060A (en) * 1978-11-24 1980-05-28 Hitachi Ltd Manufacture of i2l semiconductor device
JPS5882533A (en) * 1981-07-10 1983-05-18 Hitachi Ltd Semiconductor integrated circuit device
JPS5887644A (en) * 1981-11-06 1983-05-25 テキサス・インスツルメンツ・インコ−ポレイテツド Programmable digital information processing system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5571060A (en) * 1978-11-24 1980-05-28 Hitachi Ltd Manufacture of i2l semiconductor device
JPS5882533A (en) * 1981-07-10 1983-05-18 Hitachi Ltd Semiconductor integrated circuit device
JPS5887644A (en) * 1981-11-06 1983-05-25 テキサス・インスツルメンツ・インコ−ポレイテツド Programmable digital information processing system

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