JPS6052996A - Sense amplifying circuit - Google Patents

Sense amplifying circuit

Info

Publication number
JPS6052996A
JPS6052996A JP58160263A JP16026383A JPS6052996A JP S6052996 A JPS6052996 A JP S6052996A JP 58160263 A JP58160263 A JP 58160263A JP 16026383 A JP16026383 A JP 16026383A JP S6052996 A JPS6052996 A JP S6052996A
Authority
JP
Japan
Prior art keywords
transistor
transistors
voltage
gate
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58160263A
Other languages
Japanese (ja)
Other versions
JPH0159679B2 (en
Inventor
Hideji Koike
秀治 小池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP58160263A priority Critical patent/JPS6052996A/en
Publication of JPS6052996A publication Critical patent/JPS6052996A/en
Publication of JPH0159679B2 publication Critical patent/JPH0159679B2/ja
Granted legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To maintain a symmetry of a sense amplifier even after irradiating a radiant ray, by equalizing a shift quantity of a threshold voltage of an MOS transistor by irradiating the radiant ray, extending over the whole circuit. CONSTITUTION:As for a pair of N type transistors Q6, Q7, one terminal is connected to an input signal terminal 12 and a reference signal input terminal 13, the back gate is connected to a ground, and they are controlled by a prescribed gate voltage VR. On the other hand, a pair of (p) type transistors Q8, Q9 of a common gate are connected between the other terminals of the transistors Q6, Q7 and a power source terminal 11, also the back gate is connected to the terminal 11, and the common gate and the transistor Q7 are connected. A sense amplifier for outputting a sense output OUT is formed by these transistors Q6, Q7 and Q8, Q9. Accordingly, between the same type transistors Q6 and Q7, and Q8 and Q9, the voltage between the gate and the back gate becomes the same, a shift quantity of a threshold voltage is equalized extending over the whole circuit, and even after irradiating a radiant ray, the symmetry can be maintained, and the sense amplifying circuit is operated stably and with a high accuracy.

Description

【発明の詳細な説明】 ′〔発明の技術分野〕 この発明は、半導体集積回路に係るもので、特にＣＭＯ
Ｓメモリ回路に使用される耐放射線性に優れたセンスア
ンプ回路に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to semiconductor integrated circuits, and in particular to CMO
The present invention relates to a sense amplifier circuit with excellent radiation resistance used in S memory circuits.

〔発明の技術的背景〕[Technical background of the invention]

一般に、０ＭＯ８構成のセンスアンプ回路は、例えば第
１図に示すように構成されている。すなわち、それぞれ
のダートに入力信号ＤＩＮおよび基準電圧Ｖｒｅｆが印
加される一対の入力用トランジスタＱ＋　、Ｑ２の一端
と電源電圧ＶＣＣが印加される電源端子１１間にはそれ
ぞれカレントミラー回路を構成する負荷トランジスタＱ
３．Ｑ４が挿接され、トランジスタＱ＋　−Ｑ２の他端
は共通接続されてトランジスタＱ５を介して接地される
。このトランジスタＱ５のダートには所定の電位ｖＲが
印加されて導通設定され、定電流源として働く。そして
、トランジスタＱｌ、Ｑ３′−トは接地され、トランジ
スタＱ３　、Ｑ４のパックゲートは電源端子１１に接続
される。Generally, a sense amplifier circuit having an 0MO8 configuration is configured as shown in FIG. 1, for example. That is, a load transistor forming a current mirror circuit is connected between one end of a pair of input transistors Q+ and Q2 to which the input signal DIN and the reference voltage Vref are applied to each dart, and the power supply terminal 11 to which the power supply voltage VCC is applied. Q
3. Q4 is inserted and connected, and the other ends of transistors Q+-Q2 are commonly connected and grounded via transistor Q5. A predetermined potential vR is applied to the dart of this transistor Q5 to make it conductive, and it functions as a constant current source. The transistors Q1 and Q3' are grounded, and the pack gates of the transistors Q3 and Q4 are connected to the power supply terminal 11.

上記のような構成において、入力信号ＤＩＮのレベルが
基準電圧ｖｒｅｆよシ低い時は、トランジスタＱ１はオ
フ状態、Ｑ２はオン状態となシ出力信号ＯＵＴはハイ（
“Ｈ”）レベルとなる。一方、入力信号ＤＩＮのレベル
が基準電圧ｖｒｅｆを越えると、トランジスタＱ１はオ
ン状態、Ｑ２はオフ状態に反転し、出力信号ＯＵＴはロ
ー（Ｌ″）レベルとなる。In the above configuration, when the level of the input signal DIN is lower than the reference voltage vref, the transistor Q1 is in the off state, the transistor Q2 is in the on state, and the output signal OUT is high (
“H”) level. On the other hand, when the level of the input signal DIN exceeds the reference voltage vref, the transistor Q1 is turned on, the transistor Q2 is turned off, and the output signal OUT becomes a low (L'') level.

〔背景技術の問題点〕[Problems with background technology]

ところで、半導体累子（ＭＯＳ　）ランジスタ）に放射
線が照射された場合、放射線によってダート酸化膜中の
負の電荷がはじき出されてケ゛−ト酸化膜が正に帯電す
るため、各トランジスタのしきい値電圧が相対的に見て
低下（負の方向へシフト）する。このしきい値電圧のシ
フト量゛はＭＯＳ　）ランジスタのダートとパックゲー
トとの間の電圧に依存しており、今、第１図に示した回
路において入力信号Ｉ）ｒＮのレベルが基準電圧ｖｒｅ
ｆに対してｒ　ＤＩＮ　〉■ｒｅｆ　Ｊなる関係にある
リングの対称性が失なわれ、センス動作が不安定’−善
’、■シ感度も低下する欠点がある。By the way, when a semiconductor transistor (MOS transistor) is irradiated with radiation, the negative charges in the dirt oxide film are thrown out by the radiation and the dirt oxide film becomes positively charged, so that the threshold value of each transistor decreases. The voltage relatively decreases (shifts in the negative direction). The amount of shift of this threshold voltage depends on the voltage between the dirt and the pack gate of the MOS transistor, and now, in the circuit shown in FIG.
The symmetry of the ring, which has the relationship r DIN > ref J with respect to f, is lost, the sensing operation is unstable, and the sensitivity is also reduced.

回路で、前記第１図の回路を対称配置してセンス動作の
安定化を図ったものである。図において第１図と同一構
成部には同じ符号を付してその説明は省略する。このよ
うな構成においても前記第１図の回路と同様に放射線の
照射によってセンスアンプの対称性が失なわれ、動作が
不安定となるとともに、感度が低下する欠点がある。In this circuit, the circuit shown in FIG. 1 is arranged symmetrically to stabilize the sensing operation. In the figure, the same components as in FIG. 1 are given the same reference numerals, and their explanations will be omitted. Even in this configuration, as with the circuit shown in FIG. 1, the symmetry of the sense amplifier is lost due to radiation irradiation, resulting in unstable operation and reduced sensitivity.

〔発明の目的〕[Purpose of the invention]

この発明は上記のような事情に鑑みてなされたもので、
その目的とするところは、放射線によるＭＯＳ　）ラン
ジスタのしきい値電圧のシフト量を回路全体に渡って均
一化することにより、放射線照射後もセンスアンプの対
称性を維持でき安定で高感度な動作を行なえる耐放射線
性に優れたセンスアンプ回路を提供することである。This invention was made in view of the above circumstances,
The purpose of this is to equalize the amount of shift in the threshold voltage of the MOS (MOS) transistor caused by radiation throughout the circuit, thereby maintaining the symmetry of the sense amplifier even after radiation irradiation, resulting in stable and highly sensitive operation. An object of the present invention is to provide a sense amplifier circuit with excellent radiation resistance that can perform the following.

・〔発明の概要〕 り１瀦の対称性を維持するために、一端から入゛ｊ　・
′！ｊ 力信号あるいは基準電圧が供給されパックケ°−１１〜
接地された第１導電形で一対の入力用第１゜第２Ｍ０Ｓ
トランジスタを設け、この第１．第２ＭＯ８）ランノス
タのケゝ−トに電位発生手段によって発生した所定電位
を印加して導通設定し、上記第１．第２Ｍ０３）ランジ
スタの他端に電位供給手段によってそれぞれ選択的に電
流を供給して、上記第１あるいは第２Ｍ０Ｓトランジス
タの他端から出力を得るように構成したものである。・[Summary of the invention] In order to maintain the symmetry of the
′! j If the power signal or reference voltage is supplied and the pack case is
A pair of input 1st and 2nd M0S with the grounded first conductivity type.
A transistor is provided, and this first . 2nd MO8) A predetermined potential generated by a potential generating means is applied to the case of the lannostar to set conduction, and the above-mentioned 1st MO. The current is selectively supplied to the other end of the second M03) transistor by the potential supply means, so that an output is obtained from the other end of the first or second M0S transistor.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例について第３図を参照して説
明する。すなわち、一端が信号入力端子１２あるいは基
準電圧ｖｒｅｆの印加端子１３に接続されパックゲート
が接地された第１導電形（Ｎチャネル形）で一対の入力
用第１．第２ＭＯＳ　）ランジスタＱａ　、Ｑ７を設け
、これらトランジスタＱ　６　ｖ　Ｑ　７のゲートに図
示しない電として働く第２導電形（Ｐチャネル形）の第
３゜４、第、４Ｍ０８）ランジスタＱｓ　、Ｑｓを挿接
する。An embodiment of the present invention will be described below with reference to FIG. That is, one end is connected to the signal input terminal 12 or the reference voltage vref application terminal 13, and the pack gate is grounded. 2nd MOS) transistors Qa and Q7 are provided, and 3rd conductivity type (P channel type) transistors Qs and 4M08 are inserted into the gates of these transistors Q6vQ7, which serve as currents (not shown). come into contact with

崩、、７．ッ２＊Ｑｓ、Ｑｅ。ヶー□、□′続し、パッ
クケゝ−トはそれぞれ電源端子１１に接続する。そして
、トラン・ゾスタＱ６とＱＢとの接続点から入力信号Ｄ
１１４と基準電圧Ｖｒｅｆとの比較出力ＯＵＴを得るよ
うにして成る。なお、電位発生手段の出力電位ｖＲはト
ランジスタＱ６ｔＱ７のしきい値電圧ｖＴｎ６＋　ＶＴ
Ｒ７よシ犬きく、電源電圧ＶＣＣよシ小さく、且つ電位
ｖＲは基準電圧Ｖｒｅｆよシ大きい、つまシ次式（１）
　、　（２）に示すような関係を有する。Collapse, 7. t2*Qs, Qe. The pack case is connected to the power supply terminal 11, respectively. Then, input signal D is input from the connection point between Tran Zosta Q6 and QB.
114 and the reference voltage Vref to obtain a comparison output OUT. Note that the output potential vR of the potential generation means is equal to the threshold voltage vTn6+VT of the transistor Q6tQ7.
R7 is smaller than the power supply voltage VCC, and the potential vR is larger than the reference voltage Vref, so the following equation (1)
, has the relationship shown in (2).

ＶＴＲ６＋　ＶＴＲ７＜　ＶＢ　＜　ＶＣＣ−・・（１
）Ｖｒｅｆ　＜　ＶＲ＜　ＶＣＣ・・・・・・・・・・
・・・・・・・・・・・（２）次に、上記のような構成
において動作を説明する。今、入力信号ＤＩＨの電位Ｖ
Ｄを、Ｑ　Ｖ、基準電圧Ｖｒａｆを１．ＯＶ、）ランジ
スタＱｓ　、Ｑｙのしきい値電圧ｖＴＨ６＋　ＶＴＲ７
をそレ−ｔ’し０．５Ｖ、の電位は、トランジスタＱ７
−　Ｑ９の導通抵抗、′−゛、ソ。VTR6+ VTR7<VB<VCC-...(1
)Vref<VR<VCC・・・・・・・・・・
(2) Next, the operation in the above configuration will be explained. Now, the potential V of the input signal DIH
D, QV, and reference voltage Vraf are 1. OV, ) Threshold voltage of transistors Qs, Qy vTH6+ VTR7
The potential of 0.5V is the voltage of transistor Q7.
- Continuity resistance of Q9, '-゛, so.

はぼ入力信号電位ＶＤ（０■）つまりＬ”レベルとなる
。一方、入力信号電位ＶＤがｖＲからトランジスタＱ６
のしきい値電圧を引いた電圧を越えるとトランジスタＱ
６はオフ状態となり、トランジスタＱ７はオン状態が維
持される。従って、接続点Ｎｌは前記所定電位が維持さ
れ、出力信号ＯＵＴは電源電圧Ｖｃｃ（”Ｈ″レベルと
なる。The input signal potential VD (0■), that is, becomes the L" level. On the other hand, the input signal potential VD changes from vR to the transistor Q6.
When the voltage exceeds the threshold voltage of transistor Q
6 is turned off, and transistor Q7 is maintained on. Therefore, the connection point Nl is maintained at the predetermined potential, and the output signal OUT becomes the power supply voltage Vcc (“H” level).

このような構成によれば、Ｎチャネル形のＭＯＳ　）ラ
ンジスタＱ６　、ＱｙおよびＰチャネル形のＭＯＳ　）
ランジスタＱ８．．Ｑ９のダートとバックダート間の′
重圧は、同一′４電形の間では同じであり、たとえ放射
線が照射されてしきい値電圧が変化してもセンスアンプ
の対称性が失なわれることはなく、安定で高感度な動作
を行なえる。According to such a configuration, N-channel type MOS) transistors Q6, Qy and P-channel type MOS)
Ransistor Q8. ．． Between Q9 dirt and back dirt'
The pressure is the same between the same '4 voltage types, and even if the threshold voltage changes due to radiation irradiation, the symmetry of the sense amplifier will not be lost, allowing stable and highly sensitive operation. I can do it.

這を供給しても良い。この場合の動作を、入・力怖号１
）ｒＮの電位ＶＤ−１，５ｖ、入力信号Ｉの電”ｋ　Ｖ
ｉ　：＝　２．５　Ｖ　、ＶＢ　＝　３　Ｖ　ＩＶＴＨ
６＝　ＶＴＲ７＝０−１．“８■として説明する。この
とき、トランジスタ′Ｑｓはオン状態、Ｑ７はオフ状態
となシ、接続点Ｎ、は゛１１″レベル（Ｖｃｃ−ＩＶＴ
Ｈ９１）となって、トランジスタＱ９の導通抵抗を高く
する。You can also supply the fish. The operation in this case is input/input fear number 1.
)rN potential VD-1,5v, input signal I voltage "kV
i := 2.5 V, VB = 3 V IVTH
6=VTR7=0-1. At this time, the transistor 'Qs is in the on state, Q7 is in the off state, and the connection point N is at the "11" level (Vcc-IVT
H91), increasing the conduction resistance of transistor Q9.

これによって出力信号ＯＵＴは入力信号電圧ＶＤ（１，
５Ｖ）とほぼ等しくなる。一方、電位Ｖ。As a result, the output signal OUT becomes the input signal voltage VD (1,
5V). On the other hand, the potential V.

＝２．５ｖ、ｖτ＝　１．５　Ｖとな７ると、トランジ
スタＱ６がオフ状態％Ｑ７がオン状態に反転し、接続点
Ｎ、はほぼ入力信号電圧■五（１，５Ｖ）となり、トラ
ンジスタＱＢの導通抵抗が低下して出力信号ＯＵＴはほ
ぼＶＣＣレベルとなる。= 2.5 V, vτ = 1.5 V, transistor Q6 is turned off, Q7 is turned on, and the connection point N becomes almost the input signal voltage 5 (1.5 V), and the transistor The conduction resistance of QB decreases and the output signal OUT becomes approximately at the VCC level.

第４図は、この発明の他の実施例を示すもので、前記第
３図におけるトランジスタＱｓ＋Ｑ９のダートをそれぞ
れ、トランジスタＱ７とＱ９との接続点Ｎ１およびトラ
ンジスタＱ８とＱ６との接続点Ｎ２に交差接続したもの
である。FIG. 4 shows another embodiment of the present invention, in which the darts of transistors Qs+Q9 in FIG. It is connected.

図において、前記第３図と同一構成部には同じ符号を伺
してその説明は省略する。上記のようによってトランジ
スタＱ９の導通抵抗が低下し、接続点Ｎ１は”■”レベ
ルとなり、ＮｌのＨ”レベルによってトランジスタＱＢ
の導通抵抗が高くなる。一方、入力信号電圧ＶＤが基準
電圧Ｖｒ、ｆよυ高くなると、トランジスタＱ６はオフ
状態となり、トランジスタＱ７はオン状態が維持される
。従って、接続点Ｎ１はｖｒｏｆとなシ、出力信号ＯＵ
ＴはＶｃｃ（”Ｈ”レベル）となる。In the figure, the same components as those in FIG. As described above, the conduction resistance of the transistor Q9 decreases, the connection point N1 becomes the "■" level, and the H level of Nl causes the transistor QB
conduction resistance increases. On the other hand, when the input signal voltage VD becomes higher than the reference voltages Vr and f, the transistor Q6 turns off and the transistor Q7 remains on. Therefore, the connection point N1 is connected to vrof, and the output signal OU
T becomes Vcc (“H” level).

このような構成においては、Ｐチャネル形のＭＯＳ　）
ランジスタＱａ　、Ｑ９は、ダートに印加される電圧が
異なるため、このトランジスタＱｓ　、Ｑ９の放射線照
射によるしきい値電圧の変化量は異なり、センス回路の
対称性が多少失なわれるが、前記第１図の回路に比べて
その程度は少ない。とれは、Ｐチャネル形ＭＯ３）ラン
ソスタＱｓ　、Ｑ９のバイアス条件は、ダート電圧が常
にバックケ゛−ト電圧より低いために放射線によるしき
い値電圧のシフト量がＮチャネル形よシＰチャネル形の
方が小さいためであり、Ｎチャネル形ＭＯ８）ランジス
タＱ６．Ｑ７のしき安定で高感度な動作を行なえる耐放
射線性に優れたセンスアンプ回路が得られる。In such a configuration, P-channel type MOS)
Since the voltages applied to the darts of the transistors Qa and Q9 are different, the amount of change in the threshold voltage of the transistors Qs and Q9 due to radiation irradiation is different, and the symmetry of the sense circuit is somewhat lost. The degree of this is less compared to the circuit shown in the figure. This is because the bias conditions for the P-channel type MO3) Lansostar Qs and Q9 are such that the dart voltage is always lower than the backgate voltage, so the shift amount of the threshold voltage due to radiation is greater in the P-channel type than in the N-channel type. This is because it is small, and the N-channel type MO8) transistor Q6. A sense amplifier circuit with excellent radiation resistance that can perform more stable and highly sensitive operation than Q7 can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図および第２図はそれぞれ従来のセンスアンプ回路
を説明するだめの図、第３図はこの発明の一実施例に係
るセンスアンプ回路を示す図、第４図はこの発明の他の
実施例を説明するだめの回路図である。 ｖＲ・・・第１電位供給源、１２・・・信号入力端子、
ＤＩＮ・・・入力信号、１３・・・基準電圧端子、Ｖｒ
ｅｆ・・・基準電圧、Ｑａ　、Ｑ？・・・第１．第２ト
ランジスタ、１ノ・・・電源端子、Ｖｃｃ・・・電源、
Ｑ８゜Ｑ９・・・第３．第４トランジスタ、ＯＵＴ・・
・出力信号。 出願人　工業技術院長　川　１）裕　部第３図 ＯｔＪＴ1 and 2 are diagrams for explaining a conventional sense amplifier circuit, respectively, FIG. 3 is a diagram showing a sense amplifier circuit according to an embodiment of the present invention, and FIG. 4 is a diagram showing another embodiment of the present invention. FIG. 2 is a circuit diagram for explaining an example. vR...first potential supply source, 12...signal input terminal,
DIN...Input signal, 13...Reference voltage terminal, Vr
ef...Reference voltage, Qa, Q? ...First. 2nd transistor, 1no...power supply terminal, Vcc...power supply,
Q8゜Q9...3rd. 4th transistor, OUT...
・Output signal. Applicant: Director of the Agency of Industrial Science and Technology Kawa 1) Hirobe Figure 3 OtJT

Claims (3)

【特許請求の範囲】[Claims] （１）一端から入力信号あるいは基準電圧がそ一トに所
定電位を印加して導通設定する電位発”１１給手段とを
具備し、上記第１あるいは第２　ＭＯＳ：１ トランジスタの他端から出力を得る如く構成したことを
特徴とするセンスアンプ回路。(1) The input signal or the reference voltage is provided from one end of the first or second MOS transistor by applying a predetermined potential thereto to set the conduction. A sense amplifier circuit characterized in that it is configured to obtain the following. （２）上記電流供給手段は、上記一対の入力用第１．第
２Ｍ０Ｓトランノスクの他端と電源間にそれぞれ挿接さ
れる第２導電形の第３．第４ＭＯ８）ランジスタを備え
、これら第３．第４ＭＯ８）ランノスタのダートは共通
接続されて第１、第３　ＭＯＳ　）ランジスクの接続点
あるいは第２．１４Ｍ０８）ランジスタの接続点の一方
に接続され、パックゲートがそれぞれ電源に接続されて
成ることを特徴とする特許請求の範囲第１項記載のセン
スアンプ回路。(2) The current supply means includes the pair of input first . The third conductivity type is inserted between the other end of the second M0S transnosk and the power supply. 4th MO8) transistor, and these 3rd MO8) transistors. The darts of the 4th MO8) lannostar are connected in common and connected to the connection point of the 1st and 3rd MOS transistors or the connection point of the 2.14th MO8) transistor, and the pack gates are connected to the power supply respectively. A sense amplifier circuit according to claim 1, characterized in that: （３）上記電流供給手段は、上記一対の入力用第１．第
２Ｍ０８）ランジスタの他端と電源間にそれぞれ挿接さ
れる第２斗電形の第３．第４Ｍ０Ｓトランジスタを備え
、上記第３Ｍ０Ｓトラ／ジスタのケ８−トは第２．第４
　ＭＯＳ　）ランジスタ(3) The current supply means includes the pair of input first . 2nd M08) The 3rd M08 of the 2nd M08) is inserted between the other end of the transistor and the power supply. A fourth MOS transistor is provided, and the third MOS transistor/transistor has a second gate. Fourth
MOS) transistor
JP58160263A 1983-09-02 1983-09-02 Sense amplifying circuit Granted JPS6052996A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58160263A JPS6052996A (en) 1983-09-02 1983-09-02 Sense amplifying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58160263A JPS6052996A (en) 1983-09-02 1983-09-02 Sense amplifying circuit

Publications (2)

Publication Number Publication Date
JPS6052996A true JPS6052996A (en) 1985-03-26
JPH0159679B2 JPH0159679B2 (en) 1989-12-19

Family

ID=15711218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58160263A Granted JPS6052996A (en) 1983-09-02 1983-09-02 Sense amplifying circuit

Country Status (1)

Country Link
JP (1) JPS6052996A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4713797A (en) * 1985-11-25 1987-12-15 Motorola Inc. Current mirror sense amplifier for a non-volatile memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4713797A (en) * 1985-11-25 1987-12-15 Motorola Inc. Current mirror sense amplifier for a non-volatile memory

Also Published As

Publication number Publication date
JPH0159679B2 (en) 1989-12-19

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