JPS604328A - Integrated circuit - Google Patents
Integrated circuitInfo
- Publication number
- JPS604328A JPS604328A JP58110906A JP11090683A JPS604328A JP S604328 A JPS604328 A JP S604328A JP 58110906 A JP58110906 A JP 58110906A JP 11090683 A JP11090683 A JP 11090683A JP S604328 A JPS604328 A JP S604328A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- input
- output
- integrated circuit
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
- H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の利用分野〕 この発明は集積回路に関するものである。[Detailed description of the invention] [Field of application of the invention] This invention relates to integrated circuits.
従来の集積回路では、(り集積(ロ)路外部から与えら
れたクロックパルスを、そのまま内部で使用する形式の
ものと、(2)来&回路内部に第1図で示すようなりロ
ックパルス幅補正回路を設け、外部から与んられたクロ
ックパルスを内部で使用するのに過当なパルス幅を待つ
クロックパルスに変渓した後、使用する形式のものが存
在する。In conventional integrated circuits, there are two types of integrated circuits: (2) A type in which a clock pulse given from outside the circuit is used internally as is, and (2) A type in which a clock pulse given from outside the circuit is used internally as is. There is a type of clock pulse in which a correction circuit is provided and the clock pulse applied from the outside is changed to a clock pulse that waits for an appropriate pulse width to be used internally before being used.
第1図において、集積回路の外部から与えられタフロッ
クパルスは入カバッファ回’Nr1’21#C。In FIG. 1, the tough lock pulse applied from outside the integrated circuit is input to the input buffer circuit 'Nr1'21#C.
M地回に@2と出力1gl鮎3に分配される。遅延回路
2に人力したタロツクパルスは必要なパルス幅分の時間
が経過した後回路2を出力し、回路3に入力する。回路
3の出力は端子310人力極性が論理11“でかつ端子
32020人力極性理′0“である間だけ論理10“と
なる。従って回路10人力に加えられた論理11“から
、1iiIi!′O“へ変化する信号は、10回路2の
−M延時間と等しいパルス幅を持つパルスに変換され回
路3から出力される。It is distributed to @2 and output 1gl sweetfish 3 in M earth cycle. The tarok pulse inputted into the delay circuit 2 is outputted from the circuit 2 after a time corresponding to the necessary pulse width has elapsed, and inputted into the circuit 3. The output of the circuit 3 becomes logic 10" only while the terminal 310 human power polarity is logic 11" and the terminal 32020 human power polarity is '0". Therefore, from the logic 11" added to the circuit 10 human power, 1iiiIi! The signal changing to 'O'' is converted into a pulse having a pulse width equal to the -M delay time of the 10 circuits 2 and outputted from the circuit 3.
次に従来方式の間趙点を述べる。形式(りの集積回路を
用いる場合、集積回路外部で発生させたクロックパルス
を復数の集積回路に分配する際に生じる波形のなまり、
伝送祿路遅延等の要因によるパルス幅のばらつき、位相
のすれに対応するため、クロックパルスのタイミンクに
充分な余裕を持たす必要が有り、これは論理回路の高速
化に悴い無視できない遅延要因となってきた。Next, we will discuss the conventional method. When using an integrated circuit, the waveform is rounded, which occurs when a clock pulse generated outside the integrated circuit is distributed to multiple integrated circuits.
In order to cope with variations in pulse width and phase shifts due to factors such as transmission path delays, it is necessary to provide sufficient margin in the timing of clock pulses, and this is a delay factor that cannot be ignored as logic circuits become faster. It has become.
形式(2)の集積回路を用いると、外部から与えられた
クロックのパルス幅をも集積回路内部lこおG)て′−
1気的に心安十分なパルス幅に変換できるためパルス幅
のばらつきに対するタイミンクの余裕が不要となり、形
式(りの乗積回路に軟べてより烏速な論理回路が央現で
きる反面、図1のクロックパルス幅補正回路の構造上明
らかなように該補正回路を通し集積回路内部に分配され
るクロック信号を任意の極性に固足することが不可能と
なる。When using an integrated circuit of type (2), the pulse width of the externally applied clock can also be controlled internally within the integrated circuit.
Since the pulse width can be converted into a pulse width that is safe and sufficient, there is no need for a timing margin for variations in pulse width, and on the other hand, a much faster logic circuit can be realized by converting it into a multiplication circuit of the form (Fig. 1). As is clear from the structure of the clock pulse width correction circuit, it is impossible to fix the clock signal distributed inside the integrated circuit through the correction circuit to an arbitrary polarity.
これは集積回路の故障検査上次の点で問題となる。匠米
果槓回路の故障検査の方法として集積回路内部のクロッ
ク・18°号の極性を固定し、フリップフロップの入力
がその才ま出力に通り抜ける状態にした後、集積回路外
部から各m組合わせの検査データを入力し、出力を期待
fitと比軟する方法が検査効率、故障検出率の点で優
れているとされているのに対し、クロック悟+3を任意
の極性に固定できないと、他の検査効率、故障偵出率の
劣る方法を用いて故障検査を行わなくてはならす、検査
工数、製品の信頼性の点で問題か生じる。This poses a problem in the following respects for failure testing of integrated circuits. As a fault inspection method for the circuit, after fixing the polarity of the clock No. 18° inside the integrated circuit and making it so that the input of the flip-flop passes through its output, each m combination is detected from outside the integrated circuit. The method of inputting test data and comparing the output with the expected fit is said to be superior in terms of test efficiency and failure detection rate. Failure testing must be performed using a method with poor testing efficiency and fault detection rate, resulting in problems in testing man-hours and product reliability.
この発明の目的は上記の如き従来の問題点を除去するこ
とであり、クロック入力’) Win 91. ’ 0
“または論理′1“に固定すると、入力信号かその才ま
出力に抜ける形式のフリップ・フロップを用い、かつク
ロックパルス嘱袖止(ロ)路を6部に設けた集積回路に
対し、検査データ作成の困難さ、故障検出率の低さとい
う欠点を完全に解消できる集積回路を提供することにあ
る。The purpose of the present invention is to eliminate the above-mentioned problems of the conventional technology. ' 0
If it is fixed to "or logic '1", test data will be generated for an integrated circuit that uses a flip-flop that connects the input signal to its output and has a clock pulse start and stop path in the sixth section. The object of the present invention is to provide an integrated circuit that can completely eliminate the drawbacks of difficulty in manufacturing and low failure detection rate.
この発明の%徴とするところは、集積回路外部から固定
指示信号を与えることにより、外部から入力したクロッ
ク信号かその該ま出力に通り抜ける機能を持つクロック
パルス幅袖正向路を集積回路内部に設けた点にある。The feature of this invention is that by applying a fixed instruction signal from outside the integrated circuit, a clock pulse width forward path is created inside the integrated circuit, which has the function of passing through the externally input clock signal or its corresponding output. It is at the point that I have set.
以下、本発明の一実施例を図を用いて説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第2図は本発明を実施したときの集積回路上に設けられ
たタロツクパルス幅袖正回路の回路図を示している。FIG. 2 shows a circuit diagram of a tally clock pulse width correction circuit provided on an integrated circuit when the present invention is implemented.
図において、入力バッファ回路40入力は集積回路の外
部に設けられたクロック信号入力端子に接vr、され、
出力は出力NAND回路60入力端子601と遅延回路
5へ徽続されている。回路5の出力は回路60入力端子
602へ接続され1g回路6の出力は内部クロックとし
て集積回路内の谷部へ分配される。In the figure, the input buffer circuit 40 input is connected to a clock signal input terminal provided outside the integrated circuit,
The output is connected to the output NAND circuit 60 input terminal 601 and the delay circuit 5. The output of circuit 5 is connected to circuit 60 input terminal 602 and the output of 1g circuit 6 is distributed to the valleys within the integrated circuit as an internal clock.
−M延回路5は、入力より銅にインバータ51,52゜
1”J A N ])回路53へと接続され、回路53
の出力が[1路5の出力となる。回路5へ入力したfK
−号が回路5より出力するのに要1−る時間が、内部ク
ロックに臂求されるパルス幅と等しくなるように猶成さ
れている。The -M extension circuit 5 is connected to the inverter 51, 52゜1" J A N ]) circuit 53 from the input to the copper, and the circuit 53
The output becomes the output of [1 path 5. fK input to circuit 5
The time required for the - signal to be output from the circuit 5 is made equal to the pulse width required by the internal clock.
入力端子532は本発明1を夾施するために設けた固だ
指示13号用の入力で、集積回路の外部へり1き出され
でいる。The input terminal 532 is an input for a fixed instruction No. 13 provided to implement the present invention 1, and is extended to the outside of the integrated circuit.
第3図はクロックパルス1llj補正回路のタイタン外
チャー1・を示しており、横細を時間、縦軸は各回路の
入出力極性の動作8表わしている。FIG. 3 shows the titan outer char 1 of the clock pulse 1llj correction circuit, where the horizontal thin line represents time and the vertical axis represents input/output polarity operation 8 of each circuit.
(りは通常使用状態におけるタイミンクチャートであり
、固定指示信号は論理11“に固定しである。(This is a timing chart in a normal use state, and the fixed instruction signal is fixed at logic 11".
回路4に入力するクロック信号が時刻t1に論理′1“
から論理10“に変化すると、回路6(入力端子601
)と回路510入力は時刻t2に論理10“から論理′
1“Iこ変化する。このとき入力端子602は論理′1
“であるから回路6の出力は時刻t3に論理11“から
論理10“に変化する。回路51に入力した信号はパル
ス幅分の時間を要して回路53を出力し、時刻t5に端
子602の入力が論理′1“から論理10“に変化する
。この結果回路6の出力は時刻t6に論理′0“から論
理′1“に変化する。The clock signal input to the circuit 4 becomes logic '1'' at time t1.
to logic 10", circuit 6 (input terminal 601
) and the circuit 510 input changes from logic 10" to logic ' at time t2.
1"I changes. At this time, the input terminal 602 becomes logic '1'.
Therefore, the output of the circuit 6 changes from logic 11" to logic 10" at time t3.The signal input to the circuit 51 takes a time equal to the pulse width and is output from the circuit 53, and at time t5 the output from the circuit 602 changes from logic 11" to logic 10". As a result, the output of the circuit 6 changes from logic '0' to logic '1' at time t6.
以上の動作は既存のクロックパルス鴨袖正回路と同じで
あるが、動作原理から明らかなように回路6の出力を論
理10“に・固定不可能なため、従来は集積回路の故障
検出か元号にできないという問題があった。The above operation is the same as that of the existing clock pulse Kamosode positive circuit, but as is clear from the operating principle, it is impossible to fix the output of circuit 6 to logic 10'', so conventionally the fault detection of the integrated circuit was There was a problem that it could not be numbered.
(2)は本発明の特徴である故障検出時の動作を表わし
ている。固定指示信号は論理′0“に固足しであるので
、入力端子602は論理11“に―、足され、回路6は
インバータとして動作する。(2) represents the operation at the time of failure detection, which is a feature of the present invention. Since the fixed instruction signal is fixed at the logic '0', the input terminal 602 is added at the logic '11', and the circuit 6 operates as an inverter.
回路6の出力を論理′0“に固定するには、回路4に論
理′0“を入力すればよく、回路6の出力を*理11“
に固定するには回路4に論理′1″を入力すればよい。To fix the output of circuit 6 to logic '0', it is sufficient to input logic '0' to circuit 4, and the output of circuit 6 can be fixed to logic '0'.
In order to fix it to , it is sufficient to input logic '1'' to the circuit 4.
このように内部クロックの極性を集積回路の外部から自
由に指定可能となり、故障検量時にはクロックの極性を
固足しフリップ・フロップの入力がそのまま出力に通り
抜ける状態にして検査かできるため、検査データ作成か
容易になり、故障検出率も向上する。In this way, the polarity of the internal clock can be freely specified from outside the integrated circuit, and during fault verification, the polarity of the clock can be fixed and the input of the flip-flop can be passed through to the output as it is.This makes it easier to create test data. It becomes easier and the failure detection rate also improves.
本発明によれば、集積N路内に設けられたクロックパル
ス幅補正回路の出力を集積回路の外部から信号を与える
ことにより任意の極性に固定できるので、クロック入力
を調理% o −zたは論理11“に固定すると、入力
信号かそのまま出力に抜ける形式のフリップ・フロップ
を用いた集積回路に対して次の如き幼果を得ることがで
きる。According to the present invention, the output of the clock pulse width correction circuit provided in the integrated circuit can be fixed to any polarity by applying a signal from outside the integrated circuit. If the logic is fixed to 11'', the following result can be obtained for an integrated circuit using a flip-flop in which the input signal is directly passed through to the output.
1、 集積回路内部にクロックパルス幅補正回路を設け
ることにより、該乗積回路により構成されるシステム全
体としてみた場合クロックのパルス幅のばらつきを考慮
する必要がなくなり、その分クロック周期を短かくする
ことが可能となる。1. By providing a clock pulse width correction circuit inside the integrated circuit, it is no longer necessary to take into account variations in the clock pulse width when looking at the entire system made up of the multiplication circuit, and the clock period can be shortened accordingly. becomes possible.
2、集積回路内部にクロックパルス幅補正回路を設けた
場合に間組であった、故陣恢用時の検査データ作成困難
、故障検出率低下等の欠点を完全に解消可能となる。2. When a clock pulse width correction circuit is provided inside an integrated circuit, it is possible to completely eliminate the disadvantages such as difficulty in creating test data for late use and a decrease in failure detection rate.
第1図は従来の集積回路内m#こ設けられたパルス幅補
正(ロ)路の回路図、@2図は本発明の一実施例を示す
集積回路内部に設けられたパルス幅補正回路の回路図、
第3図は第2図に示したもののタイミングチャート図で
ある。
1・・・入力ハツファ 2・・・遅蜆回路3・・・出力
回路 4・・・入力バッファ回路5・・・遅姑回路 6
・・・出力回路
51・・・インバータ 52・・・インバータ代理人弁
理士 高 橋 明 1
53・・・NAND回路Figure 1 is a circuit diagram of a conventional pulse width correction circuit provided in an integrated circuit, and Figure 2 is a circuit diagram of a pulse width correction circuit provided in an integrated circuit showing an embodiment of the present invention. circuit diagram,
FIG. 3 is a timing chart diagram of what is shown in FIG. 2. 1... Input buffer 2... Delay circuit 3... Output circuit 4... Input buffer circuit 5... Delay circuit 6
... Output circuit 51 ... Inverter 52 ... Inverter representative patent attorney Akira Takahashi 1 53 ... NAND circuit
Claims (1)
たクロック信号を、内部で使用するのに′電気的に過当
なパルス幅を持つクロックパルスに変換し内部に分配す
る機能と、外部から与えられたクロック信号をそのま談
内部に分配する機能を、外部から与える信号により選択
することか可能な回路を内部に設けたことを特徴とする
集、fA回路。1. In an integrated circuit, there is a function to convert a clock signal applied from outside the branch circuit into a clock pulse having an electrically excessive pulse width for internal use, and to distribute it internally. What is claimed is: 1. An fA circuit, characterized in that a circuit is provided inside the circuit which allows the function of distributing a clock signal internally to the circuit to be selected by a signal applied from the outside.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58110906A JPS604328A (en) | 1983-06-22 | 1983-06-22 | Integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58110906A JPS604328A (en) | 1983-06-22 | 1983-06-22 | Integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS604328A true JPS604328A (en) | 1985-01-10 |
Family
ID=14547655
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58110906A Pending JPS604328A (en) | 1983-06-22 | 1983-06-22 | Integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS604328A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61142527U (en) * | 1985-02-22 | 1986-09-03 | ||
US8979464B2 (en) | 2008-09-05 | 2015-03-17 | Ntn Corporation | Production facility, and production system |
-
1983
- 1983-06-22 JP JP58110906A patent/JPS604328A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61142527U (en) * | 1985-02-22 | 1986-09-03 | ||
US8979464B2 (en) | 2008-09-05 | 2015-03-17 | Ntn Corporation | Production facility, and production system |
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