JPS6043021B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6043021B2 JPS6043021B2 JP55139475A JP13947580A JPS6043021B2 JP S6043021 B2 JPS6043021 B2 JP S6043021B2 JP 55139475 A JP55139475 A JP 55139475A JP 13947580 A JP13947580 A JP 13947580A JP S6043021 B2 JPS6043021 B2 JP S6043021B2
- Authority
- JP
- Japan
- Prior art keywords
- stage
- circuit
- electrode
- capacitance electrode
- lumped constant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6644—Packaging aspects of high-frequency amplifiers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】
この発明は３端子半導体チップを多段カスケード接続
する内部整合化多段増幅用の半導体装置に関するものて
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device for internal matching multi-stage amplification in which three-terminal semiconductor chips are connected in multi-stage cascade.
第１図は従来の内部整合化多段増幅用の半導体装置を
示す要部斜視図てあり、説明を簡単にするため、ソース
接地型砒化ガリウム電界効果トランジスタ（以下ＧａＡ
ｓＦＥＴと言う）を２段カスケード接続した場合を用い
て説明する。FIG. 1 is a perspective view of the main parts of a conventional semiconductor device for internally matched multi-stage amplification, and for the sake of simplicity, source-grounded gallium arsenide field effect transistors (hereinafter referred to as GaA
This will be explained using a case where two stages of sFETs are connected in cascade.
同図において、１は半導体チップ、２は入力整合用キャ
パシタ電極、３はこの入力整合用キャパシタ電極２を表
面に形成した第１の誘電体基板、４は出力整合用キャパ
シタ電極、５はこの出力整合用キャパシタ電極４を表面
に形成した第２の誘電体基板、６は第１の誘電体基板３
および第２の誘電体基板５が接着により固定された接地
用金属基板、７は半導体チップ１上に形成したゲート電
極パッド、８はこのゲート電極パッド７と入力整合用キ
ャパシタ電極２を接続する第１のボンディングワイヤ、
９は第１のセラミック基板、１０はこの第１のセラミッ
ク基板９上に形成した第１の分布定数線路、１１は入力
整合用キャパシタ電極２と第１の分布定数線路１０とを
接続する第２のボンディングワイヤ、１２は半導体チッ
プ１上に形成したドレイン電極、１３はこのドレイン電
極１２と出力整合用キャパシタ電極４とを接続する第３
のボンディングワイヤ、１４は第２のセラミック基板、
１５はこの第２のセラミック基板１４上に形成した第２
の分布定数線路、１６は出力整合用キャパシタ電極４と
第２の分布定数線路１５とを接続する第４のボンディン
グワイヤである。 なお、入力整合回路は第１のボンデ
ィングワイヤ８による集中定数インダクタンスＬｉ、入
力整合用キャパシタ電極２による集中定数キャパシタン
スＣｌ、第２のボンディングワイヤ１１による集中定数
インタグタンスＬ。In the figure, 1 is a semiconductor chip, 2 is an input matching capacitor electrode, 3 is a first dielectric substrate on which the input matching capacitor electrode 2 is formed, 4 is an output matching capacitor electrode, and 5 is this output. A second dielectric substrate on which a matching capacitor electrode 4 is formed; 6 is a first dielectric substrate 3;
and a grounding metal substrate to which a second dielectric substrate 5 is fixed by adhesive; 7 is a gate electrode pad formed on the semiconductor chip 1; 8 is a grounding metal substrate for connecting the gate electrode pad 7 and the input matching capacitor electrode 2; 1 bonding wire,
9 is a first ceramic substrate, 10 is a first distributed constant line formed on this first ceramic substrate 9, and 11 is a second line that connects the input matching capacitor electrode 2 and the first distributed constant line 10. 12 is a drain electrode formed on the semiconductor chip 1, and 13 is a third bonding wire connecting this drain electrode 12 and the output matching capacitor electrode 4.
14 is a second ceramic substrate,
15 is a second ceramic substrate formed on this second ceramic substrate 14.
The distributed constant line 16 is a fourth bonding wire that connects the output matching capacitor electrode 4 and the second distributed constant line 15. The input matching circuit has a lumped constant inductance Li formed by the first bonding wire 8, a lumped constant capacitance Cl formed by the input matching capacitor electrode 2, and a lumped constant intagtance L formed by the second bonding wire 11.
からなる一段フィルタにより構成される。また、出力整
合回路は第３のボンディングワイヤ１３による集中定数
インダクタンスＬ３、出力整合用キャパシタ電極４によ
る集中定数キャパシタンスＣ２、および第４のボンディ
ングワイヤ１６による集中定数インダクタンスＬ。から
なる一段フィルタにより構成される。 そして、上記の
ように構成した内部整合化３端子半導体素子を２段カス
ケード接続して増幅利得の増大を図る場合には第２図に
示すように、第１の内部整合化素子ＴＲｌおよび第２の
内部整合化素子ＴＲ２を外部に配設したセラミック基板
１７上に形成したＭＩＣ線路１８により接続する方法が
とられている。It is composed of a single-stage filter consisting of. The output matching circuit has a lumped constant inductance L3 formed by the third bonding wire 13, a lumped constant capacitance C2 formed by the output matching capacitor electrode 4, and a lumped constant inductance L formed by the fourth bonding wire 16. It is composed of a single-stage filter consisting of. In order to increase the amplification gain by cascading the internally matched three-terminal semiconductor devices configured as described above in two stages, as shown in FIG. A method is used in which the internal matching element TR2 is connected by an MIC line 18 formed on a ceramic substrate 17 disposed outside.
なお、第２図において破線で囲まれたバイアス回路１９
および２０はそれぞれ第１の内部整合化素子ＴＲｌのド
レインバイアス回路および第２の内部整合化素子ＴＲ２
のゲートバイアス回路で、個々のバイアス回路１９およ
び２０を前記ＭＩＣ線路１８に形成したスリット２１を
またいで配設したチップコンデンサ２２により分離して
いる。In addition, the bias circuit 19 surrounded by a broken line in FIG.
and 20 are the drain bias circuit of the first internal matching element TRl and the second internal matching element TR2, respectively.
In this gate bias circuit, individual bias circuits 19 and 20 are separated by a chip capacitor 22 disposed across a slit 21 formed in the MIC line 18.
しかしながら、従来の内部整合化３端子半導体素子を外
部回路によりカスケード接続し、多段増幅回路を形成す
る半導体装置では外部回路の寸法をある限界値以下にま
で小さくすることができないため、増幅回路全体の寸法
が大きくなり、多段増幅回路モジュールの小型、軽量化
に対する障壁となつていた。However, in conventional semiconductor devices in which internally matched three-terminal semiconductor elements are cascade-connected by an external circuit to form a multistage amplifier circuit, the dimensions of the external circuit cannot be reduced below a certain limit, so the size of the entire amplifier circuit cannot be reduced. The increased dimensions have been a barrier to making multi-stage amplifier circuit modules smaller and lighter.
また、動作周波数がマイクロ波帯以上の超高周波領域に
なつてくると、ＭＩＣ分布定数線路やチップコンデンサ
などの外部回路自体の回路損失が急激に増大し、多段増
幅回路全体の増幅利得が減少する。一方このような超高
周波帯では半導体チップの全ゲート幅が増大するにした
がい、チップ自身の入出力インピーダンスが極端に低減
するために、個々の内部整合化半導体素子の帯域特性が
狭帯域となつており、この狭帯域特性を有する半導体素
子を大きな電気長を有する外部回路を用いて接続するこ
とにより、増幅回路全体の増幅利得の周波数特性がます
ます狭帯域化し、マイクロ波帯における広帯域増幅器の
製作に対するネックとなるなどの欠点があつた。したが
つて、この発明の目的は小型軽量で、しかも高利得て、
広帯域な半導体装置を提供するものてある。Furthermore, when the operating frequency reaches the ultra-high frequency region above the microwave band, the circuit loss of external circuits such as MIC distributed constant lines and chip capacitors increases rapidly, and the amplification gain of the entire multistage amplifier circuit decreases. . On the other hand, in such ultra-high frequency bands, as the total gate width of a semiconductor chip increases, the input/output impedance of the chip itself is extremely reduced, resulting in the band characteristics of each internally matched semiconductor element becoming narrower. By connecting semiconductor elements with this narrowband characteristic using an external circuit with a large electrical length, the frequency characteristic of the amplification gain of the entire amplifier circuit becomes increasingly narrowband, making it possible to create a wideband amplifier in the microwave band. There were drawbacks such as being a bottleneck to the system. Therefore, the purpose of this invention is to provide a small and lightweight device with high gain.
There are devices that provide broadband semiconductor devices.
このような目的を達成するため、この発明は前段の出力
整合回路を構成する第１の集中定数キャパシタンス電極
と後段の入力整合回路を構成する第２の集中定数キャパ
シタンス電極とを同一の誘電体基板上に形成し、かつ第
１の集中定数キャパシタンス電極と第２の集中定数キャ
パシタンス電極とを幅の細いスリット部をはさんで配設
するものであり、以下、実施例を用いて詳細に説明する
。In order to achieve such an object, the present invention provides a first lumped constant capacitance electrode constituting the output matching circuit in the preceding stage and a second lumped constant capacitance electrode constituting the input matching circuit in the subsequent stage on the same dielectric substrate. A first lumped constant capacitance electrode and a second lumped constant capacitance electrode are disposed on both sides of a narrow slit, and will be described in detail below using examples. .
第３図はこの発明に係る半導体装置の一実施例を示す要
部斜視図であり、一例としてＧａＡｓＦＥＴの第１の半
導体チップ１Ａおよび第２の半導体チップ１Ｂを集中定
数内部整合エレメントを用いて接続して内部整合化２段
増幅回路を形成したものである。FIG. 3 is a perspective view of a main part showing an embodiment of a semiconductor device according to the present invention, and as an example, a first semiconductor chip 1A and a second semiconductor chip 1B of GaAsFET are connected using a lumped constant internal matching element. In this case, an internally matched two-stage amplifier circuit is formed.
同図において、２３は第２の半導体チップ１Ｂ上に形成
したソース電極バッド、２４は第２の半導体チップ１Ｂ
上に形成したドレイン電極バッド、２５は第３の誘電体
基板、２６はこの第３の誘電体基板２５上に形成した第
１のキャパシタンス電極、２７は第１の半導体チップ１
Ａ上に形成した第１のドレイン電極バッド、２８は第１
のキャパシタンス電極２６と第１のドレイン電極バッド
２７とを接続する第１のボンディングワイヤ、２９は第
３の誘電体基板２５上に形成した第２のキャパシタンス
電極、３０は第２の半導体チップ１Ｂ上に形成した第２
のゲート電極バッド、３１は第２のキャパシタンス電極
２９と第２のゲート電極バッド３０との間を接続する第
２のボンディングワイヤ、３２は第３の誘電体基板２５
上で電極パターンのない幅の狭いスリット部、３３は第
１段目回路のドレインバイアス端子、３４は第１のキャ
パシタンス電極２６とドレインバイアス端子３３との間
を接続するボンディングワイヤ、３５は第２段目回路の
ゲートバイアス端子、３６は第２のキャパシタンス電極
２９とゲートバイアス端子３５との間を接続するボンデ
ィングワイヤである。なお、第１の半導体チップ１Ａは
第１段目の回路を構成し、第２の半導体チップ１Ｂは第
２段目の回路を構成する。また、第４図は第３図に示す
半導体装置の等価回路てあり、この等価回路を用いて第
３図の半導体装置の構成を説明する。ます、第１段目の
出力内部整合回路は第３の誘電体基板２５上に形成した
第１のキャパシタンス電極２６によるキャパシタンスＣ
２″および第５のボンディングワイヤ２８によるインダ
クタンス！″より構成される。第２段目の入力内部整合
回路は第３の誘電体基板２５上に形成した第２のキャパ
シタンス電極２９によるキャパシタンスＣ／および第６
のボンディングワイヤ３１によるインダクタンスＬ４″
より構成される。また、第１のキャパシタンス電極２６
とは第２のキャパシタンス電極２９とは第３の誘電体基
板２５上で電極パターンのない幅の狭いスリット部３２
を介して互に向いあつて配置されている。このため、直
流的には第１段目の回路と第２段目の回路とは完全に分
離される。したがつて、このスリット部３２の幅を百ミ
クロンのオーダー以下にまで細くすることによつて、第
１のキャパシタンス電極２６および第２のキャパシタン
ス電極２９の間に、あるキャパシタンス値をもつたギャ
ップコンデンサＣ３が形成する。そして、上記誘電体基
板２５の誘電率が大きいため、動作周波数がマイクロ波
帯のような超高周波帯の場合にはギャップコンデンサＣ
３の容量値はギャップコンデンサＣ３によるリアクタン
ス成分士がほとんど無視できる程度の大きな値ωＣ３を
とることができる。In the figure, 23 is a source electrode pad formed on the second semiconductor chip 1B, and 24 is a source electrode pad formed on the second semiconductor chip 1B.
25 is the third dielectric substrate; 26 is the first capacitance electrode formed on the third dielectric substrate 25; 27 is the first semiconductor chip 1;
A first drain electrode pad 28 is formed on the first drain electrode pad A.
29 is a second capacitance electrode formed on the third dielectric substrate 25, 30 is on the second semiconductor chip 1B. The second formed in
31 is a second bonding wire connecting between the second capacitance electrode 29 and the second gate electrode pad 30; 32 is a third dielectric substrate 25;
At the top, there is a narrow slit portion without an electrode pattern, 33 is a drain bias terminal of the first stage circuit, 34 is a bonding wire connecting between the first capacitance electrode 26 and the drain bias terminal 33, and 35 is a second The gate bias terminal 36 of the stage circuit is a bonding wire connecting between the second capacitance electrode 29 and the gate bias terminal 35. Note that the first semiconductor chip 1A constitutes a first stage circuit, and the second semiconductor chip 1B constitutes a second stage circuit. Further, FIG. 4 shows an equivalent circuit of the semiconductor device shown in FIG. 3, and the configuration of the semiconductor device shown in FIG. 3 will be explained using this equivalent circuit. First, the output internal matching circuit of the first stage has a capacitance C formed by the first capacitance electrode 26 formed on the third dielectric substrate 25.
2'' and an inductance !'' by the fifth bonding wire 28. The second stage input internal matching circuit has a capacitance C/ and a sixth capacitance formed by the second capacitance electrode 29 formed on the third dielectric substrate 25.
Inductance L4'' due to the bonding wire 31
It consists of In addition, the first capacitance electrode 26
What is the second capacitance electrode 29? A narrow slit portion 32 without an electrode pattern on the third dielectric substrate 25
They are arranged facing each other through the. Therefore, the first stage circuit and the second stage circuit are completely separated from each other in terms of direct current. Therefore, by narrowing the width of this slit portion 32 to less than the order of 100 microns, a gap capacitor having a certain capacitance value can be formed between the first capacitance electrode 26 and the second capacitance electrode 29. C3 forms. Since the dielectric substrate 25 has a large dielectric constant, when the operating frequency is in an ultra-high frequency band such as a microwave band, the gap capacitor C
The capacitance value of 3 can take a large value ωC3 to the extent that the reactance component due to the gap capacitor C3 can be almost ignored.
また、ボンディングワイヤ３４および３５によるインダ
クタンス値を十分大きな値にすることにより、ＲＦチョ
ーク回路を形一成する。また、第４図において、破線で
囲んだ第１段目の半導体チップ１Ａを用いた増幅回路Ａ
と破線で囲んだ第２段目の半導体チップ１Ｂを用いた増
幅回路ＢとはキヤプコンデンサＣ３によつて直流的には
分離し、ＲＦ的に接続した構造になつている。このよう
に構成した内部整合化半導体装置では第１段目の出力整
合回路の第１のキャパシタンス電極２６と第２段目の入
力整合回路の第２のキャパシタンス電極２９とを同一の
平板状の誘電体基板２５上に形成し、かつ、第１のキャ
パシタンス電極２６と第２のキャパシタンス電極２９の
間に細いスリットを形成することによリギヤプコンデン
サを形成するので、第１段目の出力整合回路と第２段目
の入力整合回路とを直流的に分離すると共にＲＦ的には
密結合した構成になるので、段間にＭＩＣ線路の゛よう
な外部回路を挿入する必要がなくなる。Further, by setting the inductance value of the bonding wires 34 and 35 to a sufficiently large value, an RF choke circuit is formed. In addition, in FIG. 4, an amplifier circuit A using the first stage semiconductor chip 1A surrounded by a broken line
The amplifying circuit B using the second stage semiconductor chip 1B, which is surrounded by a broken line, is separated in terms of DC by a capacitor C3 and connected in terms of RF. In the internally matched semiconductor device configured in this way, the first capacitance electrode 26 of the first stage output matching circuit and the second capacitance electrode 29 of the second stage input matching circuit are connected to the same flat dielectric. Since a re-gap capacitor is formed by forming a narrow slit on the body substrate 25 and between the first capacitance electrode 26 and the second capacitance electrode 29, the first stage output matching circuit Since the second stage input matching circuit and the second stage input matching circuit are separated in terms of direct current and closely coupled in terms of RF, there is no need to insert an external circuit such as a MIC line between the stages.
このため、第１の半導体チップ１Ａと第２の半導体チッ
プ１Ｂとを近接して配置することがてきる。その結果、
２段増幅回路の増幅利得の周波数特性を著しく広帯域に
することができる。しかも、外部回路のＭＩＣ線路およ
び段間の直流分離用チップコンデンサに起因する回路損
失が完全に除去できるので、回路全体の増幅利得が増大
すると共に回路寸法および重量を軽量化することができ
る。なお、以上の実施例では２個の半導体チップをカス
ケード接続した２段増幅素子の場合について説明したが
、これに限定する必要はなく、３段以上の多段接続につ
いても同様にできることはもちろんである。Therefore, the first semiconductor chip 1A and the second semiconductor chip 1B can be placed close to each other. the result,
The frequency characteristics of the amplification gain of the two-stage amplifier circuit can be made extremely wide-band. Moreover, since circuit loss caused by the MIC line of the external circuit and the chip capacitor for direct current isolation between stages can be completely eliminated, the amplification gain of the entire circuit can be increased and the circuit size and weight can be reduced. In the above embodiments, the case of a two-stage amplification element in which two semiconductor chips are connected in cascade has been described, but there is no need to limit it to this, and it is of course possible to perform multi-stage connection of three or more stages in the same way. .
また、以上の実施例では砒素ガリウム電界効果トランジ
スタを例にとつて説明したが、これに限定するものでは
なく、他のマイクロ波電力用ＦＥＴ，．ＭＯＳトランジ
スタ、薄膜トランジスタなどの半導体装置にも同様にで
きることはもちろんである。以上、詳細に説明したよう
に、この発明に係る半導体装置によれば段間の回路寸法
を飛躍的に短縮することができる。Further, although the above embodiments have been explained using an arsenide gallium field effect transistor as an example, the present invention is not limited to this, and other microwave power FETs, . Of course, the same can be applied to semiconductor devices such as MOS transistors and thin film transistors. As described above in detail, according to the semiconductor device according to the present invention, the circuit size between stages can be dramatically shortened.
この結果、増幅回路全体の重量の軽量と寸法の小型化が
できると共に、多段増幅回路の増幅利得が向上し、かつ
増幅利得の周波数特性を極めて広帯域にすることができ
るなどの効果がある。As a result, the overall weight and size of the amplifier circuit can be reduced, the amplification gain of the multistage amplifier circuit can be improved, and the frequency characteristics of the amplification gain can be made extremely broadband.
第１図は従来の内部整合化多段増幅用の半導体装置を示
す要部斜視図、第２図は内部整合化一段ＧａＡｓＦＥＴ
を２段カスケード接続した従来の２段増幅回路構成を示
す要部を示す平面図、第３図はこの発明に係る半導体装
置の一実施例を示す要部斜視図、第４図は第３図の等価
回路を示す図である。
１・・・・・・半導体チップ、２・・・・・・入力整合
用キャパシタ電極、３・・・・・・第１の誘電体基板、
４・・・・・・出力整合用キャパシタ電極、５・・・・
・・第２の誘電体基板、６・・・・・・接地用金属基板
、７・・・・・・ゲート電極バッド、８・・・・・・第
１のボンディングワイヤ、９・・゜第１のセラミック基
板、１０・・・・・・第１の分布定数・線路、１１・・
・・・・第２のボンディングワイヤ、１２・・・・ドレ
イン電極、１３・・・・・・第３のボンディングワイヤ
、１４・・・・・・第２のセラミック基板、１５・・・
・第２の分布定数線路、１６・・・・・・第４のボンデ
ィングワイヤ、１７・・・・・・セラミック基板、１８
・・ＭＩＣ線路、１９および２０・・・・・・バイアス
回路、２１・・・・・スリット、２２・・・・・・チッ
プコンデンサ、２３・・・・・・ソース電極バッド、２
４・・・・・・ドレイン電極バッド、２５・・・・・・
第３の誘電体基板、２６・・・・・・第１のキャパシタ
ンス電極、２７・・・・・・第１のドレイノン電極バッ
ド、２８・・・・・・第５のボンディングワイヤ、２９
・・・・・・第２のキャパシタンス電極、３０・・・・
・・第２のゲート電極バッド、３１・・・・・・第６の
ボンディングワイヤ、３２・・・・・スリット部、３３
・・・ドレインバイアス端子、３４・・・・・・ボンデ
イングワイヤ、３５・・・・・・ゲートバイアス端子、
３６・・・・・・ボンディングワイヤ。Figure 1 is a perspective view of the main parts of a conventional internally matched multi-stage amplification semiconductor device, and Figure 2 is an internally matched single-stage GaAsFET.
FIG. 3 is a perspective view of essential parts showing an embodiment of a semiconductor device according to the present invention, and FIG. It is a figure showing an equivalent circuit of. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 2... Capacitor electrode for input matching, 3... First dielectric substrate,
4... Capacitor electrode for output matching, 5...
...Second dielectric substrate, 6...Grounding metal substrate, 7...Gate electrode pad, 8...First bonding wire, 9...゜th 1 ceramic substrate, 10...first distributed constant/line, 11...
... Second bonding wire, 12 ... Drain electrode, 13 ... Third bonding wire, 14 ... Second ceramic substrate, 15 ...
- Second distributed constant line, 16... Fourth bonding wire, 17... Ceramic substrate, 18
...MIC line, 19 and 20...Bias circuit, 21...Slit, 22...Chip capacitor, 23...Source electrode pad, 2
4...Drain electrode pad, 25...
Third dielectric substrate, 26... First capacitance electrode, 27... First drainon electrode pad, 28... Fifth bonding wire, 29
...Second capacitance electrode, 30...
...Second gate electrode pad, 31...Sixth bonding wire, 32...Slit portion, 33
...Drain bias terminal, 34...Bonding wire, 35...Gate bias terminal,
36...Bonding wire.
Claims (1)
する内部整合化多段増幅用の半導体装置において、前段
の出力整合回路を構成する第１の集中定数キャパシタン
ス電極と後段の入力整合回路を構成する第２の集中定数
キャパシタンス電極とを同一の誘電体基板上に形成し、
かつ第１の集中定数キャパシタンス電極と第２の集中定
数キャパシタンス電極とを幅の細いスリット部をはさん
で配設することを特徴とする半導体装置。1. In a semiconductor device for internal matching multi-stage amplification in which a plurality of three-terminal semiconductor chips are connected in multi-stage cascade, a first lumped constant capacitance electrode constitutes an output matching circuit in the preceding stage and a second lumped constant capacitance electrode constitutes an input matching circuit in the succeeding stage. lumped constant capacitance electrodes are formed on the same dielectric substrate,
A semiconductor device characterized in that the first lumped constant capacitance electrode and the second lumped constant capacitance electrode are arranged with a narrow slit section in between.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55139475A JPS6043021B2 (en) | 1980-10-03 | 1980-10-03 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55139475A JPS6043021B2 (en) | 1980-10-03 | 1980-10-03 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5762547A JPS5762547A (en) | 1982-04-15 |
| JPS6043021B2 true JPS6043021B2 (en) | 1985-09-26 |
Family
ID=15246103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55139475A Expired JPS6043021B2 (en) | 1980-10-03 | 1980-10-03 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6043021B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4423388A (en) * | 1981-10-29 | 1983-12-27 | Watkins-Johnson Company | RF Amplifier circuit employing FET devices |
| JP5439415B2 (en) * | 2011-03-01 | 2014-03-12 | 株式会社東芝 | Package for MMIC |
-
1980
- 1980-10-03 JP JP55139475A patent/JPS6043021B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5762547A (en) | 1982-04-15 |
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